mod compiler;
mod graph;
mod layout;
mod registration;
pub use compiler::{ExecStep, ExecutionPlan, InputSlot};
pub use graph::{
exposed_port_key, Connection, ExposedPortMeta, FindTerminalError, Graph, GraphError, NodeId,
NodeInstance, PortDef, PortDir, PortRef, UnitType,
};
pub use layout::NodeLayout;
pub use registration::NodeRegistration;
pub trait WireKind:
Copy + Eq + std::hash::Hash + std::fmt::Debug + serde::Serialize + for<'de> serde::Deserialize<'de>
{
fn compatible(from: Self, to: Self) -> bool;
}
pub use compiler::compile;
#[cfg(test)]
pub(crate) mod tests {
use super::WireKind;
use serde::{Deserialize, Serialize};
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub enum TestWireKind {
Scalar,
Color,
}
impl WireKind for TestWireKind {
fn compatible(from: Self, to: Self) -> bool {
from == to
}
}
}