da1470x_pac/
dcache.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:52 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"DCACHE registers"]
28unsafe impl ::core::marker::Send for super::Dcache {}
29unsafe impl ::core::marker::Sync for super::Dcache {}
30impl super::Dcache {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Dcache base address for cacheable region"]
38    #[inline(always)]
39    pub const fn dcache_base_addr_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::DcacheBaseAddrReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::DcacheBaseAddrReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(4usize),
45            )
46        }
47    }
48
49    #[doc = "Dcache Control register"]
50    #[inline(always)]
51    pub const fn dcache_ctrl_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::DcacheCtrlReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::DcacheCtrlReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "Dcache MRM (Miss Rate Monitor) CONTROL register"]
62    #[inline(always)]
63    pub const fn dcache_mrm_ctrl_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::DcacheMrmCtrlReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::DcacheMrmCtrlReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(20usize),
69            )
70        }
71    }
72
73    #[doc = "Dcache MRM (Miss Rate Monitor) EVICTS register"]
74    #[inline(always)]
75    pub const fn dcache_mrm_evicts_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::DcacheMrmEvictsReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::DcacheMrmEvictsReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(16usize),
81            )
82        }
83    }
84
85    #[doc = "Dcache MRM (Miss Rate Monitor) EVICTS THRESHOLD register"]
86    #[inline(always)]
87    pub const fn dcache_mrm_evicts_thres_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::DcacheMrmEvictsThresReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::DcacheMrmEvictsThresReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(36usize),
93            )
94        }
95    }
96
97    #[doc = "Dcache MRM (Miss Rate Monitor) HITS register"]
98    #[inline(always)]
99    pub const fn dcache_mrm_hits_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::DcacheMrmHitsReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::DcacheMrmHitsReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(8usize),
105            )
106        }
107    }
108
109    #[doc = "Dcache MRM (Miss Rate Monitor) HITS THRESHOLD register"]
110    #[inline(always)]
111    pub const fn dcache_mrm_hits_thres_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::DcacheMrmHitsThresReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::DcacheMrmHitsThresReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(32usize),
117            )
118        }
119    }
120
121    #[doc = "Dcache MRM (Miss Rate Monitor) MISSES register"]
122    #[inline(always)]
123    pub const fn dcache_mrm_misses_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::DcacheMrmMissesReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::DcacheMrmMissesReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(12usize),
129            )
130        }
131    }
132
133    #[doc = "Dcache MRM (Miss Rate Monitor) THRESHOLD register"]
134    #[inline(always)]
135    pub const fn dcache_mrm_misses_thres_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::DcacheMrmMissesThresReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::DcacheMrmMissesThresReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(28usize),
141            )
142        }
143    }
144
145    #[doc = "Dcache MRM (Miss Rate Monitor) TIME INTERVAL register"]
146    #[inline(always)]
147    pub const fn dcache_mrm_tint_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::DcacheMrmTintReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::DcacheMrmTintReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(24usize),
153            )
154        }
155    }
156}
157#[doc(hidden)]
158#[derive(Copy, Clone, Eq, PartialEq)]
159pub struct DcacheBaseAddrReg_SPEC;
160impl crate::sealed::RegSpec for DcacheBaseAddrReg_SPEC {
161    type DataType = u32;
162}
163
164#[doc = "Dcache base address for cacheable region"]
165pub type DcacheBaseAddrReg = crate::RegValueT<DcacheBaseAddrReg_SPEC>;
166
167impl DcacheBaseAddrReg {
168    #[doc = "Base of PSRAM cacheable memory\nN*1kByte. N = 0 to 131072 (max. of 128 MByte)."]
169    #[inline(always)]
170    pub fn dcache_base_addr(
171        self,
172    ) -> crate::common::RegisterField<
173        0,
174        0x1ffff,
175        1,
176        0,
177        u32,
178        u32,
179        DcacheBaseAddrReg_SPEC,
180        crate::common::RW,
181    > {
182        crate::common::RegisterField::<
183            0,
184            0x1ffff,
185            1,
186            0,
187            u32,
188            u32,
189            DcacheBaseAddrReg_SPEC,
190            crate::common::RW,
191        >::from_register(self, 0)
192    }
193}
194impl ::core::default::Default for DcacheBaseAddrReg {
195    #[inline(always)]
196    fn default() -> DcacheBaseAddrReg {
197        <crate::RegValueT<DcacheBaseAddrReg_SPEC> as RegisterValue<_>>::new(0)
198    }
199}
200
201#[doc(hidden)]
202#[derive(Copy, Clone, Eq, PartialEq)]
203pub struct DcacheCtrlReg_SPEC;
204impl crate::sealed::RegSpec for DcacheCtrlReg_SPEC {
205    type DataType = u32;
206}
207
208#[doc = "Dcache Control register"]
209pub type DcacheCtrlReg = crate::RegValueT<DcacheCtrlReg_SPEC>;
210
211impl DcacheCtrlReg {
212    #[doc = "Disable the clockgating for the DCACHE\n0: Enable clockgating (default)\n1: Disable clockgating"]
213    #[inline(always)]
214    pub fn dcache_disable_clkgate(
215        self,
216    ) -> crate::common::RegisterFieldBool<25, 1, 0, DcacheCtrlReg_SPEC, crate::common::RW> {
217        crate::common::RegisterFieldBool::<25,1,0,DcacheCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
218    }
219
220    #[doc = "Write buffer flush\n0: Write buffer isn\'t flushed (default)\n1: Write buffer is flushed"]
221    #[inline(always)]
222    pub fn dcache_wbuffer_flush(
223        self,
224    ) -> crate::common::RegisterFieldBool<24, 1, 0, DcacheCtrlReg_SPEC, crate::common::RW> {
225        crate::common::RegisterFieldBool::<24,1,0,DcacheCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
226    }
227
228    #[doc = "Status of the write buffer\n0: Write buffer isn\'t empty\n1: Write buffer is empty"]
229    #[inline(always)]
230    pub fn dcache_wbuffer_empty(
231        self,
232    ) -> crate::common::RegisterFieldBool<23, 1, 0, DcacheCtrlReg_SPEC, crate::common::R> {
233        crate::common::RegisterFieldBool::<23,1,0,DcacheCtrlReg_SPEC,crate::common::R>::from_register(self,0)
234    }
235
236    #[doc = "0: DCACHE is not write flushed yet.\n1: DCACHE is write flushed.\n\nNote 1: Setting and clearing of this (status) bit field is automatically done by the hardware.\nNote 2: The CACHE_WFLUSHED bit can also be cleared first by the software by writing a \'0\'"]
237    #[inline(always)]
238    pub fn dcache_wflushed(
239        self,
240    ) -> crate::common::RegisterFieldBool<22, 1, 0, DcacheCtrlReg_SPEC, crate::common::RW> {
241        crate::common::RegisterFieldBool::<22,1,0,DcacheCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
242    }
243
244    #[doc = "0: DCACHE isn\'t initialized yet\n1: DCACHE initialization has been completed"]
245    #[inline(always)]
246    pub fn dcache_ready(
247        self,
248    ) -> crate::common::RegisterFieldBool<21, 1, 0, DcacheCtrlReg_SPEC, crate::common::R> {
249        crate::common::RegisterFieldBool::<21,1,0,DcacheCtrlReg_SPEC,crate::common::R>::from_register(self,0)
250    }
251
252    #[doc = "Write a \'1\' to this field will trigger a write flush of the \'dirty\' lines. All modified data in \'dirty\' line will be written back to the PSRAM. The corresponding \'dirty\' bits will be cleared. Reading this bit will return \'0\'"]
253    #[inline(always)]
254    pub fn dcache_wflush(
255        self,
256    ) -> crate::common::RegisterFieldBool<20, 1, 0, DcacheCtrlReg_SPEC, crate::common::W> {
257        crate::common::RegisterFieldBool::<20,1,0,DcacheCtrlReg_SPEC,crate::common::W>::from_register(self,0)
258    }
259
260    #[doc = "Write a \'1\' to this field will trigger an initialization of the cache (\'0\'s are written in the TAG area).. Reading from this field will always return \'0\'"]
261    #[inline(always)]
262    pub fn dcache_init(
263        self,
264    ) -> crate::common::RegisterFieldBool<19, 1, 0, DcacheCtrlReg_SPEC, crate::common::W> {
265        crate::common::RegisterFieldBool::<19,1,0,DcacheCtrlReg_SPEC,crate::common::W>::from_register(self,0)
266    }
267
268    #[doc = "Enable the dcache controller HW block:\n0: Disabled, all AHB accesses towards the QSPI are bypassing the HW block straight into the PSRAM\n1: Enabled, all AHB access towards the QSPI within the cacheable region are cached."]
269    #[inline(always)]
270    pub fn dcache_enable(
271        self,
272    ) -> crate::common::RegisterFieldBool<18, 1, 0, DcacheCtrlReg_SPEC, crate::common::RW> {
273        crate::common::RegisterFieldBool::<18,1,0,DcacheCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
274    }
275
276    #[doc = "Length of PSRAM cacheable memory\nN*1kByte. N = 0 to 131072 (max. of 128 MByte).\nSetting DCACHE_LEN=0 disables the caching."]
277    #[inline(always)]
278    pub fn dcache_len(
279        self,
280    ) -> crate::common::RegisterField<
281        0,
282        0x3ffff,
283        1,
284        0,
285        u32,
286        u32,
287        DcacheCtrlReg_SPEC,
288        crate::common::RW,
289    > {
290        crate::common::RegisterField::<
291            0,
292            0x3ffff,
293            1,
294            0,
295            u32,
296            u32,
297            DcacheCtrlReg_SPEC,
298            crate::common::RW,
299        >::from_register(self, 0)
300    }
301}
302impl ::core::default::Default for DcacheCtrlReg {
303    #[inline(always)]
304    fn default() -> DcacheCtrlReg {
305        <crate::RegValueT<DcacheCtrlReg_SPEC> as RegisterValue<_>>::new(8388608)
306    }
307}
308
309#[doc(hidden)]
310#[derive(Copy, Clone, Eq, PartialEq)]
311pub struct DcacheMrmCtrlReg_SPEC;
312impl crate::sealed::RegSpec for DcacheMrmCtrlReg_SPEC {
313    type DataType = u32;
314}
315
316#[doc = "Dcache MRM (Miss Rate Monitor) CONTROL register"]
317pub type DcacheMrmCtrlReg = crate::RegValueT<DcacheMrmCtrlReg_SPEC>;
318
319impl DcacheMrmCtrlReg {
320    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache evicts reached the programmed threshold (threshold != 0)."]
321    #[inline(always)]
322    pub fn mrm_irq_evicts_thres_status(
323        self,
324    ) -> crate::common::RegisterFieldBool<5, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
325        crate::common::RegisterFieldBool::<5,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
326    }
327
328    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache hits reached the programmed threshold (threshold != 0)."]
329    #[inline(always)]
330    pub fn mrm_irq_hits_thres_status(
331        self,
332    ) -> crate::common::RegisterFieldBool<4, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
333        crate::common::RegisterFieldBool::<4,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
334    }
335
336    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0)."]
337    #[inline(always)]
338    pub fn mrm_irq_misses_thres_status(
339        self,
340    ) -> crate::common::RegisterFieldBool<3, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
341        crate::common::RegisterFieldBool::<3,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
342    }
343
344    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0)."]
345    #[inline(always)]
346    pub fn mrm_irq_tint_status(
347        self,
348    ) -> crate::common::RegisterFieldBool<2, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
349        crate::common::RegisterFieldBool::<2,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
350    }
351
352    #[doc = "0: Disables interrupt generation.\n1: Enables interrupt generation.\nNote: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,"]
353    #[inline(always)]
354    pub fn mrm_irq_mask(
355        self,
356    ) -> crate::common::RegisterFieldBool<1, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
357        crate::common::RegisterFieldBool::<1,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
358    }
359
360    #[doc = "0: Freeze the \"misses/hits\" counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG.\n1: Enables the counters.\nNote: In case CACHE_MRM_CTRL_REG\\[MRM_START\\] is set to \'1\' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it\'s \'0\'. At that time CACHE_MRM_CTRL_REG\\[MRM_START\\] will be reset automatically to \'0\' by the MRM hardware and the MRM interrupt will be generated."]
361    #[inline(always)]
362    pub fn mrm_start(
363        self,
364    ) -> crate::common::RegisterFieldBool<0, 1, 0, DcacheMrmCtrlReg_SPEC, crate::common::RW> {
365        crate::common::RegisterFieldBool::<0,1,0,DcacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
366    }
367}
368impl ::core::default::Default for DcacheMrmCtrlReg {
369    #[inline(always)]
370    fn default() -> DcacheMrmCtrlReg {
371        <crate::RegValueT<DcacheMrmCtrlReg_SPEC> as RegisterValue<_>>::new(0)
372    }
373}
374
375#[doc(hidden)]
376#[derive(Copy, Clone, Eq, PartialEq)]
377pub struct DcacheMrmEvictsReg_SPEC;
378impl crate::sealed::RegSpec for DcacheMrmEvictsReg_SPEC {
379    type DataType = u32;
380}
381
382#[doc = "Dcache MRM (Miss Rate Monitor) EVICTS register"]
383pub type DcacheMrmEvictsReg = crate::RegValueT<DcacheMrmEvictsReg_SPEC>;
384
385impl DcacheMrmEvictsReg {
386    #[doc = "Contains the amount of cache evicts"]
387    #[inline(always)]
388    pub fn mrm_evicts(
389        self,
390    ) -> crate::common::RegisterField<
391        0,
392        0xffffffff,
393        1,
394        0,
395        u32,
396        u32,
397        DcacheMrmEvictsReg_SPEC,
398        crate::common::RW,
399    > {
400        crate::common::RegisterField::<
401            0,
402            0xffffffff,
403            1,
404            0,
405            u32,
406            u32,
407            DcacheMrmEvictsReg_SPEC,
408            crate::common::RW,
409        >::from_register(self, 0)
410    }
411}
412impl ::core::default::Default for DcacheMrmEvictsReg {
413    #[inline(always)]
414    fn default() -> DcacheMrmEvictsReg {
415        <crate::RegValueT<DcacheMrmEvictsReg_SPEC> as RegisterValue<_>>::new(0)
416    }
417}
418
419#[doc(hidden)]
420#[derive(Copy, Clone, Eq, PartialEq)]
421pub struct DcacheMrmEvictsThresReg_SPEC;
422impl crate::sealed::RegSpec for DcacheMrmEvictsThresReg_SPEC {
423    type DataType = u32;
424}
425
426#[doc = "Dcache MRM (Miss Rate Monitor) EVICTS THRESHOLD register"]
427pub type DcacheMrmEvictsThresReg = crate::RegValueT<DcacheMrmEvictsThresReg_SPEC>;
428
429impl DcacheMrmEvictsThresReg {
430    #[doc = "Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_EVICTS_THRES_STATUS\\].\nNote: When MRM_EVICTS_THRES=0 (unrealistic value), no interrupt will be generated."]
431    #[inline(always)]
432    pub fn mrm_evicts_thres(
433        self,
434    ) -> crate::common::RegisterField<
435        0,
436        0xffffffff,
437        1,
438        0,
439        u32,
440        u32,
441        DcacheMrmEvictsThresReg_SPEC,
442        crate::common::RW,
443    > {
444        crate::common::RegisterField::<
445            0,
446            0xffffffff,
447            1,
448            0,
449            u32,
450            u32,
451            DcacheMrmEvictsThresReg_SPEC,
452            crate::common::RW,
453        >::from_register(self, 0)
454    }
455}
456impl ::core::default::Default for DcacheMrmEvictsThresReg {
457    #[inline(always)]
458    fn default() -> DcacheMrmEvictsThresReg {
459        <crate::RegValueT<DcacheMrmEvictsThresReg_SPEC> as RegisterValue<_>>::new(0)
460    }
461}
462
463#[doc(hidden)]
464#[derive(Copy, Clone, Eq, PartialEq)]
465pub struct DcacheMrmHitsReg_SPEC;
466impl crate::sealed::RegSpec for DcacheMrmHitsReg_SPEC {
467    type DataType = u32;
468}
469
470#[doc = "Dcache MRM (Miss Rate Monitor) HITS register"]
471pub type DcacheMrmHitsReg = crate::RegValueT<DcacheMrmHitsReg_SPEC>;
472
473impl DcacheMrmHitsReg {
474    #[doc = "Contains the amount of cache hits."]
475    #[inline(always)]
476    pub fn mrm_hits(
477        self,
478    ) -> crate::common::RegisterField<
479        0,
480        0xffffffff,
481        1,
482        0,
483        u32,
484        u32,
485        DcacheMrmHitsReg_SPEC,
486        crate::common::RW,
487    > {
488        crate::common::RegisterField::<
489            0,
490            0xffffffff,
491            1,
492            0,
493            u32,
494            u32,
495            DcacheMrmHitsReg_SPEC,
496            crate::common::RW,
497        >::from_register(self, 0)
498    }
499}
500impl ::core::default::Default for DcacheMrmHitsReg {
501    #[inline(always)]
502    fn default() -> DcacheMrmHitsReg {
503        <crate::RegValueT<DcacheMrmHitsReg_SPEC> as RegisterValue<_>>::new(0)
504    }
505}
506
507#[doc(hidden)]
508#[derive(Copy, Clone, Eq, PartialEq)]
509pub struct DcacheMrmHitsThresReg_SPEC;
510impl crate::sealed::RegSpec for DcacheMrmHitsThresReg_SPEC {
511    type DataType = u32;
512}
513
514#[doc = "Dcache MRM (Miss Rate Monitor) HITS THRESHOLD register"]
515pub type DcacheMrmHitsThresReg = crate::RegValueT<DcacheMrmHitsThresReg_SPEC>;
516
517impl DcacheMrmHitsThresReg {
518    #[doc = "Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_HITS_THRES_STATUS\\].\nNote: When MRM_HITS_THRES=0 (unrealistic value), no interrupt will be generated."]
519    #[inline(always)]
520    pub fn mrm_hits_thres(
521        self,
522    ) -> crate::common::RegisterField<
523        0,
524        0xffffffff,
525        1,
526        0,
527        u32,
528        u32,
529        DcacheMrmHitsThresReg_SPEC,
530        crate::common::RW,
531    > {
532        crate::common::RegisterField::<
533            0,
534            0xffffffff,
535            1,
536            0,
537            u32,
538            u32,
539            DcacheMrmHitsThresReg_SPEC,
540            crate::common::RW,
541        >::from_register(self, 0)
542    }
543}
544impl ::core::default::Default for DcacheMrmHitsThresReg {
545    #[inline(always)]
546    fn default() -> DcacheMrmHitsThresReg {
547        <crate::RegValueT<DcacheMrmHitsThresReg_SPEC> as RegisterValue<_>>::new(0)
548    }
549}
550
551#[doc(hidden)]
552#[derive(Copy, Clone, Eq, PartialEq)]
553pub struct DcacheMrmMissesReg_SPEC;
554impl crate::sealed::RegSpec for DcacheMrmMissesReg_SPEC {
555    type DataType = u32;
556}
557
558#[doc = "Dcache MRM (Miss Rate Monitor) MISSES register"]
559pub type DcacheMrmMissesReg = crate::RegValueT<DcacheMrmMissesReg_SPEC>;
560
561impl DcacheMrmMissesReg {
562    #[doc = "Contains the amount of cache misses."]
563    #[inline(always)]
564    pub fn mrm_misses(
565        self,
566    ) -> crate::common::RegisterField<
567        0,
568        0xffffffff,
569        1,
570        0,
571        u32,
572        u32,
573        DcacheMrmMissesReg_SPEC,
574        crate::common::RW,
575    > {
576        crate::common::RegisterField::<
577            0,
578            0xffffffff,
579            1,
580            0,
581            u32,
582            u32,
583            DcacheMrmMissesReg_SPEC,
584            crate::common::RW,
585        >::from_register(self, 0)
586    }
587}
588impl ::core::default::Default for DcacheMrmMissesReg {
589    #[inline(always)]
590    fn default() -> DcacheMrmMissesReg {
591        <crate::RegValueT<DcacheMrmMissesReg_SPEC> as RegisterValue<_>>::new(0)
592    }
593}
594
595#[doc(hidden)]
596#[derive(Copy, Clone, Eq, PartialEq)]
597pub struct DcacheMrmMissesThresReg_SPEC;
598impl crate::sealed::RegSpec for DcacheMrmMissesThresReg_SPEC {
599    type DataType = u32;
600}
601
602#[doc = "Dcache MRM (Miss Rate Monitor) THRESHOLD register"]
603pub type DcacheMrmMissesThresReg = crate::RegValueT<DcacheMrmMissesThresReg_SPEC>;
604
605impl DcacheMrmMissesThresReg {
606    #[doc = "Defines the misses threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_MISSES_THRES_STATUS\\].\nNote: When MRM_MISSES_THRES=0 (unrealistic value), no interrupt will be generated."]
607    #[inline(always)]
608    pub fn mrm_misses_thres(
609        self,
610    ) -> crate::common::RegisterField<
611        0,
612        0xffffffff,
613        1,
614        0,
615        u32,
616        u32,
617        DcacheMrmMissesThresReg_SPEC,
618        crate::common::RW,
619    > {
620        crate::common::RegisterField::<
621            0,
622            0xffffffff,
623            1,
624            0,
625            u32,
626            u32,
627            DcacheMrmMissesThresReg_SPEC,
628            crate::common::RW,
629        >::from_register(self, 0)
630    }
631}
632impl ::core::default::Default for DcacheMrmMissesThresReg {
633    #[inline(always)]
634    fn default() -> DcacheMrmMissesThresReg {
635        <crate::RegValueT<DcacheMrmMissesThresReg_SPEC> as RegisterValue<_>>::new(0)
636    }
637}
638
639#[doc(hidden)]
640#[derive(Copy, Clone, Eq, PartialEq)]
641pub struct DcacheMrmTintReg_SPEC;
642impl crate::sealed::RegSpec for DcacheMrmTintReg_SPEC {
643    type DataType = u32;
644}
645
646#[doc = "Dcache MRM (Miss Rate Monitor) TIME INTERVAL register"]
647pub type DcacheMrmTintReg = crate::RegValueT<DcacheMrmTintReg_SPEC>;
648
649impl DcacheMrmTintReg {
650    #[doc = "Defines the time interval for the monitoring in 32 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_TINT_STATUS\\].\nNote: When MRM_TINT=0 (unrealistic value), no interrupt will be generated."]
651    #[inline(always)]
652    pub fn mrm_tint(
653        self,
654    ) -> crate::common::RegisterField<
655        0,
656        0x7ffff,
657        1,
658        0,
659        u32,
660        u32,
661        DcacheMrmTintReg_SPEC,
662        crate::common::RW,
663    > {
664        crate::common::RegisterField::<
665            0,
666            0x7ffff,
667            1,
668            0,
669            u32,
670            u32,
671            DcacheMrmTintReg_SPEC,
672            crate::common::RW,
673        >::from_register(self, 0)
674    }
675}
676impl ::core::default::Default for DcacheMrmTintReg {
677    #[inline(always)]
678    fn default() -> DcacheMrmTintReg {
679        <crate::RegValueT<DcacheMrmTintReg_SPEC> as RegisterValue<_>>::new(0)
680    }
681}
da1470x_pac/dcache.rs

da1470x_pac/
dcache.rs
