da1470x_pac/
cache.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:52 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"CACHE registers"]
28unsafe impl ::core::marker::Send for super::Cache {}
29unsafe impl ::core::marker::Sync for super::Cache {}
30impl super::Cache {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Cache control register 2 (only Word (32-bits) access supported)."]
38    #[inline(always)]
39    pub const fn cache_ctrl2_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::CacheCtrl2Reg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::CacheCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(32usize),
45            )
46        }
47    }
48
49    #[doc = "Cache QSPI Flash program size and base address register (only Word (32-bits) access supported)."]
50    #[inline(always)]
51    pub const fn cache_flash_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::CacheFlashReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::CacheFlashReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(64usize),
57            )
58        }
59    }
60
61    #[doc = "Cache MRM (Miss Rate Monitor) CONTROL register (only Word (32-bits) access supported)."]
62    #[inline(always)]
63    pub const fn cache_mrm_ctrl_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::CacheMrmCtrlReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::CacheMrmCtrlReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(48usize),
69            )
70        }
71    }
72
73    #[doc = "Cache MRM (Miss Rate Monitor) HITS with 1 Wait State register (only Word (32-bits) access supported)."]
74    #[inline(always)]
75    pub const fn cache_mrm_hits1ws_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::CacheMrmHits1WsReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::CacheMrmHits1WsReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(72usize),
81            )
82        }
83    }
84
85    #[doc = "Cache MRM (Miss Rate Monitor) HITS register (only Word (32-bits) access supported)."]
86    #[inline(always)]
87    pub const fn cache_mrm_hits_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::CacheMrmHitsReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::CacheMrmHitsReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(40usize),
93            )
94        }
95    }
96
97    #[doc = "Cache MRM (Miss Rate Monitor) HITS THRESHOLD register (only Word (32-bits) access supported)."]
98    #[inline(always)]
99    pub const fn cache_mrm_hits_thres_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::CacheMrmHitsThresReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::CacheMrmHitsThresReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(60usize),
105            )
106        }
107    }
108
109    #[doc = "Cache MRM (Miss Rate Monitor) MISSES register (only Word (32-bits) access supported)."]
110    #[inline(always)]
111    pub const fn cache_mrm_misses_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::CacheMrmMissesReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::CacheMrmMissesReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(44usize),
117            )
118        }
119    }
120
121    #[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register (only Word (32-bits) access supported)."]
122    #[inline(always)]
123    pub const fn cache_mrm_misses_thres_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::CacheMrmMissesThresReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::CacheMrmMissesThresReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(56usize),
129            )
130        }
131    }
132
133    #[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register (only Word (32-bits) access supported)."]
134    #[inline(always)]
135    pub const fn cache_mrm_tint_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::CacheMrmTintReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::CacheMrmTintReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(52usize),
141            )
142        }
143    }
144
145    #[doc = "SWD HW reset control register (only Word (32-bits) access supported)."]
146    #[inline(always)]
147    pub const fn swd_reset_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::SwdResetReg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::SwdResetReg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(80usize),
153            )
154        }
155    }
156}
157#[doc(hidden)]
158#[derive(Copy, Clone, Eq, PartialEq)]
159pub struct CacheCtrl2Reg_SPEC;
160impl crate::sealed::RegSpec for CacheCtrl2Reg_SPEC {
161    type DataType = u32;
162}
163
164#[doc = "Cache control register 2 (only Word (32-bits) access supported)."]
165pub type CacheCtrl2Reg = crate::RegValueT<CacheCtrl2Reg_SPEC>;
166
167impl CacheCtrl2Reg {
168    #[doc = "Cache Controller RO status bit.\n0: Default.\n1: Set to \'1\' when CACHE_CTRL is enabled, initialized and immediately ready for a cacheable access to service."]
169    #[inline(always)]
170    pub fn cache_ready(
171        self,
172    ) -> crate::common::RegisterFieldBool<21, 1, 0, CacheCtrl2Reg_SPEC, crate::common::R> {
173        crate::common::RegisterFieldBool::<21,1,0,CacheCtrl2Reg_SPEC,crate::common::R>::from_register(self,0)
174    }
175
176    #[doc = "Cache Controller RO status bit.\n0: Default.\n1: Set to \'1\' when SRAM is being initialized (i.e. being flushed).\nNote: The flushing of the cache memory takes 256 HCLK cycles."]
177    #[inline(always)]
178    pub fn cache_ram_init(
179        self,
180    ) -> crate::common::RegisterFieldBool<20, 1, 0, CacheCtrl2Reg_SPEC, crate::common::R> {
181        crate::common::RegisterFieldBool::<20,1,0,CacheCtrl2Reg_SPEC,crate::common::R>::from_register(self,0)
182    }
183
184    #[doc = "0: Cache is not flushed yet.\n1: Cache is flushed.\n\nNote 1: Setting and clearing of this (status) bit field is automatically done by the hardware. It is set on the falling edge and cleared on the rising edge of the (Cache Controller) CACHE_RAM_INIT signal.\nNote 2: When the Cache is flushed by disabling and enabling the Cache Controller with a SYS_CTRL_REG\\[CACHERAM_MUX\\] sequence of 1 -> 0 -> 1, the CACHE_FLUSHED bit can also be cleared first by the software (if needed) with writing a CACHE_CTRL2_REG(CACHE_FLUSHED) sequence of 1 -> 0. This is needed when the software uses the CACHE_FLUSHED bit as a status bit to wait for (e.g. in a while-loop)."]
185    #[inline(always)]
186    pub fn cache_flushed(
187        self,
188    ) -> crate::common::RegisterFieldBool<19, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
189        crate::common::RegisterFieldBool::<19,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
190    }
191
192    #[doc = "0: Default.\n1: Flushing of the Cache memory is disabled when SYS_CTRL_REG\\[CACHERAM_MUX\\] is switched from \'1\' to \'0\'.\n\nNote: Setting this bit to \'1\' is only allowed for debugging purposes."]
193    #[inline(always)]
194    pub fn cache_flush_disable(
195        self,
196    ) -> crate::common::RegisterFieldBool<18, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
197        crate::common::RegisterFieldBool::<18,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
198    }
199
200    #[doc = "00: CACHERAM (mirrored) read/write and NO use of the full 184 bits databus (for executing program code or extension of the SysRAM with the Cache RAM).\nIn this mode 8 bits, 16 bits and 32 bits write access is supported.\n\n01: CACHERAM (mirrored) read and use of the full 184 bits databus of \'SRAM_1_0\' (for testing and debugging purposes).\nIn this mode only 32 bits write access is supported.\n\n10: CACHERAM (mirrored) read and use of the full 184 bits databus of \'SRAM_3_2\' (for testing and debugging purposes).\nIn this mode only 32 bits write access is supported.\n\n11: Reserved.\n\nNote 1: SYS_CTRL_REG\\[CACHERAM_MUX\\] must be set to \'0\' before accessing the memory mapped (mirrored) Cache Data and TAG memory.\nNote 2: For all 3 settings, max. 8 KByte is available from the memory map."]
201    #[inline(always)]
202    pub fn cache_use_full_db_range(
203        self,
204    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, CacheCtrl2Reg_SPEC, crate::common::RW>
205    {
206        crate::common::RegisterField::<16,0x3,1,0,u8,u8,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
207    }
208
209    #[doc = "0: Default.\n1: The \"m_HCLK_EN\" input is ignored and the controller avoids inserting m_HTRANS=BUSY because of wait states.\n\nNote:\nThis bit is only relevant for executing from QSPI Flash (when set to \'1\' it will improve performance). This bit should be kept on \'0\' for executing from eFlash."]
210    #[inline(always)]
211    pub fn cache_mhclken_disable(
212        self,
213    ) -> crate::common::RegisterFieldBool<15, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
214        crate::common::RegisterFieldBool::<15,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
215    }
216
217    #[doc = "0: Default.\n1: The cache line refill is performed with INCR type burst and \"Critical Word First\" is disabled.\n\nNote:\nThis bit is only relevant for executing from QSPI Flash (when set to \'1\' it will improve performance).This bit should be kept on \'0\' for executing from eFlash."]
218    #[inline(always)]
219    pub fn cache_cwf_disable(
220        self,
221    ) -> crate::common::RegisterFieldBool<14, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
222        crate::common::RegisterFieldBool::<14,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
223    }
224
225    #[doc = "0: Cache controller clock gating is not enabled.\n1: Cache controller clock gating is enabled (enabling power saving)."]
226    #[inline(always)]
227    pub fn cache_cgen(
228        self,
229    ) -> crate::common::RegisterFieldBool<13, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
230        crate::common::RegisterFieldBool::<13,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
231    }
232
233    #[doc = "0: Cache Data and TAG memory read only.\n1: Cache Data and TAG memory read/write.\nThe Data and TAG memory are only updated by the cache controller.\nThere is no HW protection to prevent unauthorized access by the ARM.\nNote 1: When accessing the memory mapped Cache Data and TAG memory (which is only allowed for debugging purposes) only 32 bits access is supported.\nNote 2: SYS_CTRL_REG\\[CACHERAM_MUX\\] must be set to \'0\' before accessing the memory mapped Cache Data and TAG memory.\nSee also the CACHE_CTRL2_REG\\[CACHE_USE_FULL_DB_RANGE\\] description."]
234    #[inline(always)]
235    pub fn cache_wen(
236        self,
237    ) -> crate::common::RegisterFieldBool<12, 1, 0, CacheCtrl2Reg_SPEC, crate::common::RW> {
238        crate::common::RegisterFieldBool::<12,1,0,CacheCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
239    }
240
241    #[doc = "Length of OQSPI FLASH cacheable memory.\nN*64 KBytes. N = 0 to 2048, incl. 2048 (max. of 128 Mbytes).\nSetting CACHE_LEN=0 disables the caching.\n\nNote 1: The max. relevant CACHE_LEN setting depends on the chosen Flash region (program) size.\nNote 2: The first block (CACHE_LEN=1) includes the memory space specified by CACHE_FLASH_REG\\[FLASH_REGION_OFFSET\\]."]
242    #[inline(always)]
243    pub fn cache_len(
244        self,
245    ) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, crate::common::RW>
246    {
247        crate::common::RegisterField::<
248            0,
249            0xfff,
250            1,
251            0,
252            u16,
253            u16,
254            CacheCtrl2Reg_SPEC,
255            crate::common::RW,
256        >::from_register(self, 0)
257    }
258}
259impl ::core::default::Default for CacheCtrl2Reg {
260    #[inline(always)]
261    fn default() -> CacheCtrl2Reg {
262        <crate::RegValueT<CacheCtrl2Reg_SPEC> as RegisterValue<_>>::new(0)
263    }
264}
265
266#[doc(hidden)]
267#[derive(Copy, Clone, Eq, PartialEq)]
268pub struct CacheFlashReg_SPEC;
269impl crate::sealed::RegSpec for CacheFlashReg_SPEC {
270    type DataType = u32;
271}
272
273#[doc = "Cache QSPI Flash program size and base address register (only Word (32-bits) access supported)."]
274pub type CacheFlashReg = crate::RegValueT<CacheFlashReg_SPEC>;
275
276impl CacheFlashReg {
277    #[doc = "These bits corresponds with the Flash region base address bits \\[31:16\\].\nDefault value is \'0x1800\'.\nThe Flash region base address bits \\[31:27\\] are fixed to \'0b00011\', supporting the range of 0x1800-0x1FFF\'.\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset.\nNote 2 The Flash region base address setting depends on the chosen Flash region size."]
278    #[inline(always)]
279    pub fn flash_region_base(
280        self,
281    ) -> crate::common::RegisterField<
282        16,
283        0xffff,
284        1,
285        0,
286        u16,
287        u16,
288        CacheFlashReg_SPEC,
289        crate::common::RW,
290    > {
291        crate::common::RegisterField::<
292            16,
293            0xffff,
294            1,
295            0,
296            u16,
297            u16,
298            CacheFlashReg_SPEC,
299            crate::common::RW,
300        >::from_register(self, 0)
301    }
302
303    #[doc = "Flash region offset address (in words).\nThis value is added to the Flash (CPU) address bits \\[13:2\\].\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset."]
304    #[inline(always)]
305    pub fn flash_region_offset(
306        self,
307    ) -> crate::common::RegisterField<4, 0xfff, 1, 0, u16, u16, CacheFlashReg_SPEC, crate::common::RW>
308    {
309        crate::common::RegisterField::<
310            4,
311            0xfff,
312            1,
313            0,
314            u16,
315            u16,
316            CacheFlashReg_SPEC,
317            crate::common::RW,
318        >::from_register(self, 0)
319    }
320
321    #[doc = "Flash region size.\nDefault value is \'1\' (0.5 MBytes).\n0 = 0.25 MBytes,\n1 = 0.5 MBytes,\n2 = 1 MBytes,\n3 = 2 MBytes,\n4 = 4 MBytes,\n5 = 8 MBytes,\n6 = 16 MBytes,\n7 = 32 MBytes,\n8 = 64 MBytes,\n9 = 128 MBytes.\nThese register bits are retained.\nNote 1: The updated value takes effect only after a software reset.\nNote 2: See for the max. region (program) size the memory map."]
322    #[inline(always)]
323    pub fn flash_region_size(
324        self,
325    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, CacheFlashReg_SPEC, crate::common::RW>
326    {
327        crate::common::RegisterField::<0,0xf,1,0,u8,u8,CacheFlashReg_SPEC,crate::common::RW>::from_register(self,0)
328    }
329}
330impl ::core::default::Default for CacheFlashReg {
331    #[inline(always)]
332    fn default() -> CacheFlashReg {
333        <crate::RegValueT<CacheFlashReg_SPEC> as RegisterValue<_>>::new(402653185)
334    }
335}
336
337#[doc(hidden)]
338#[derive(Copy, Clone, Eq, PartialEq)]
339pub struct CacheMrmCtrlReg_SPEC;
340impl crate::sealed::RegSpec for CacheMrmCtrlReg_SPEC {
341    type DataType = u32;
342}
343
344#[doc = "Cache MRM (Miss Rate Monitor) CONTROL register (only Word (32-bits) access supported)."]
345pub type CacheMrmCtrlReg = crate::RegValueT<CacheMrmCtrlReg_SPEC>;
346
347impl CacheMrmCtrlReg {
348    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache hits reached the programmed threshold (threshold != 0)."]
349    #[inline(always)]
350    pub fn mrm_irq_hits_thres_status(
351        self,
352    ) -> crate::common::RegisterFieldBool<4, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
353        crate::common::RegisterFieldBool::<4,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
354    }
355
356    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0)."]
357    #[inline(always)]
358    pub fn mrm_irq_misses_thres_status(
359        self,
360    ) -> crate::common::RegisterFieldBool<3, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
361        crate::common::RegisterFieldBool::<3,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
362    }
363
364    #[doc = "0: No interrupt is generated.\n1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0)."]
365    #[inline(always)]
366    pub fn mrm_irq_tint_status(
367        self,
368    ) -> crate::common::RegisterFieldBool<2, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
369        crate::common::RegisterFieldBool::<2,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
370    }
371
372    #[doc = "0: Disables interrupt generation.\n1: Enables interrupt generation.\nNote: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,"]
373    #[inline(always)]
374    pub fn mrm_irq_mask(
375        self,
376    ) -> crate::common::RegisterFieldBool<1, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
377        crate::common::RegisterFieldBool::<1,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
378    }
379
380    #[doc = "0: Freeze the \"misses/hits\" counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG.\n1: Enables the counters.\nNote: In case CACHE_MRM_CTRL_REG\\[MRM_START\\] is set to \'1\' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 32 MHz) until it\'s \'0\'. At that time CACHE_MRM_CTRL_REG\\[MRM_START\\] will be reset automatically to \'0\' by the MRM hardware and the MRM interrupt will be generated."]
381    #[inline(always)]
382    pub fn mrm_start(
383        self,
384    ) -> crate::common::RegisterFieldBool<0, 1, 0, CacheMrmCtrlReg_SPEC, crate::common::RW> {
385        crate::common::RegisterFieldBool::<0,1,0,CacheMrmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
386    }
387}
388impl ::core::default::Default for CacheMrmCtrlReg {
389    #[inline(always)]
390    fn default() -> CacheMrmCtrlReg {
391        <crate::RegValueT<CacheMrmCtrlReg_SPEC> as RegisterValue<_>>::new(0)
392    }
393}
394
395#[doc(hidden)]
396#[derive(Copy, Clone, Eq, PartialEq)]
397pub struct CacheMrmHits1WsReg_SPEC;
398impl crate::sealed::RegSpec for CacheMrmHits1WsReg_SPEC {
399    type DataType = u32;
400}
401
402#[doc = "Cache MRM (Miss Rate Monitor) HITS with 1 Wait State register (only Word (32-bits) access supported)."]
403pub type CacheMrmHits1WsReg = crate::RegValueT<CacheMrmHits1WsReg_SPEC>;
404
405impl CacheMrmHits1WsReg {
406    #[doc = "Contains the amount of cache hits."]
407    #[inline(always)]
408    pub fn mrm_hits1ws(
409        self,
410    ) -> crate::common::RegisterField<
411        0,
412        0xffffffff,
413        1,
414        0,
415        u32,
416        u32,
417        CacheMrmHits1WsReg_SPEC,
418        crate::common::RW,
419    > {
420        crate::common::RegisterField::<
421            0,
422            0xffffffff,
423            1,
424            0,
425            u32,
426            u32,
427            CacheMrmHits1WsReg_SPEC,
428            crate::common::RW,
429        >::from_register(self, 0)
430    }
431}
432impl ::core::default::Default for CacheMrmHits1WsReg {
433    #[inline(always)]
434    fn default() -> CacheMrmHits1WsReg {
435        <crate::RegValueT<CacheMrmHits1WsReg_SPEC> as RegisterValue<_>>::new(0)
436    }
437}
438
439#[doc(hidden)]
440#[derive(Copy, Clone, Eq, PartialEq)]
441pub struct CacheMrmHitsReg_SPEC;
442impl crate::sealed::RegSpec for CacheMrmHitsReg_SPEC {
443    type DataType = u32;
444}
445
446#[doc = "Cache MRM (Miss Rate Monitor) HITS register (only Word (32-bits) access supported)."]
447pub type CacheMrmHitsReg = crate::RegValueT<CacheMrmHitsReg_SPEC>;
448
449impl CacheMrmHitsReg {
450    #[doc = "Contains the amount of cache hits."]
451    #[inline(always)]
452    pub fn mrm_hits(
453        self,
454    ) -> crate::common::RegisterField<
455        0,
456        0xffffffff,
457        1,
458        0,
459        u32,
460        u32,
461        CacheMrmHitsReg_SPEC,
462        crate::common::RW,
463    > {
464        crate::common::RegisterField::<
465            0,
466            0xffffffff,
467            1,
468            0,
469            u32,
470            u32,
471            CacheMrmHitsReg_SPEC,
472            crate::common::RW,
473        >::from_register(self, 0)
474    }
475}
476impl ::core::default::Default for CacheMrmHitsReg {
477    #[inline(always)]
478    fn default() -> CacheMrmHitsReg {
479        <crate::RegValueT<CacheMrmHitsReg_SPEC> as RegisterValue<_>>::new(0)
480    }
481}
482
483#[doc(hidden)]
484#[derive(Copy, Clone, Eq, PartialEq)]
485pub struct CacheMrmHitsThresReg_SPEC;
486impl crate::sealed::RegSpec for CacheMrmHitsThresReg_SPEC {
487    type DataType = u32;
488}
489
490#[doc = "Cache MRM (Miss Rate Monitor) HITS THRESHOLD register (only Word (32-bits) access supported)."]
491pub type CacheMrmHitsThresReg = crate::RegValueT<CacheMrmHitsThresReg_SPEC>;
492
493impl CacheMrmHitsThresReg {
494    #[doc = "Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_HITS_THRES_STATUS\\].\nNote: When MRM_HITS_THRES=0 (unrealistic value), no interrupt will be generated."]
495    #[inline(always)]
496    pub fn mrm_hits_thres(
497        self,
498    ) -> crate::common::RegisterField<
499        0,
500        0xffffffff,
501        1,
502        0,
503        u32,
504        u32,
505        CacheMrmHitsThresReg_SPEC,
506        crate::common::RW,
507    > {
508        crate::common::RegisterField::<
509            0,
510            0xffffffff,
511            1,
512            0,
513            u32,
514            u32,
515            CacheMrmHitsThresReg_SPEC,
516            crate::common::RW,
517        >::from_register(self, 0)
518    }
519}
520impl ::core::default::Default for CacheMrmHitsThresReg {
521    #[inline(always)]
522    fn default() -> CacheMrmHitsThresReg {
523        <crate::RegValueT<CacheMrmHitsThresReg_SPEC> as RegisterValue<_>>::new(0)
524    }
525}
526
527#[doc(hidden)]
528#[derive(Copy, Clone, Eq, PartialEq)]
529pub struct CacheMrmMissesReg_SPEC;
530impl crate::sealed::RegSpec for CacheMrmMissesReg_SPEC {
531    type DataType = u32;
532}
533
534#[doc = "Cache MRM (Miss Rate Monitor) MISSES register (only Word (32-bits) access supported)."]
535pub type CacheMrmMissesReg = crate::RegValueT<CacheMrmMissesReg_SPEC>;
536
537impl CacheMrmMissesReg {
538    #[doc = "Contains the amount of cache misses."]
539    #[inline(always)]
540    pub fn mrm_misses(
541        self,
542    ) -> crate::common::RegisterField<
543        0,
544        0xffffffff,
545        1,
546        0,
547        u32,
548        u32,
549        CacheMrmMissesReg_SPEC,
550        crate::common::RW,
551    > {
552        crate::common::RegisterField::<
553            0,
554            0xffffffff,
555            1,
556            0,
557            u32,
558            u32,
559            CacheMrmMissesReg_SPEC,
560            crate::common::RW,
561        >::from_register(self, 0)
562    }
563}
564impl ::core::default::Default for CacheMrmMissesReg {
565    #[inline(always)]
566    fn default() -> CacheMrmMissesReg {
567        <crate::RegValueT<CacheMrmMissesReg_SPEC> as RegisterValue<_>>::new(0)
568    }
569}
570
571#[doc(hidden)]
572#[derive(Copy, Clone, Eq, PartialEq)]
573pub struct CacheMrmMissesThresReg_SPEC;
574impl crate::sealed::RegSpec for CacheMrmMissesThresReg_SPEC {
575    type DataType = u32;
576}
577
578#[doc = "Cache MRM (Miss Rate Monitor) THRESHOLD register (only Word (32-bits) access supported)."]
579pub type CacheMrmMissesThresReg = crate::RegValueT<CacheMrmMissesThresReg_SPEC>;
580
581impl CacheMrmMissesThresReg {
582    #[doc = "Defines the misses threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_MISSES_THRES_STATUS\\].\nNote: When MRM_MISSES_THRES=0 (unrealistic value), no interrupt will be generated."]
583    #[inline(always)]
584    pub fn mrm_misses_thres(
585        self,
586    ) -> crate::common::RegisterField<
587        0,
588        0xffffffff,
589        1,
590        0,
591        u32,
592        u32,
593        CacheMrmMissesThresReg_SPEC,
594        crate::common::RW,
595    > {
596        crate::common::RegisterField::<
597            0,
598            0xffffffff,
599            1,
600            0,
601            u32,
602            u32,
603            CacheMrmMissesThresReg_SPEC,
604            crate::common::RW,
605        >::from_register(self, 0)
606    }
607}
608impl ::core::default::Default for CacheMrmMissesThresReg {
609    #[inline(always)]
610    fn default() -> CacheMrmMissesThresReg {
611        <crate::RegValueT<CacheMrmMissesThresReg_SPEC> as RegisterValue<_>>::new(0)
612    }
613}
614
615#[doc(hidden)]
616#[derive(Copy, Clone, Eq, PartialEq)]
617pub struct CacheMrmTintReg_SPEC;
618impl crate::sealed::RegSpec for CacheMrmTintReg_SPEC {
619    type DataType = u32;
620}
621
622#[doc = "Cache MRM (Miss Rate Monitor) TIME INTERVAL register (only Word (32-bits) access supported)."]
623pub type CacheMrmTintReg = crate::RegValueT<CacheMrmTintReg_SPEC>;
624
625impl CacheMrmTintReg {
626    #[doc = "Defines the time interval for the monitoring in 32 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG\\[MRM_IRQ_TINT_STATUS\\].\nNote: When MRM_TINT=0 (unrealistic value), no interrupt will be generated."]
627    #[inline(always)]
628    pub fn mrm_tint(
629        self,
630    ) -> crate::common::RegisterField<
631        0,
632        0x7ffff,
633        1,
634        0,
635        u32,
636        u32,
637        CacheMrmTintReg_SPEC,
638        crate::common::RW,
639    > {
640        crate::common::RegisterField::<
641            0,
642            0x7ffff,
643            1,
644            0,
645            u32,
646            u32,
647            CacheMrmTintReg_SPEC,
648            crate::common::RW,
649        >::from_register(self, 0)
650    }
651}
652impl ::core::default::Default for CacheMrmTintReg {
653    #[inline(always)]
654    fn default() -> CacheMrmTintReg {
655        <crate::RegValueT<CacheMrmTintReg_SPEC> as RegisterValue<_>>::new(0)
656    }
657}
658
659#[doc(hidden)]
660#[derive(Copy, Clone, Eq, PartialEq)]
661pub struct SwdResetReg_SPEC;
662impl crate::sealed::RegSpec for SwdResetReg_SPEC {
663    type DataType = u32;
664}
665
666#[doc = "SWD HW reset control register (only Word (32-bits) access supported)."]
667pub type SwdResetReg = crate::RegValueT<SwdResetReg_SPEC>;
668
669impl SwdResetReg {
670    #[doc = "0: default.\n1: HW reset request (from the debugger tool). The register is automatically reset with a HW_RESET.\nThis bit can only be accessed by the debugger software and not by the application."]
671    #[inline(always)]
672    pub fn swd_hw_reset_req(
673        self,
674    ) -> crate::common::RegisterFieldBool<0, 1, 0, SwdResetReg_SPEC, crate::common::W> {
675        crate::common::RegisterFieldBool::<0,1,0,SwdResetReg_SPEC,crate::common::W>::from_register(self,0)
676    }
677}
678impl ::core::default::Default for SwdResetReg {
679    #[inline(always)]
680    fn default() -> SwdResetReg {
681        <crate::RegValueT<SwdResetReg_SPEC> as RegisterValue<_>>::new(0)
682    }
683}
da1470x_pac/cache.rs

da1470x_pac/
cache.rs
