1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"LRA registers"]
28unsafe impl ::core::marker::Send for super::Lra {}
29unsafe impl ::core::marker::Sync for super::Lra {}
30impl super::Lra {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "General Purpose ADC Control Register"]
38 #[inline(always)]
39 pub const fn lra_adc_ctrl1_reg(
40 &self,
41 ) -> &'static crate::common::Reg<self::LraAdcCtrl1Reg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::LraAdcCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(68usize),
45 )
46 }
47 }
48
49 #[doc = "General Purpose ADC Result Register"]
50 #[inline(always)]
51 pub const fn lra_adc_result_reg(
52 &self,
53 ) -> &'static crate::common::Reg<self::LraAdcResultReg_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::LraAdcResultReg_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(80usize),
57 )
58 }
59 }
60
61 #[doc = "LRA Bridge Register"]
62 #[inline(always)]
63 pub const fn lra_brd_hs_reg(
64 &self,
65 ) -> &'static crate::common::Reg<self::LraBrdHsReg_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::LraBrdHsReg_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(60usize),
69 )
70 }
71 }
72
73 #[doc = "LRA Bridge Register"]
74 #[inline(always)]
75 pub const fn lra_brd_ls_reg(
76 &self,
77 ) -> &'static crate::common::Reg<self::LraBrdLsReg_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::LraBrdLsReg_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(56usize),
81 )
82 }
83 }
84
85 #[doc = "LRA Bridge Staus Register"]
86 #[inline(always)]
87 pub const fn lra_brd_stat_reg(
88 &self,
89 ) -> &'static crate::common::Reg<self::LraBrdStatReg_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::LraBrdStatReg_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(64usize),
93 )
94 }
95 }
96
97 #[doc = "General Purpose LRA Control Register"]
98 #[inline(always)]
99 pub const fn lra_ctrl1_reg(
100 &self,
101 ) -> &'static crate::common::Reg<self::LraCtrl1Reg_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::LraCtrl1Reg_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(0usize),
105 )
106 }
107 }
108
109 #[doc = "General Purpose LRA Control Register"]
110 #[inline(always)]
111 pub const fn lra_ctrl2_reg(
112 &self,
113 ) -> &'static crate::common::Reg<self::LraCtrl2Reg_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::LraCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(4usize),
117 )
118 }
119 }
120
121 #[doc = "LRA test Register"]
122 #[inline(always)]
123 pub const fn lra_dft_reg(
124 &self,
125 ) -> &'static crate::common::Reg<self::LraDftReg_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::LraDftReg_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(88usize),
129 )
130 }
131 }
132
133 #[doc = "LRA Filter Coefficient Register"]
134 #[inline(always)]
135 pub const fn lra_flt_coef1_reg(
136 &self,
137 ) -> &'static crate::common::Reg<self::LraFltCoef1Reg_SPEC, crate::common::RW> {
138 unsafe {
139 crate::common::Reg::<self::LraFltCoef1Reg_SPEC, crate::common::RW>::from_ptr(
140 self._svd2pac_as_ptr().add(44usize),
141 )
142 }
143 }
144
145 #[doc = "LRA Filter Coefficient Register"]
146 #[inline(always)]
147 pub const fn lra_flt_coef2_reg(
148 &self,
149 ) -> &'static crate::common::Reg<self::LraFltCoef2Reg_SPEC, crate::common::RW> {
150 unsafe {
151 crate::common::Reg::<self::LraFltCoef2Reg_SPEC, crate::common::RW>::from_ptr(
152 self._svd2pac_as_ptr().add(48usize),
153 )
154 }
155 }
156
157 #[doc = "LRA Filter Coefficient Register"]
158 #[inline(always)]
159 pub const fn lra_flt_coef3_reg(
160 &self,
161 ) -> &'static crate::common::Reg<self::LraFltCoef3Reg_SPEC, crate::common::RW> {
162 unsafe {
163 crate::common::Reg::<self::LraFltCoef3Reg_SPEC, crate::common::RW>::from_ptr(
164 self._svd2pac_as_ptr().add(52usize),
165 )
166 }
167 }
168
169 #[doc = "LRA Sample Register"]
170 #[inline(always)]
171 pub const fn lra_flt_smp1_reg(
172 &self,
173 ) -> &'static crate::common::Reg<self::LraFltSmp1Reg_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::LraFltSmp1Reg_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(12usize),
177 )
178 }
179 }
180
181 #[doc = "LRA Sample Register"]
182 #[inline(always)]
183 pub const fn lra_flt_smp2_reg(
184 &self,
185 ) -> &'static crate::common::Reg<self::LraFltSmp2Reg_SPEC, crate::common::RW> {
186 unsafe {
187 crate::common::Reg::<self::LraFltSmp2Reg_SPEC, crate::common::RW>::from_ptr(
188 self._svd2pac_as_ptr().add(16usize),
189 )
190 }
191 }
192
193 #[doc = "LRA Sample Register"]
194 #[inline(always)]
195 pub const fn lra_flt_smp3_reg(
196 &self,
197 ) -> &'static crate::common::Reg<self::LraFltSmp3Reg_SPEC, crate::common::RW> {
198 unsafe {
199 crate::common::Reg::<self::LraFltSmp3Reg_SPEC, crate::common::RW>::from_ptr(
200 self._svd2pac_as_ptr().add(20usize),
201 )
202 }
203 }
204
205 #[doc = "LRA Sample Register"]
206 #[inline(always)]
207 pub const fn lra_flt_smp4_reg(
208 &self,
209 ) -> &'static crate::common::Reg<self::LraFltSmp4Reg_SPEC, crate::common::RW> {
210 unsafe {
211 crate::common::Reg::<self::LraFltSmp4Reg_SPEC, crate::common::RW>::from_ptr(
212 self._svd2pac_as_ptr().add(24usize),
213 )
214 }
215 }
216
217 #[doc = "LRA Sample Register"]
218 #[inline(always)]
219 pub const fn lra_flt_smp5_reg(
220 &self,
221 ) -> &'static crate::common::Reg<self::LraFltSmp5Reg_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::LraFltSmp5Reg_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(28usize),
225 )
226 }
227 }
228
229 #[doc = "LRA Sample Register"]
230 #[inline(always)]
231 pub const fn lra_flt_smp6_reg(
232 &self,
233 ) -> &'static crate::common::Reg<self::LraFltSmp6Reg_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::LraFltSmp6Reg_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(32usize),
237 )
238 }
239 }
240
241 #[doc = "LRA Sample Register"]
242 #[inline(always)]
243 pub const fn lra_flt_smp7_reg(
244 &self,
245 ) -> &'static crate::common::Reg<self::LraFltSmp7Reg_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::LraFltSmp7Reg_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(36usize),
249 )
250 }
251 }
252
253 #[doc = "LRA Sample Register"]
254 #[inline(always)]
255 pub const fn lra_flt_smp8_reg(
256 &self,
257 ) -> &'static crate::common::Reg<self::LraFltSmp8Reg_SPEC, crate::common::RW> {
258 unsafe {
259 crate::common::Reg::<self::LraFltSmp8Reg_SPEC, crate::common::RW>::from_ptr(
260 self._svd2pac_as_ptr().add(40usize),
261 )
262 }
263 }
264
265 #[doc = "LRA LDO Regsiter"]
266 #[inline(always)]
267 pub const fn lra_ldo_reg(
268 &self,
269 ) -> &'static crate::common::Reg<self::LraLdoReg_SPEC, crate::common::RW> {
270 unsafe {
271 crate::common::Reg::<self::LraLdoReg_SPEC, crate::common::RW>::from_ptr(
272 self._svd2pac_as_ptr().add(84usize),
273 )
274 }
275 }
276}
277#[doc(hidden)]
278#[derive(Copy, Clone, Eq, PartialEq)]
279pub struct LraAdcCtrl1Reg_SPEC;
280impl crate::sealed::RegSpec for LraAdcCtrl1Reg_SPEC {
281 type DataType = u32;
282}
283
284#[doc = "General Purpose ADC Control Register"]
285pub type LraAdcCtrl1Reg = crate::RegValueT<LraAdcCtrl1Reg_SPEC>;
286
287impl LraAdcCtrl1Reg {
288 #[doc = "0:ADC conversion ready.\n1:ADC conversion in progress."]
289 #[inline(always)]
290 pub fn lra_adc_busy(
291 self,
292 ) -> crate::common::RegisterFieldBool<31, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::R> {
293 crate::common::RegisterFieldBool::<31,1,0,LraAdcCtrl1Reg_SPEC,crate::common::R>::from_register(self,0)
294 }
295
296 #[doc = "ADC offset compensation value.\nSigned value with 3 fractional bits.\n-16 (0x80) to +15.875 (0x7F) in intervals of 0.125 (0x01).\nNote: ADC gain error must be compensated in the calculation of VREF."]
297 #[inline(always)]
298 pub fn lra_adc_offset(
299 self,
300 ) -> crate::common::RegisterField<9, 0xff, 1, 0, u8, u8, LraAdcCtrl1Reg_SPEC, crate::common::RW>
301 {
302 crate::common::RegisterField::<9,0xff,1,0,u8,u8,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
303 }
304
305 #[doc = "Select which inputs will be enabled on the ADC.\n0,1 = normal inputs (i.e. both I and Q inputs connected to LRA-current-sense voltage source)\n2 = I channel connected to the analog input testbus on PORTS P14 and P15, Q channel is muted.\n3 =Q channel connected to the analog input testbus on PORTS P14 and P15, I channel is muted.\nNote: The LRA_ADC_CTRL1_REG\\[ADC_MUTE\\] field takes precedence over this test functionality."]
306 #[inline(always)]
307 pub fn lra_adc_test_param(
308 self,
309 ) -> crate::common::RegisterFieldBool<8, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::RW> {
310 crate::common::RegisterFieldBool::<8,1,0,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
311 }
312
313 #[doc = "Select analog testbus on ADC input."]
314 #[inline(always)]
315 pub fn lra_adc_test_in_sel(
316 self,
317 ) -> crate::common::RegisterFieldBool<7, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::RW> {
318 crate::common::RegisterFieldBool::<7,1,0,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
319 }
320
321 #[doc = "ADC clock divider"]
322 #[inline(always)]
323 pub fn lra_adc_freq(
324 self,
325 ) -> crate::common::RegisterField<3, 0xf, 1, 0, u8, u8, LraAdcCtrl1Reg_SPEC, crate::common::RW>
326 {
327 crate::common::RegisterField::<3,0xf,1,0,u8,u8,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
328 }
329
330 #[doc = "Change polarity of ADC input"]
331 #[inline(always)]
332 pub fn lra_adc_sign(
333 self,
334 ) -> crate::common::RegisterFieldBool<2, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::RW> {
335 crate::common::RegisterFieldBool::<2,1,0,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
336 }
337
338 #[doc = "0: Normal operation\n1: Short the inputs of the ADC (used for DC offset cal)"]
339 #[inline(always)]
340 pub fn lra_adc_mute(
341 self,
342 ) -> crate::common::RegisterFieldBool<1, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::RW> {
343 crate::common::RegisterFieldBool::<1,1,0,LraAdcCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
344 }
345
346 #[doc = "0: ADC conversion ready.\n1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero."]
347 #[inline(always)]
348 pub fn lra_adc_start(
349 self,
350 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraAdcCtrl1Reg_SPEC, crate::common::W> {
351 crate::common::RegisterFieldBool::<0,1,0,LraAdcCtrl1Reg_SPEC,crate::common::W>::from_register(self,0)
352 }
353}
354impl ::core::default::Default for LraAdcCtrl1Reg {
355 #[inline(always)]
356 fn default() -> LraAdcCtrl1Reg {
357 <crate::RegValueT<LraAdcCtrl1Reg_SPEC> as RegisterValue<_>>::new(32)
358 }
359}
360
361#[doc(hidden)]
362#[derive(Copy, Clone, Eq, PartialEq)]
363pub struct LraAdcResultReg_SPEC;
364impl crate::sealed::RegSpec for LraAdcResultReg_SPEC {
365 type DataType = u32;
366}
367
368#[doc = "General Purpose ADC Result Register"]
369pub type LraAdcResultReg = crate::RegValueT<LraAdcResultReg_SPEC>;
370
371impl LraAdcResultReg {
372 #[doc = "Manual value to replace the ADC output. Select its use by FLT_IN_SEL."]
373 #[inline(always)]
374 pub fn man_flt_in(
375 self,
376 ) -> crate::common::RegisterField<
377 16,
378 0xffff,
379 1,
380 0,
381 u16,
382 u16,
383 LraAdcResultReg_SPEC,
384 crate::common::RW,
385 > {
386 crate::common::RegisterField::<
387 16,
388 0xffff,
389 1,
390 0,
391 u16,
392 u16,
393 LraAdcResultReg_SPEC,
394 crate::common::RW,
395 >::from_register(self, 0)
396 }
397
398 #[doc = "Returns the 10 up to 16 bits linear value of the last AD conversion as a signed value. The most significant 11 bits are always valid, the lower 5 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 32 samples results in 5 extra bits.\nIn the context of the LRA constant current or constant duty cycle control systems, the (non-oversampled) value is interpreted as a signed value with 7 integer bits and 3 fractional bits: -128.000 (0x8000) to +127.875 (0x7FE0) in steps of 0.125 (0x0010). \nNote that the measured values in this context are always positive."]
399 #[inline(always)]
400 pub fn gp_adc_val(
401 self,
402 ) -> crate::common::RegisterField<
403 0,
404 0xffff,
405 1,
406 0,
407 u16,
408 u16,
409 LraAdcResultReg_SPEC,
410 crate::common::R,
411 > {
412 crate::common::RegisterField::<
413 0,
414 0xffff,
415 1,
416 0,
417 u16,
418 u16,
419 LraAdcResultReg_SPEC,
420 crate::common::R,
421 >::from_register(self, 0)
422 }
423}
424impl ::core::default::Default for LraAdcResultReg {
425 #[inline(always)]
426 fn default() -> LraAdcResultReg {
427 <crate::RegValueT<LraAdcResultReg_SPEC> as RegisterValue<_>>::new(16384)
428 }
429}
430
431#[doc(hidden)]
432#[derive(Copy, Clone, Eq, PartialEq)]
433pub struct LraBrdHsReg_SPEC;
434impl crate::sealed::RegSpec for LraBrdHsReg_SPEC {
435 type DataType = u32;
436}
437
438#[doc = "LRA Bridge Register"]
439pub type LraBrdHsReg = crate::RegValueT<LraBrdHsReg_SPEC>;
440
441impl LraBrdHsReg {
442 #[doc = "Current-sensing amplifier gain settings:\n0001: x6\n0010: x8\n0100: x10\n1000: x12"]
443 #[inline(always)]
444 pub fn trim_gain(
445 self,
446 ) -> crate::common::RegisterField<11, 0xf, 1, 0, u8, u8, LraBrdHsReg_SPEC, crate::common::RW>
447 {
448 crate::common::RegisterField::<11,0xf,1,0,u8,u8,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
449 }
450
451 #[doc = "HS gnd trim, default at 100\n000: 2.2V and 111:3.6V with 0.2V per step"]
452 #[inline(always)]
453 pub fn hsgnd_trim(
454 self,
455 ) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, LraBrdHsReg_SPEC, crate::common::RW>
456 {
457 crate::common::RegisterField::<8,0x7,1,0,u8,u8,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
458 }
459
460 #[doc = "HS short-circuit protection limit trimming"]
461 #[inline(always)]
462 pub fn scp_hs_trim(
463 self,
464 ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, LraBrdHsReg_SPEC, crate::common::RW>
465 {
466 crate::common::RegisterField::<4,0xf,1,0,u8,u8,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
467 }
468
469 #[doc = "HS short-circuit protection enable"]
470 #[inline(always)]
471 pub fn scp_hs_en(
472 self,
473 ) -> crate::common::RegisterFieldBool<3, 1, 0, LraBrdHsReg_SPEC, crate::common::RW> {
474 crate::common::RegisterFieldBool::<3,1,0,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
475 }
476
477 #[doc = "HS edge-rate control trimming. Lowto-High switching slewing:\n00: 25 MV/s\n01: 50 MV/s\n10: 75 MV/s\n11: 100 MV/s"]
478 #[inline(always)]
479 pub fn erc_hs_trim(
480 self,
481 ) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, LraBrdHsReg_SPEC, crate::common::RW>
482 {
483 crate::common::RegisterField::<1,0x3,1,0,u8,u8,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
484 }
485
486 #[doc = "HS edge-rate control enable"]
487 #[inline(always)]
488 pub fn erc_hs_en(
489 self,
490 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraBrdHsReg_SPEC, crate::common::RW> {
491 crate::common::RegisterFieldBool::<0,1,0,LraBrdHsReg_SPEC,crate::common::RW>::from_register(self,0)
492 }
493}
494impl ::core::default::Default for LraBrdHsReg {
495 #[inline(always)]
496 fn default() -> LraBrdHsReg {
497 <crate::RegValueT<LraBrdHsReg_SPEC> as RegisterValue<_>>::new(0)
498 }
499}
500
501#[doc(hidden)]
502#[derive(Copy, Clone, Eq, PartialEq)]
503pub struct LraBrdLsReg_SPEC;
504impl crate::sealed::RegSpec for LraBrdLsReg_SPEC {
505 type DataType = u32;
506}
507
508#[doc = "LRA Bridge Register"]
509pub type LraBrdLsReg = crate::RegValueT<LraBrdLsReg_SPEC>;
510
511impl LraBrdLsReg {
512 #[doc = "LSN short-circuit protection limit trimming"]
513 #[inline(always)]
514 pub fn scp_ls_trim_n(
515 self,
516 ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, LraBrdLsReg_SPEC, crate::common::RW>
517 {
518 crate::common::RegisterField::<8,0xf,1,0,u8,u8,LraBrdLsReg_SPEC,crate::common::RW>::from_register(self,0)
519 }
520
521 #[doc = "LSP short-circuit protection limit trimming"]
522 #[inline(always)]
523 pub fn scp_ls_trim_p(
524 self,
525 ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, LraBrdLsReg_SPEC, crate::common::RW>
526 {
527 crate::common::RegisterField::<4,0xf,1,0,u8,u8,LraBrdLsReg_SPEC,crate::common::RW>::from_register(self,0)
528 }
529
530 #[doc = "LS short-circuit protection enable"]
531 #[inline(always)]
532 pub fn scp_ls_en(
533 self,
534 ) -> crate::common::RegisterFieldBool<3, 1, 0, LraBrdLsReg_SPEC, crate::common::RW> {
535 crate::common::RegisterFieldBool::<3,1,0,LraBrdLsReg_SPEC,crate::common::RW>::from_register(self,0)
536 }
537
538 #[doc = "LS edge-rate control trimming. High-to-Low switching slewing:\n00: 25 MV/s\n01: 50 MV/s\n10: 75 MV/s\n11: 100 MV/s"]
539 #[inline(always)]
540 pub fn erc_ls_trim(
541 self,
542 ) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, LraBrdLsReg_SPEC, crate::common::RW>
543 {
544 crate::common::RegisterField::<1,0x3,1,0,u8,u8,LraBrdLsReg_SPEC,crate::common::RW>::from_register(self,0)
545 }
546
547 #[doc = "LS edge-rate control enable"]
548 #[inline(always)]
549 pub fn erc_ls_en(
550 self,
551 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraBrdLsReg_SPEC, crate::common::RW> {
552 crate::common::RegisterFieldBool::<0,1,0,LraBrdLsReg_SPEC,crate::common::RW>::from_register(self,0)
553 }
554}
555impl ::core::default::Default for LraBrdLsReg {
556 #[inline(always)]
557 fn default() -> LraBrdLsReg {
558 <crate::RegValueT<LraBrdLsReg_SPEC> as RegisterValue<_>>::new(0)
559 }
560}
561
562#[doc(hidden)]
563#[derive(Copy, Clone, Eq, PartialEq)]
564pub struct LraBrdStatReg_SPEC;
565impl crate::sealed::RegSpec for LraBrdStatReg_SPEC {
566 type DataType = u32;
567}
568
569#[doc = "LRA Bridge Staus Register"]
570pub type LraBrdStatReg = crate::RegValueT<LraBrdStatReg_SPEC>;
571
572impl LraBrdStatReg {
573 #[doc = "HS short circuit comparator output"]
574 #[inline(always)]
575 pub fn scp_hs_out(
576 self,
577 ) -> crate::common::RegisterFieldBool<13, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
578 crate::common::RegisterFieldBool::<13,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
579 }
580
581 #[doc = "LSN short circuit comparator output"]
582 #[inline(always)]
583 pub fn scp_ls_comp_out_n(
584 self,
585 ) -> crate::common::RegisterFieldBool<12, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
586 crate::common::RegisterFieldBool::<12,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
587 }
588
589 #[doc = "LSP short circuit comparator output"]
590 #[inline(always)]
591 pub fn scp_ls_comp_out_p(
592 self,
593 ) -> crate::common::RegisterFieldBool<11, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
594 crate::common::RegisterFieldBool::<11,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
595 }
596
597 #[doc = "1: LS short-circuit event detected\n0: no LS short-circuit event detected"]
598 #[inline(always)]
599 pub fn sc_event_ls(
600 self,
601 ) -> crate::common::RegisterFieldBool<10, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
602 crate::common::RegisterFieldBool::<10,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
603 }
604
605 #[doc = "1: HS short-circuit event detected\n0: no HS short-circuit event detected"]
606 #[inline(always)]
607 pub fn sc_event_hs(
608 self,
609 ) -> crate::common::RegisterFieldBool<9, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
610 crate::common::RegisterFieldBool::<9,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
611 }
612
613 #[doc = "1: Loop saturation detected\n0: Loop not saturated"]
614 #[inline(always)]
615 pub fn loop_stat(
616 self,
617 ) -> crate::common::RegisterFieldBool<8, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
618 crate::common::RegisterFieldBool::<8,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
619 }
620
621 #[doc = "LSN control status"]
622 #[inline(always)]
623 pub fn lsn_on(
624 self,
625 ) -> crate::common::RegisterFieldBool<7, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
626 crate::common::RegisterFieldBool::<7,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
627 }
628
629 #[doc = "LSP control status"]
630 #[inline(always)]
631 pub fn lsp_on(
632 self,
633 ) -> crate::common::RegisterFieldBool<6, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
634 crate::common::RegisterFieldBool::<6,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
635 }
636
637 #[doc = "HSN control status"]
638 #[inline(always)]
639 pub fn hsn_on(
640 self,
641 ) -> crate::common::RegisterFieldBool<5, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
642 crate::common::RegisterFieldBool::<5,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
643 }
644
645 #[doc = "HSP control status"]
646 #[inline(always)]
647 pub fn hsp_on(
648 self,
649 ) -> crate::common::RegisterFieldBool<4, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
650 crate::common::RegisterFieldBool::<4,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
651 }
652
653 #[doc = "LSN power FET gate actual status"]
654 #[inline(always)]
655 pub fn lsn_stat(
656 self,
657 ) -> crate::common::RegisterFieldBool<3, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
658 crate::common::RegisterFieldBool::<3,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
659 }
660
661 #[doc = "LSP power FET gate actual status"]
662 #[inline(always)]
663 pub fn lsp_stat(
664 self,
665 ) -> crate::common::RegisterFieldBool<2, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
666 crate::common::RegisterFieldBool::<2,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
667 }
668
669 #[doc = "HSN power FET gate actual status"]
670 #[inline(always)]
671 pub fn hsn_stat(
672 self,
673 ) -> crate::common::RegisterFieldBool<1, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
674 crate::common::RegisterFieldBool::<1,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
675 }
676
677 #[doc = "HSP power FET gate actual status"]
678 #[inline(always)]
679 pub fn hsp_stat(
680 self,
681 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraBrdStatReg_SPEC, crate::common::R> {
682 crate::common::RegisterFieldBool::<0,1,0,LraBrdStatReg_SPEC,crate::common::R>::from_register(self,0)
683 }
684}
685impl ::core::default::Default for LraBrdStatReg {
686 #[inline(always)]
687 fn default() -> LraBrdStatReg {
688 <crate::RegValueT<LraBrdStatReg_SPEC> as RegisterValue<_>>::new(0)
689 }
690}
691
692#[doc(hidden)]
693#[derive(Copy, Clone, Eq, PartialEq)]
694pub struct LraCtrl1Reg_SPEC;
695impl crate::sealed::RegSpec for LraCtrl1Reg_SPEC {
696 type DataType = u32;
697}
698
699#[doc = "General Purpose LRA Control Register"]
700pub type LraCtrl1Reg = crate::RegValueT<LraCtrl1Reg_SPEC>;
701
702impl LraCtrl1Reg {
703 #[doc = "Current bin index (0-15). Check if equal to IRQ_IDX before and/or after updating HALF_PERIOD with ISR."]
704 #[inline(always)]
705 pub fn smp_idx(
706 self,
707 ) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, LraCtrl1Reg_SPEC, crate::common::R>
708 {
709 crate::common::RegisterField::<24,0xf,1,0,u8,u8,LraCtrl1Reg_SPEC,crate::common::R>::from_register(self,0)
710 }
711
712 #[doc = "0 = interrupt scp event disabled\n1 = interupt scp event enabled"]
713 #[inline(always)]
714 pub fn irq_scp_event_en(
715 self,
716 ) -> crate::common::RegisterFieldBool<18, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
717 crate::common::RegisterFieldBool::<18,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
718 }
719
720 #[doc = "0 = interrupt adc disabled\n1 = interupt adc enabled"]
721 #[inline(always)]
722 pub fn irq_adc_en(
723 self,
724 ) -> crate::common::RegisterFieldBool<17, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
725 crate::common::RegisterFieldBool::<17,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
726 }
727
728 #[doc = "0 = interrupt controller disabled\n1 = interupt controller enabled"]
729 #[inline(always)]
730 pub fn irq_ctrl_en(
731 self,
732 ) -> crate::common::RegisterFieldBool<16, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
733 crate::common::RegisterFieldBool::<16,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
734 }
735
736 #[doc = "At which sample index an IRQ will be generated (0-15). When IRQ_IDX < 8, IRQs are generated at both half cycles (IRQ_IDX and IRQ_IDX+8), otherwise only in the second half cycle."]
737 #[inline(always)]
738 pub fn irq_idx(
739 self,
740 ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, LraCtrl1Reg_SPEC, crate::common::RW>
741 {
742 crate::common::RegisterField::<12,0xf,1,0,u8,u8,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
743 }
744
745 #[doc = "Divider value of the interrupt request. Number of LRA/ERM periods, between successive IRQs. 0,1=every (half) cycle, depending on IRQ_IDX; 2=every second cycle, IRQ at the end of first or both half cycles (based on IRQ_IDX), etc."]
746 #[inline(always)]
747 pub fn irq_div(
748 self,
749 ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, LraCtrl1Reg_SPEC, crate::common::RW>
750 {
751 crate::common::RegisterField::<8,0xf,1,0,u8,u8,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
752 }
753
754 #[doc = "Select which samples to store for the resonance control algorithm.\n0=Sense voltage after down-sampling\n1=Error voltage (after subtraction of VREF and down-sampled sense voltgae input)\n2=Duty cycle signal after loop-filter\n3=Duty cycle signal after summation with DREF"]
755 #[inline(always)]
756 pub fn smp_sel(
757 self,
758 ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, LraCtrl1Reg_SPEC, crate::common::RW>
759 {
760 crate::common::RegisterField::<6,0x3,1,0,u8,u8,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
761 }
762
763 #[doc = "LXP and LXN node pull down enbale, when SC_EVENT=0 && LOOP_EN=0"]
764 #[inline(always)]
765 pub fn pulldown_en(
766 self,
767 ) -> crate::common::RegisterFieldBool<5, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
768 crate::common::RegisterFieldBool::<5,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
769 }
770
771 #[doc = "0=disable loop\n1=enable loop"]
772 #[inline(always)]
773 pub fn loop_en(
774 self,
775 ) -> crate::common::RegisterFieldBool<4, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
776 crate::common::RegisterFieldBool::<4,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
777 }
778
779 #[doc = "0=lra ldo disabled\n1=lra ldo enabled"]
780 #[inline(always)]
781 pub fn ldo_en(
782 self,
783 ) -> crate::common::RegisterFieldBool<3, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
784 crate::common::RegisterFieldBool::<3,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
785 }
786
787 #[doc = "0=lra adc disabled\n1=lra adc enabled"]
788 #[inline(always)]
789 pub fn adc_en(
790 self,
791 ) -> crate::common::RegisterFieldBool<2, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
792 crate::common::RegisterFieldBool::<2,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
793 }
794
795 #[doc = "0=hbridge disabled\n1=hbridge enabled"]
796 #[inline(always)]
797 pub fn hbridge_en(
798 self,
799 ) -> crate::common::RegisterFieldBool<1, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
800 crate::common::RegisterFieldBool::<1,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
801 }
802
803 #[doc = "0=lra controller disabled\n1=lra controller enabled"]
804 #[inline(always)]
805 pub fn lra_en(
806 self,
807 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraCtrl1Reg_SPEC, crate::common::RW> {
808 crate::common::RegisterFieldBool::<0,1,0,LraCtrl1Reg_SPEC,crate::common::RW>::from_register(self,0)
809 }
810}
811impl ::core::default::Default for LraCtrl1Reg {
812 #[inline(always)]
813 fn default() -> LraCtrl1Reg {
814 <crate::RegValueT<LraCtrl1Reg_SPEC> as RegisterValue<_>>::new(29120)
815 }
816}
817
818#[doc(hidden)]
819#[derive(Copy, Clone, Eq, PartialEq)]
820pub struct LraCtrl2Reg_SPEC;
821impl crate::sealed::RegSpec for LraCtrl2Reg_SPEC {
822 type DataType = u32;
823}
824
825#[doc = "General Purpose LRA Control Register"]
826pub type LraCtrl2Reg = crate::RegValueT<LraCtrl2Reg_SPEC>;
827
828impl LraCtrl2Reg {
829 #[doc = "Half of the LRA period, in units of 4 ms (= 125 kHz divided by the resonant frequency of the LRA)."]
830 #[inline(always)]
831 pub fn half_period(
832 self,
833 ) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, LraCtrl2Reg_SPEC, crate::common::RW>
834 {
835 crate::common::RegisterField::<
836 16,
837 0xffff,
838 1,
839 0,
840 u16,
841 u16,
842 LraCtrl2Reg_SPEC,
843 crate::common::RW,
844 >::from_register(self, 0)
845 }
846
847 #[doc = "Automatic frequency control (0=disabled;, 1=enabled, not yet implemented)"]
848 #[inline(always)]
849 pub fn auto_mode(
850 self,
851 ) -> crate::common::RegisterFieldBool<5, 1, 0, LraCtrl2Reg_SPEC, crate::common::RW> {
852 crate::common::RegisterFieldBool::<5,1,0,LraCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
853 }
854
855 #[doc = "Sampling mode for data aiding automatic resonance control (0=averaging, 1=last sample)"]
856 #[inline(always)]
857 pub fn smp_mode(
858 self,
859 ) -> crate::common::RegisterFieldBool<4, 1, 0, LraCtrl2Reg_SPEC, crate::common::RW> {
860 crate::common::RegisterFieldBool::<4,1,0,LraCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
861 }
862
863 #[doc = "Polarity of the square wave (0=normal; 1=inverted); Use for rapid stop."]
864 #[inline(always)]
865 pub fn polarity(
866 self,
867 ) -> crate::common::RegisterFieldBool<3, 1, 0, LraCtrl2Reg_SPEC, crate::common::RW> {
868 crate::common::RegisterFieldBool::<3,1,0,LraCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
869 }
870
871 #[doc = "0 = normal operation\n1 = ADC output overruled by register field MAN_FLT_IN"]
872 #[inline(always)]
873 pub fn flt_in_sel(
874 self,
875 ) -> crate::common::RegisterFieldBool<2, 1, 0, LraCtrl2Reg_SPEC, crate::common::RW> {
876 crate::common::RegisterFieldBool::<2,1,0,LraCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
877 }
878
879 #[doc = "PWM pulse placement: 0=middle, 1=left, 2=right, 3=alternate"]
880 #[inline(always)]
881 pub fn pwm_mode(
882 self,
883 ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, LraCtrl2Reg_SPEC, crate::common::RW>
884 {
885 crate::common::RegisterField::<0,0x3,1,0,u8,u8,LraCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
886 }
887}
888impl ::core::default::Default for LraCtrl2Reg {
889 #[inline(always)]
890 fn default() -> LraCtrl2Reg {
891 <crate::RegValueT<LraCtrl2Reg_SPEC> as RegisterValue<_>>::new(40960000)
892 }
893}
894
895#[doc(hidden)]
896#[derive(Copy, Clone, Eq, PartialEq)]
897pub struct LraDftReg_SPEC;
898impl crate::sealed::RegSpec for LraDftReg_SPEC {
899 type DataType = u32;
900}
901
902#[doc = "LRA test Register"]
903pub type LraDftReg = crate::RegValueT<LraDftReg_SPEC>;
904
905impl LraDftReg {
906 #[doc = "spare registers bits , currently not used"]
907 #[inline(always)]
908 pub fn spare(
909 self,
910 ) -> crate::common::RegisterField<29, 0x7, 1, 0, u8, u8, LraDftReg_SPEC, crate::common::RW>
911 {
912 crate::common::RegisterField::<29,0x7,1,0,u8,u8,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
913 }
914
915 #[doc = "0=use SWM from controller\n1=use SWM_MAN"]
916 #[inline(always)]
917 pub fn swm_sel(
918 self,
919 ) -> crate::common::RegisterFieldBool<28, 1, 0, LraDftReg_SPEC, crate::common::RW> {
920 crate::common::RegisterFieldBool::<28,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
921 }
922
923 #[doc = "swm manual"]
924 #[inline(always)]
925 pub fn swm_man(
926 self,
927 ) -> crate::common::RegisterFieldBool<27, 1, 0, LraDftReg_SPEC, crate::common::RW> {
928 crate::common::RegisterFieldBool::<27,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
929 }
930
931 #[doc = "0=use PWM from controller\n1=use PWM_MAN"]
932 #[inline(always)]
933 pub fn pwm_sel(
934 self,
935 ) -> crate::common::RegisterFieldBool<26, 1, 0, LraDftReg_SPEC, crate::common::RW> {
936 crate::common::RegisterFieldBool::<26,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
937 }
938
939 #[doc = "pwm manual"]
940 #[inline(always)]
941 pub fn pwm_man(
942 self,
943 ) -> crate::common::RegisterFieldBool<25, 1, 0, LraDftReg_SPEC, crate::common::RW> {
944 crate::common::RegisterFieldBool::<25,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
945 }
946
947 #[doc = "20ns unit delay cell trimming bits"]
948 #[inline(always)]
949 pub fn timer_trim(
950 self,
951 ) -> crate::common::RegisterField<23, 0x3, 1, 0, u8, u8, LraDftReg_SPEC, crate::common::RW>
952 {
953 crate::common::RegisterField::<23,0x3,1,0,u8,u8,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
954 }
955
956 #[doc = "Selection of delay of MAG and DEMAG signal:\n00: 60ns\n01: 80ns\n10: 100ns\n11: 120ns"]
957 #[inline(always)]
958 pub fn timer_scale_trim(
959 self,
960 ) -> crate::common::RegisterField<21, 0x3, 1, 0, u8, u8, LraDftReg_SPEC, crate::common::RW>
961 {
962 crate::common::RegisterField::<21,0x3,1,0,u8,u8,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
963 }
964
965 #[inline(always)]
966 pub fn dft_sel(
967 self,
968 ) -> crate::common::RegisterFieldBool<20, 1, 0, LraDftReg_SPEC, crate::common::RW> {
969 crate::common::RegisterFieldBool::<20,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
970 }
971
972 #[doc = "Force HSP and HSN power FETs on:\n0: not actived\n1: HSP and HSN are forced on"]
973 #[inline(always)]
974 pub fn dft_force_hspn(
975 self,
976 ) -> crate::common::RegisterFieldBool<19, 1, 0, LraDftReg_SPEC, crate::common::RW> {
977 crate::common::RegisterFieldBool::<19,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
978 }
979
980 #[doc = "Enable for the timer trimming"]
981 #[inline(always)]
982 pub fn dft_en_timer(
983 self,
984 ) -> crate::common::RegisterFieldBool<18, 1, 0, LraDftReg_SPEC, crate::common::RW> {
985 crate::common::RegisterFieldBool::<18,1,0,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
986 }
987
988 #[doc = "Force state machine in a certain state:\n00: No test\n01: High-Z\n10: Mag\n11: Demag"]
989 #[inline(always)]
990 pub fn dft_stall(
991 self,
992 ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, LraDftReg_SPEC, crate::common::RW>
993 {
994 crate::common::RegisterField::<16,0x3,1,0,u8,u8,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
995 }
996
997 #[doc = "Selection of test bus connection"]
998 #[inline(always)]
999 pub fn dft_ctrl(
1000 self,
1001 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraDftReg_SPEC, crate::common::RW>
1002 {
1003 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,LraDftReg_SPEC,crate::common::RW>::from_register(self,0)
1004 }
1005}
1006impl ::core::default::Default for LraDftReg {
1007 #[inline(always)]
1008 fn default() -> LraDftReg {
1009 <crate::RegValueT<LraDftReg_SPEC> as RegisterValue<_>>::new(0)
1010 }
1011}
1012
1013#[doc(hidden)]
1014#[derive(Copy, Clone, Eq, PartialEq)]
1015pub struct LraFltCoef1Reg_SPEC;
1016impl crate::sealed::RegSpec for LraFltCoef1Reg_SPEC {
1017 type DataType = u32;
1018}
1019
1020#[doc = "LRA Filter Coefficient Register"]
1021pub type LraFltCoef1Reg = crate::RegValueT<LraFltCoef1Reg_SPEC>;
1022
1023impl LraFltCoef1Reg {
1024 #[doc = "Loop filter state-space coefficient a12 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)."]
1025 #[inline(always)]
1026 pub fn flt_coef_01(
1027 self,
1028 ) -> crate::common::RegisterField<
1029 16,
1030 0xffff,
1031 1,
1032 0,
1033 u16,
1034 u16,
1035 LraFltCoef1Reg_SPEC,
1036 crate::common::RW,
1037 > {
1038 crate::common::RegisterField::<
1039 16,
1040 0xffff,
1041 1,
1042 0,
1043 u16,
1044 u16,
1045 LraFltCoef1Reg_SPEC,
1046 crate::common::RW,
1047 >::from_register(self, 0)
1048 }
1049
1050 #[doc = "Loop filter state-space coefficient a11 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)."]
1051 #[inline(always)]
1052 pub fn flt_coef_00(
1053 self,
1054 ) -> crate::common::RegisterField<
1055 0,
1056 0xffff,
1057 1,
1058 0,
1059 u16,
1060 u16,
1061 LraFltCoef1Reg_SPEC,
1062 crate::common::RW,
1063 > {
1064 crate::common::RegisterField::<
1065 0,
1066 0xffff,
1067 1,
1068 0,
1069 u16,
1070 u16,
1071 LraFltCoef1Reg_SPEC,
1072 crate::common::RW,
1073 >::from_register(self, 0)
1074 }
1075}
1076impl ::core::default::Default for LraFltCoef1Reg {
1077 #[inline(always)]
1078 fn default() -> LraFltCoef1Reg {
1079 <crate::RegValueT<LraFltCoef1Reg_SPEC> as RegisterValue<_>>::new(26873446)
1080 }
1081}
1082
1083#[doc(hidden)]
1084#[derive(Copy, Clone, Eq, PartialEq)]
1085pub struct LraFltCoef2Reg_SPEC;
1086impl crate::sealed::RegSpec for LraFltCoef2Reg_SPEC {
1087 type DataType = u32;
1088}
1089
1090#[doc = "LRA Filter Coefficient Register"]
1091pub type LraFltCoef2Reg = crate::RegValueT<LraFltCoef2Reg_SPEC>;
1092
1093impl LraFltCoef2Reg {
1094 #[doc = "Loop filter state-space coefficient a21 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)."]
1095 #[inline(always)]
1096 pub fn flt_coef_10(
1097 self,
1098 ) -> crate::common::RegisterField<
1099 16,
1100 0xffff,
1101 1,
1102 0,
1103 u16,
1104 u16,
1105 LraFltCoef2Reg_SPEC,
1106 crate::common::RW,
1107 > {
1108 crate::common::RegisterField::<
1109 16,
1110 0xffff,
1111 1,
1112 0,
1113 u16,
1114 u16,
1115 LraFltCoef2Reg_SPEC,
1116 crate::common::RW,
1117 >::from_register(self, 0)
1118 }
1119
1120 #[doc = "Loop filter state-space coefficient b1 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).\nNote: For correct intended loop gain, modify the intended value of b1 to b1/ADC_GAIN, where\nADC_GAIN is the normalized gain of the ADC (i.e. ADC_GAIN = GP_ADC_VALUE´300 mA/\\[ILRA´128\\])."]
1121 #[inline(always)]
1122 pub fn flt_coef_02(
1123 self,
1124 ) -> crate::common::RegisterField<
1125 0,
1126 0xffff,
1127 1,
1128 0,
1129 u16,
1130 u16,
1131 LraFltCoef2Reg_SPEC,
1132 crate::common::RW,
1133 > {
1134 crate::common::RegisterField::<
1135 0,
1136 0xffff,
1137 1,
1138 0,
1139 u16,
1140 u16,
1141 LraFltCoef2Reg_SPEC,
1142 crate::common::RW,
1143 >::from_register(self, 0)
1144 }
1145}
1146impl ::core::default::Default for LraFltCoef2Reg {
1147 #[inline(always)]
1148 fn default() -> LraFltCoef2Reg {
1149 <crate::RegValueT<LraFltCoef2Reg_SPEC> as RegisterValue<_>>::new(241569598)
1150 }
1151}
1152
1153#[doc(hidden)]
1154#[derive(Copy, Clone, Eq, PartialEq)]
1155pub struct LraFltCoef3Reg_SPEC;
1156impl crate::sealed::RegSpec for LraFltCoef3Reg_SPEC {
1157 type DataType = u32;
1158}
1159
1160#[doc = "LRA Filter Coefficient Register"]
1161pub type LraFltCoef3Reg = crate::RegValueT<LraFltCoef3Reg_SPEC>;
1162
1163impl LraFltCoef3Reg {
1164 #[doc = "Loop filter state-space coefficient b2 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).\nNote: For correct intended loop gain, modify the intended value of b1 to b1/ADC_GAIN, where\nADC_GAIN is the normalized gain of the ADC (i.e. ADC_GAIN = GP_ADC_VALUE´300 mA/\\[ILRA´128\\])."]
1165 #[inline(always)]
1166 pub fn flt_coef_12(
1167 self,
1168 ) -> crate::common::RegisterField<
1169 16,
1170 0xffff,
1171 1,
1172 0,
1173 u16,
1174 u16,
1175 LraFltCoef3Reg_SPEC,
1176 crate::common::RW,
1177 > {
1178 crate::common::RegisterField::<
1179 16,
1180 0xffff,
1181 1,
1182 0,
1183 u16,
1184 u16,
1185 LraFltCoef3Reg_SPEC,
1186 crate::common::RW,
1187 >::from_register(self, 0)
1188 }
1189
1190 #[doc = "Loop filter state-space coefficient a22 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)."]
1191 #[inline(always)]
1192 pub fn flt_coef_11(
1193 self,
1194 ) -> crate::common::RegisterField<
1195 0,
1196 0xffff,
1197 1,
1198 0,
1199 u16,
1200 u16,
1201 LraFltCoef3Reg_SPEC,
1202 crate::common::RW,
1203 > {
1204 crate::common::RegisterField::<
1205 0,
1206 0xffff,
1207 1,
1208 0,
1209 u16,
1210 u16,
1211 LraFltCoef3Reg_SPEC,
1212 crate::common::RW,
1213 >::from_register(self, 0)
1214 }
1215}
1216impl ::core::default::Default for LraFltCoef3Reg {
1217 #[inline(always)]
1218 fn default() -> LraFltCoef3Reg {
1219 <crate::RegValueT<LraFltCoef3Reg_SPEC> as RegisterValue<_>>::new(382599578)
1220 }
1221}
1222
1223#[doc(hidden)]
1224#[derive(Copy, Clone, Eq, PartialEq)]
1225pub struct LraFltSmp1Reg_SPEC;
1226impl crate::sealed::RegSpec for LraFltSmp1Reg_SPEC {
1227 type DataType = u32;
1228}
1229
1230#[doc = "LRA Sample Register"]
1231pub type LraFltSmp1Reg = crate::RegValueT<LraFltSmp1Reg_SPEC>;
1232
1233impl LraFltSmp1Reg {
1234 #[doc = "Second sample in first half-cycle used for resonance control algorithm."]
1235 #[inline(always)]
1236 pub fn lra_smp_2(
1237 self,
1238 ) -> crate::common::RegisterField<
1239 16,
1240 0xffff,
1241 1,
1242 0,
1243 u16,
1244 u16,
1245 LraFltSmp1Reg_SPEC,
1246 crate::common::R,
1247 > {
1248 crate::common::RegisterField::<
1249 16,
1250 0xffff,
1251 1,
1252 0,
1253 u16,
1254 u16,
1255 LraFltSmp1Reg_SPEC,
1256 crate::common::R,
1257 >::from_register(self, 0)
1258 }
1259
1260 #[doc = "First sample in first half-cycle used for resonance control algorithm."]
1261 #[inline(always)]
1262 pub fn lra_smp_1(
1263 self,
1264 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp1Reg_SPEC, crate::common::R>
1265 {
1266 crate::common::RegisterField::<
1267 0,
1268 0xffff,
1269 1,
1270 0,
1271 u16,
1272 u16,
1273 LraFltSmp1Reg_SPEC,
1274 crate::common::R,
1275 >::from_register(self, 0)
1276 }
1277}
1278impl ::core::default::Default for LraFltSmp1Reg {
1279 #[inline(always)]
1280 fn default() -> LraFltSmp1Reg {
1281 <crate::RegValueT<LraFltSmp1Reg_SPEC> as RegisterValue<_>>::new(0)
1282 }
1283}
1284
1285#[doc(hidden)]
1286#[derive(Copy, Clone, Eq, PartialEq)]
1287pub struct LraFltSmp2Reg_SPEC;
1288impl crate::sealed::RegSpec for LraFltSmp2Reg_SPEC {
1289 type DataType = u32;
1290}
1291
1292#[doc = "LRA Sample Register"]
1293pub type LraFltSmp2Reg = crate::RegValueT<LraFltSmp2Reg_SPEC>;
1294
1295impl LraFltSmp2Reg {
1296 #[doc = "Fourth sample in first half-cycle used for resonance control algorithm."]
1297 #[inline(always)]
1298 pub fn lra_smp_4(
1299 self,
1300 ) -> crate::common::RegisterField<
1301 16,
1302 0xffff,
1303 1,
1304 0,
1305 u16,
1306 u16,
1307 LraFltSmp2Reg_SPEC,
1308 crate::common::R,
1309 > {
1310 crate::common::RegisterField::<
1311 16,
1312 0xffff,
1313 1,
1314 0,
1315 u16,
1316 u16,
1317 LraFltSmp2Reg_SPEC,
1318 crate::common::R,
1319 >::from_register(self, 0)
1320 }
1321
1322 #[doc = "Third sample in first half-cycle used for resonance control algorithm."]
1323 #[inline(always)]
1324 pub fn lra_smp_3(
1325 self,
1326 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp2Reg_SPEC, crate::common::R>
1327 {
1328 crate::common::RegisterField::<
1329 0,
1330 0xffff,
1331 1,
1332 0,
1333 u16,
1334 u16,
1335 LraFltSmp2Reg_SPEC,
1336 crate::common::R,
1337 >::from_register(self, 0)
1338 }
1339}
1340impl ::core::default::Default for LraFltSmp2Reg {
1341 #[inline(always)]
1342 fn default() -> LraFltSmp2Reg {
1343 <crate::RegValueT<LraFltSmp2Reg_SPEC> as RegisterValue<_>>::new(0)
1344 }
1345}
1346
1347#[doc(hidden)]
1348#[derive(Copy, Clone, Eq, PartialEq)]
1349pub struct LraFltSmp3Reg_SPEC;
1350impl crate::sealed::RegSpec for LraFltSmp3Reg_SPEC {
1351 type DataType = u32;
1352}
1353
1354#[doc = "LRA Sample Register"]
1355pub type LraFltSmp3Reg = crate::RegValueT<LraFltSmp3Reg_SPEC>;
1356
1357impl LraFltSmp3Reg {
1358 #[doc = "Sixth sample in first half-cycle used for resonance control algorithm."]
1359 #[inline(always)]
1360 pub fn lra_smp_6(
1361 self,
1362 ) -> crate::common::RegisterField<
1363 16,
1364 0xffff,
1365 1,
1366 0,
1367 u16,
1368 u16,
1369 LraFltSmp3Reg_SPEC,
1370 crate::common::R,
1371 > {
1372 crate::common::RegisterField::<
1373 16,
1374 0xffff,
1375 1,
1376 0,
1377 u16,
1378 u16,
1379 LraFltSmp3Reg_SPEC,
1380 crate::common::R,
1381 >::from_register(self, 0)
1382 }
1383
1384 #[doc = "Fifth sample in first half-cycle used for resonance control algorithm."]
1385 #[inline(always)]
1386 pub fn lra_smp_5(
1387 self,
1388 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp3Reg_SPEC, crate::common::R>
1389 {
1390 crate::common::RegisterField::<
1391 0,
1392 0xffff,
1393 1,
1394 0,
1395 u16,
1396 u16,
1397 LraFltSmp3Reg_SPEC,
1398 crate::common::R,
1399 >::from_register(self, 0)
1400 }
1401}
1402impl ::core::default::Default for LraFltSmp3Reg {
1403 #[inline(always)]
1404 fn default() -> LraFltSmp3Reg {
1405 <crate::RegValueT<LraFltSmp3Reg_SPEC> as RegisterValue<_>>::new(0)
1406 }
1407}
1408
1409#[doc(hidden)]
1410#[derive(Copy, Clone, Eq, PartialEq)]
1411pub struct LraFltSmp4Reg_SPEC;
1412impl crate::sealed::RegSpec for LraFltSmp4Reg_SPEC {
1413 type DataType = u32;
1414}
1415
1416#[doc = "LRA Sample Register"]
1417pub type LraFltSmp4Reg = crate::RegValueT<LraFltSmp4Reg_SPEC>;
1418
1419impl LraFltSmp4Reg {
1420 #[doc = "Eighth sample in first half-cycle used for resonance control algorithm."]
1421 #[inline(always)]
1422 pub fn lra_smp_8(
1423 self,
1424 ) -> crate::common::RegisterField<
1425 16,
1426 0xffff,
1427 1,
1428 0,
1429 u16,
1430 u16,
1431 LraFltSmp4Reg_SPEC,
1432 crate::common::R,
1433 > {
1434 crate::common::RegisterField::<
1435 16,
1436 0xffff,
1437 1,
1438 0,
1439 u16,
1440 u16,
1441 LraFltSmp4Reg_SPEC,
1442 crate::common::R,
1443 >::from_register(self, 0)
1444 }
1445
1446 #[doc = "Seventh sample in first half-cycle used for resonance control algorithm."]
1447 #[inline(always)]
1448 pub fn lra_smp_7(
1449 self,
1450 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp4Reg_SPEC, crate::common::R>
1451 {
1452 crate::common::RegisterField::<
1453 0,
1454 0xffff,
1455 1,
1456 0,
1457 u16,
1458 u16,
1459 LraFltSmp4Reg_SPEC,
1460 crate::common::R,
1461 >::from_register(self, 0)
1462 }
1463}
1464impl ::core::default::Default for LraFltSmp4Reg {
1465 #[inline(always)]
1466 fn default() -> LraFltSmp4Reg {
1467 <crate::RegValueT<LraFltSmp4Reg_SPEC> as RegisterValue<_>>::new(0)
1468 }
1469}
1470
1471#[doc(hidden)]
1472#[derive(Copy, Clone, Eq, PartialEq)]
1473pub struct LraFltSmp5Reg_SPEC;
1474impl crate::sealed::RegSpec for LraFltSmp5Reg_SPEC {
1475 type DataType = u32;
1476}
1477
1478#[doc = "LRA Sample Register"]
1479pub type LraFltSmp5Reg = crate::RegValueT<LraFltSmp5Reg_SPEC>;
1480
1481impl LraFltSmp5Reg {
1482 #[doc = "Second sample in second half-cycle used for resonance control algorithm."]
1483 #[inline(always)]
1484 pub fn lra_smp_10(
1485 self,
1486 ) -> crate::common::RegisterField<
1487 16,
1488 0xffff,
1489 1,
1490 0,
1491 u16,
1492 u16,
1493 LraFltSmp5Reg_SPEC,
1494 crate::common::R,
1495 > {
1496 crate::common::RegisterField::<
1497 16,
1498 0xffff,
1499 1,
1500 0,
1501 u16,
1502 u16,
1503 LraFltSmp5Reg_SPEC,
1504 crate::common::R,
1505 >::from_register(self, 0)
1506 }
1507
1508 #[doc = "First sample in second half-cycle used for resonance control algorithm."]
1509 #[inline(always)]
1510 pub fn lra_smp_9(
1511 self,
1512 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp5Reg_SPEC, crate::common::R>
1513 {
1514 crate::common::RegisterField::<
1515 0,
1516 0xffff,
1517 1,
1518 0,
1519 u16,
1520 u16,
1521 LraFltSmp5Reg_SPEC,
1522 crate::common::R,
1523 >::from_register(self, 0)
1524 }
1525}
1526impl ::core::default::Default for LraFltSmp5Reg {
1527 #[inline(always)]
1528 fn default() -> LraFltSmp5Reg {
1529 <crate::RegValueT<LraFltSmp5Reg_SPEC> as RegisterValue<_>>::new(0)
1530 }
1531}
1532
1533#[doc(hidden)]
1534#[derive(Copy, Clone, Eq, PartialEq)]
1535pub struct LraFltSmp6Reg_SPEC;
1536impl crate::sealed::RegSpec for LraFltSmp6Reg_SPEC {
1537 type DataType = u32;
1538}
1539
1540#[doc = "LRA Sample Register"]
1541pub type LraFltSmp6Reg = crate::RegValueT<LraFltSmp6Reg_SPEC>;
1542
1543impl LraFltSmp6Reg {
1544 #[doc = "Fourth sample in second half-cycle used for resonance control algorithm."]
1545 #[inline(always)]
1546 pub fn lra_smp_12(
1547 self,
1548 ) -> crate::common::RegisterField<
1549 16,
1550 0xffff,
1551 1,
1552 0,
1553 u16,
1554 u16,
1555 LraFltSmp6Reg_SPEC,
1556 crate::common::R,
1557 > {
1558 crate::common::RegisterField::<
1559 16,
1560 0xffff,
1561 1,
1562 0,
1563 u16,
1564 u16,
1565 LraFltSmp6Reg_SPEC,
1566 crate::common::R,
1567 >::from_register(self, 0)
1568 }
1569
1570 #[doc = "Third sample in second half-cycle used for resonance control algorithm."]
1571 #[inline(always)]
1572 pub fn lra_smp_11(
1573 self,
1574 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp6Reg_SPEC, crate::common::R>
1575 {
1576 crate::common::RegisterField::<
1577 0,
1578 0xffff,
1579 1,
1580 0,
1581 u16,
1582 u16,
1583 LraFltSmp6Reg_SPEC,
1584 crate::common::R,
1585 >::from_register(self, 0)
1586 }
1587}
1588impl ::core::default::Default for LraFltSmp6Reg {
1589 #[inline(always)]
1590 fn default() -> LraFltSmp6Reg {
1591 <crate::RegValueT<LraFltSmp6Reg_SPEC> as RegisterValue<_>>::new(0)
1592 }
1593}
1594
1595#[doc(hidden)]
1596#[derive(Copy, Clone, Eq, PartialEq)]
1597pub struct LraFltSmp7Reg_SPEC;
1598impl crate::sealed::RegSpec for LraFltSmp7Reg_SPEC {
1599 type DataType = u32;
1600}
1601
1602#[doc = "LRA Sample Register"]
1603pub type LraFltSmp7Reg = crate::RegValueT<LraFltSmp7Reg_SPEC>;
1604
1605impl LraFltSmp7Reg {
1606 #[doc = "Sixth sample in second half-cycle used for resonance control algorithm."]
1607 #[inline(always)]
1608 pub fn lra_smp_14(
1609 self,
1610 ) -> crate::common::RegisterField<
1611 16,
1612 0xffff,
1613 1,
1614 0,
1615 u16,
1616 u16,
1617 LraFltSmp7Reg_SPEC,
1618 crate::common::R,
1619 > {
1620 crate::common::RegisterField::<
1621 16,
1622 0xffff,
1623 1,
1624 0,
1625 u16,
1626 u16,
1627 LraFltSmp7Reg_SPEC,
1628 crate::common::R,
1629 >::from_register(self, 0)
1630 }
1631
1632 #[doc = "Fifth sample in second half-cycle used for resonance control algorithm."]
1633 #[inline(always)]
1634 pub fn lra_smp_13(
1635 self,
1636 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp7Reg_SPEC, crate::common::R>
1637 {
1638 crate::common::RegisterField::<
1639 0,
1640 0xffff,
1641 1,
1642 0,
1643 u16,
1644 u16,
1645 LraFltSmp7Reg_SPEC,
1646 crate::common::R,
1647 >::from_register(self, 0)
1648 }
1649}
1650impl ::core::default::Default for LraFltSmp7Reg {
1651 #[inline(always)]
1652 fn default() -> LraFltSmp7Reg {
1653 <crate::RegValueT<LraFltSmp7Reg_SPEC> as RegisterValue<_>>::new(0)
1654 }
1655}
1656
1657#[doc(hidden)]
1658#[derive(Copy, Clone, Eq, PartialEq)]
1659pub struct LraFltSmp8Reg_SPEC;
1660impl crate::sealed::RegSpec for LraFltSmp8Reg_SPEC {
1661 type DataType = u32;
1662}
1663
1664#[doc = "LRA Sample Register"]
1665pub type LraFltSmp8Reg = crate::RegValueT<LraFltSmp8Reg_SPEC>;
1666
1667impl LraFltSmp8Reg {
1668 #[doc = "Eighth sample in second half-cycle used for resonance control algorithm."]
1669 #[inline(always)]
1670 pub fn lra_smp_16(
1671 self,
1672 ) -> crate::common::RegisterField<
1673 16,
1674 0xffff,
1675 1,
1676 0,
1677 u16,
1678 u16,
1679 LraFltSmp8Reg_SPEC,
1680 crate::common::R,
1681 > {
1682 crate::common::RegisterField::<
1683 16,
1684 0xffff,
1685 1,
1686 0,
1687 u16,
1688 u16,
1689 LraFltSmp8Reg_SPEC,
1690 crate::common::R,
1691 >::from_register(self, 0)
1692 }
1693
1694 #[doc = "Seventh sample in second half-cycle used for resonance control algorithm."]
1695 #[inline(always)]
1696 pub fn lra_smp_15(
1697 self,
1698 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LraFltSmp8Reg_SPEC, crate::common::R>
1699 {
1700 crate::common::RegisterField::<
1701 0,
1702 0xffff,
1703 1,
1704 0,
1705 u16,
1706 u16,
1707 LraFltSmp8Reg_SPEC,
1708 crate::common::R,
1709 >::from_register(self, 0)
1710 }
1711}
1712impl ::core::default::Default for LraFltSmp8Reg {
1713 #[inline(always)]
1714 fn default() -> LraFltSmp8Reg {
1715 <crate::RegValueT<LraFltSmp8Reg_SPEC> as RegisterValue<_>>::new(0)
1716 }
1717}
1718
1719#[doc(hidden)]
1720#[derive(Copy, Clone, Eq, PartialEq)]
1721pub struct LraLdoReg_SPEC;
1722impl crate::sealed::RegSpec for LraLdoReg_SPEC {
1723 type DataType = u32;
1724}
1725
1726#[doc = "LRA LDO Regsiter"]
1727pub type LraLdoReg = crate::RegValueT<LraLdoReg_SPEC>;
1728
1729impl LraLdoReg {
1730 #[doc = "0: LDO not yet ok\n1: LDO voltage is ready"]
1731 #[inline(always)]
1732 pub fn ldo_ok(
1733 self,
1734 ) -> crate::common::RegisterFieldBool<31, 1, 0, LraLdoReg_SPEC, crate::common::R> {
1735 crate::common::RegisterFieldBool::<31,1,0,LraLdoReg_SPEC,crate::common::R>::from_register(self,0)
1736 }
1737
1738 #[doc = "When set to 1, LDO output is connected to the testbus through a test switch"]
1739 #[inline(always)]
1740 pub fn ldo_tst(
1741 self,
1742 ) -> crate::common::RegisterFieldBool<1, 1, 0, LraLdoReg_SPEC, crate::common::RW> {
1743 crate::common::RegisterFieldBool::<1,1,0,LraLdoReg_SPEC,crate::common::RW>::from_register(self,0)
1744 }
1745
1746 #[doc = "0: Indicates that the reference input is tracked,\n1: Indicates that the reference input is sampled"]
1747 #[inline(always)]
1748 pub fn ldo_vref_hold(
1749 self,
1750 ) -> crate::common::RegisterFieldBool<0, 1, 0, LraLdoReg_SPEC, crate::common::RW> {
1751 crate::common::RegisterFieldBool::<0,1,0,LraLdoReg_SPEC,crate::common::RW>::from_register(self,0)
1752 }
1753}
1754impl ::core::default::Default for LraLdoReg {
1755 #[inline(always)]
1756 fn default() -> LraLdoReg {
1757 <crate::RegValueT<LraLdoReg_SPEC> as RegisterValue<_>>::new(0)
1758 }
1759}