da14697_pac/
gpadc.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"GPADC registers"]
28unsafe impl ::core::marker::Send for super::Gpadc {}
29unsafe impl ::core::marker::Sync for super::Gpadc {}
30impl super::Gpadc {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "General Purpose ADC Clear Interrupt Register"]
38    #[inline(always)]
39    pub const fn gp_adc_clear_int_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::GpAdcClearIntReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::GpAdcClearIntReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(20usize),
45            )
46        }
47    }
48
49    #[doc = "General Purpose ADC Second Control Register"]
50    #[inline(always)]
51    pub const fn gp_adc_ctrl2_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::GpAdcCtrl2Reg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::GpAdcCtrl2Reg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "General Purpose ADC Third Control Register"]
62    #[inline(always)]
63    pub const fn gp_adc_ctrl3_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::GpAdcCtrl3Reg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::GpAdcCtrl3Reg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "General Purpose ADC Control Register"]
74    #[inline(always)]
75    pub const fn gp_adc_ctrl_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::GpAdcCtrlReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::GpAdcCtrlReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(0usize),
81            )
82        }
83    }
84
85    #[doc = "General Purpose ADC Negative Offset Register"]
86    #[inline(always)]
87    pub const fn gp_adc_offn_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::GpAdcOffnReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::GpAdcOffnReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(16usize),
93            )
94        }
95    }
96
97    #[doc = "General Purpose ADC Positive Offset Register"]
98    #[inline(always)]
99    pub const fn gp_adc_offp_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::GpAdcOffpReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::GpAdcOffpReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(12usize),
105            )
106        }
107    }
108
109    #[doc = "General Purpose ADC Result Register"]
110    #[inline(always)]
111    pub const fn gp_adc_result_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::GpAdcResultReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::GpAdcResultReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(24usize),
117            )
118        }
119    }
120}
121#[doc(hidden)]
122#[derive(Copy, Clone, Eq, PartialEq)]
123pub struct GpAdcClearIntReg_SPEC;
124impl crate::sealed::RegSpec for GpAdcClearIntReg_SPEC {
125    type DataType = u32;
126}
127
128#[doc = "General Purpose ADC Clear Interrupt Register"]
129pub type GpAdcClearIntReg = crate::RegValueT<GpAdcClearIntReg_SPEC>;
130
131impl GpAdcClearIntReg {
132    #[doc = "Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0."]
133    #[inline(always)]
134    pub fn gp_adc_clr_int(
135        self,
136    ) -> crate::common::RegisterField<
137        0,
138        0xffff,
139        1,
140        0,
141        u16,
142        u16,
143        GpAdcClearIntReg_SPEC,
144        crate::common::W,
145    > {
146        crate::common::RegisterField::<
147            0,
148            0xffff,
149            1,
150            0,
151            u16,
152            u16,
153            GpAdcClearIntReg_SPEC,
154            crate::common::W,
155        >::from_register(self, 0)
156    }
157}
158impl ::core::default::Default for GpAdcClearIntReg {
159    #[inline(always)]
160    fn default() -> GpAdcClearIntReg {
161        <crate::RegValueT<GpAdcClearIntReg_SPEC> as RegisterValue<_>>::new(0)
162    }
163}
164
165#[doc(hidden)]
166#[derive(Copy, Clone, Eq, PartialEq)]
167pub struct GpAdcCtrl2Reg_SPEC;
168impl crate::sealed::RegSpec for GpAdcCtrl2Reg_SPEC {
169    type DataType = u32;
170}
171
172#[doc = "General Purpose ADC Second Control Register"]
173pub type GpAdcCtrl2Reg = crate::RegValueT<GpAdcCtrl2Reg_SPEC>;
174
175impl GpAdcCtrl2Reg {
176    #[doc = "0: Data is stored after handshake synchronisation\n1: Data is stored two ADC_CLK cycles after internal start trigger\n15: Data is stored sixteen ADC_CLK cycles after internal start trigger"]
177    #[inline(always)]
178    pub fn gp_adc_store_del(
179        self,
180    ) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, GpAdcCtrl2Reg_SPEC, crate::common::RW>
181    {
182        crate::common::RegisterField::<12,0xf,1,0,u8,u8,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
183    }
184
185    #[doc = "0: The sample time (switch is closed) is one ADC_CLK cycle\n1: The sample time is 1*32 ADC_CLK cycles\n2: The sample time is 2*32 ADC_CLK cycles\n15: The sample time is 15*32 ADC_CLK cycles"]
186    #[inline(always)]
187    pub fn gp_adc_smpl_time(
188        self,
189    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, GpAdcCtrl2Reg_SPEC, crate::common::RW>
190    {
191        crate::common::RegisterField::<8,0xf,1,0,u8,u8,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
192    }
193
194    #[doc = "0: 1 sample is taken or 2 in case ADC_CHOP is active.\n1: 2 samples are taken.\n2: 4 samples are taken.\n7: 128 samples are taken."]
195    #[inline(always)]
196    pub fn gp_adc_conv_nrs(
197        self,
198    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, GpAdcCtrl2Reg_SPEC, crate::common::RW>
199    {
200        crate::common::RegisterField::<5,0x7,1,0,u8,u8,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
201    }
202
203    #[doc = "0: DMA functionality disabled\n1: DMA functionality enabled"]
204    #[inline(always)]
205    pub fn gp_adc_dma_en(
206        self,
207    ) -> crate::common::RegisterFieldBool<3, 1, 0, GpAdcCtrl2Reg_SPEC, crate::common::RW> {
208        crate::common::RegisterFieldBool::<3,1,0,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
209    }
210
211    #[doc = "1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC."]
212    #[inline(always)]
213    pub fn gp_adc_i20u(
214        self,
215    ) -> crate::common::RegisterFieldBool<2, 1, 0, GpAdcCtrl2Reg_SPEC, crate::common::RW> {
216        crate::common::RegisterFieldBool::<2,1,0,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
217    }
218
219    #[doc = "1: Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC."]
220    #[inline(always)]
221    pub fn gp_adc_idyn(
222        self,
223    ) -> crate::common::RegisterFieldBool<1, 1, 0, GpAdcCtrl2Reg_SPEC, crate::common::RW> {
224        crate::common::RegisterFieldBool::<1,1,0,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
225    }
226
227    #[doc = "0: Input voltages up to 1.2V allowed.\n1: Input voltages up to 3.6V allowed by enabling 3x attenuator. (if ADC_SEL=7 or 8, this bit is automatically set to 1) Enabling the attenuator requires a longer sampling time."]
228    #[inline(always)]
229    pub fn gp_adc_attn3x(
230        self,
231    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpAdcCtrl2Reg_SPEC, crate::common::RW> {
232        crate::common::RegisterFieldBool::<0,1,0,GpAdcCtrl2Reg_SPEC,crate::common::RW>::from_register(self,0)
233    }
234}
235impl ::core::default::Default for GpAdcCtrl2Reg {
236    #[inline(always)]
237    fn default() -> GpAdcCtrl2Reg {
238        <crate::RegValueT<GpAdcCtrl2Reg_SPEC> as RegisterValue<_>>::new(0)
239    }
240}
241
242#[doc(hidden)]
243#[derive(Copy, Clone, Eq, PartialEq)]
244pub struct GpAdcCtrl3Reg_SPEC;
245impl crate::sealed::RegSpec for GpAdcCtrl3Reg_SPEC {
246    type DataType = u32;
247}
248
249#[doc = "General Purpose ADC Third Control Register"]
250pub type GpAdcCtrl3Reg = crate::RegValueT<GpAdcCtrl3Reg_SPEC>;
251
252impl GpAdcCtrl3Reg {
253    #[doc = "Defines the interval between two ADC conversions in case GP_ADC_CONT is set.\n0: No extra delay between two conversions.\n1: 1.024ms interval between two conversions.\n2: 2.048ms interval between two conversions.\n255: 261.12ms interval between two conversions."]
254    #[inline(always)]
255    pub fn gp_adc_interval(
256        self,
257    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, GpAdcCtrl3Reg_SPEC, crate::common::RW>
258    {
259        crate::common::RegisterField::<8,0xff,1,0,u8,u8,GpAdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
260    }
261
262    #[doc = "Defines the delay for enabling the ADC after enabling the LDO.\n0: Not allowed\n1: 32x ADC_CLK period.\nn: n*32x ADC_CLK period."]
263    #[inline(always)]
264    pub fn gp_adc_en_del(
265        self,
266    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, GpAdcCtrl3Reg_SPEC, crate::common::RW>
267    {
268        crate::common::RegisterField::<0,0xff,1,0,u8,u8,GpAdcCtrl3Reg_SPEC,crate::common::RW>::from_register(self,0)
269    }
270}
271impl ::core::default::Default for GpAdcCtrl3Reg {
272    #[inline(always)]
273    fn default() -> GpAdcCtrl3Reg {
274        <crate::RegValueT<GpAdcCtrl3Reg_SPEC> as RegisterValue<_>>::new(64)
275    }
276}
277
278#[doc(hidden)]
279#[derive(Copy, Clone, Eq, PartialEq)]
280pub struct GpAdcCtrlReg_SPEC;
281impl crate::sealed::RegSpec for GpAdcCtrlReg_SPEC {
282    type DataType = u32;
283}
284
285#[doc = "General Purpose ADC Control Register"]
286pub type GpAdcCtrlReg = crate::RegValueT<GpAdcCtrlReg_SPEC>;
287
288impl GpAdcCtrlReg {
289    #[doc = "1: Enable the on-chip temperature sensors"]
290    #[inline(always)]
291    pub fn gp_adc_diff_temp_en(
292        self,
293    ) -> crate::common::RegisterFieldBool<18, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
294        crate::common::RegisterFieldBool::<18,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
295    }
296
297    #[doc = "0= Gnd, 1 =sensor near radio, 2 =sensor near charger, 3 =sensor near bandgap\nwith sensors disabled (GP_ADC_DIFF_TEMP_EN = 0) :0 = GND 1 = Z, 2= V(ntc) from charger, 3 = V(temp) from charger"]
298    #[inline(always)]
299    pub fn gp_adc_diff_temp_sel(
300        self,
301    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, GpAdcCtrlReg_SPEC, crate::common::RW>
302    {
303        crate::common::RegisterField::<16,0x3,1,0,u8,u8,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
304    }
305
306    #[doc = "1: Samples and disconnects VREF, should be refreshed frequently. Note that the LDO consumpes power when bit is set."]
307    #[inline(always)]
308    pub fn gp_adc_ldo_zero(
309        self,
310    ) -> crate::common::RegisterFieldBool<15, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
311        crate::common::RegisterFieldBool::<15,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
312    }
313
314    #[doc = "0: Chopper mode off\n1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC; Highly recommended for DC-measurements."]
315    #[inline(always)]
316    pub fn gp_adc_chop(
317        self,
318    ) -> crate::common::RegisterFieldBool<14, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
319        crate::common::RegisterFieldBool::<14,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
320    }
321
322    #[doc = "0: Default\n1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency"]
323    #[inline(always)]
324    pub fn gp_adc_sign(
325        self,
326    ) -> crate::common::RegisterFieldBool<13, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
327        crate::common::RegisterFieldBool::<13,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
328    }
329
330    #[doc = "ADC input selection.\nIf GP_ADC_SE = 1 (single ended mode):\n0: GP ADC0 (P1_09)\n1: GP ADC1 (P0_25)\n2: GP ADC2 (P0_08)\n3: MUX ( CH 21:16)\\]\n4: VDDD ( internal)\n5: V30 (GP_ADC_ATTN3X scaler automatically selected)\n6: V30 (GP_ADC_ATTN3X scaler automatically selected)\n7: DCDC (GP_ADC_ATTN3X scaler automatically selected)\n8: VBAT (5V to 1.2V scaler selected)\n9: VSSA\n10: Radio Test Out<0>\n11 :Radio Test Out<1>\n12: Radio Test In<0>\n13: Radio Test In<1>\n14: 3V3 Testbus\n15: 1V2 Testbus\n16: GP ADC3 (P0_09)\n17: GP ADC4 (P1_13)\n18: GP ADC5 (P1_12)\n19: GP ADC6 (P1_18)\n20: GP ADC7 (P1_19)\n21: Diff Temperature sensor, See GP_ADC_DIFF_TEMP_SEL\nAll other combinations are reserved.\nIf GP_ADC_SE = 0 (differential mode):\n0: P1\\[09\\] vs P0\\[25\\]\nAll other combinations are P0\\[08\\] vs P0\\[09\\]."]
331    #[inline(always)]
332    pub fn gp_adc_sel(
333        self,
334    ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, GpAdcCtrlReg_SPEC, crate::common::RW>
335    {
336        crate::common::RegisterField::<8,0x1f,1,0,u8,u8,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
337    }
338
339    #[doc = "0: Normal operation\n1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC)."]
340    #[inline(always)]
341    pub fn gp_adc_mute(
342        self,
343    ) -> crate::common::RegisterFieldBool<7, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
344        crate::common::RegisterFieldBool::<7,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
345    }
346
347    #[doc = "0: Differential mode\n1: Single ended mode"]
348    #[inline(always)]
349    pub fn gp_adc_se(
350        self,
351    ) -> crate::common::RegisterFieldBool<6, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
352        crate::common::RegisterFieldBool::<6,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
353    }
354
355    #[doc = "0: Disable (mask) GP_ADC_INT.\n1: Enable GP_ADC_INT to ICU."]
356    #[inline(always)]
357    pub fn gp_adc_mint(
358        self,
359    ) -> crate::common::RegisterFieldBool<5, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
360        crate::common::RegisterFieldBool::<5,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
361    }
362
363    #[doc = "1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG."]
364    #[inline(always)]
365    pub fn gp_adc_int(
366        self,
367    ) -> crate::common::RegisterFieldBool<4, 1, 0, GpAdcCtrlReg_SPEC, crate::common::R> {
368        crate::common::RegisterFieldBool::<4,1,0,GpAdcCtrlReg_SPEC,crate::common::R>::from_register(self,0)
369    }
370
371    #[doc = "0: Internal high-speed ADC clock used (recommended).\n1: Digital clock used (ADC_CLK)."]
372    #[inline(always)]
373    pub fn gp_adc_clk_sel(
374        self,
375    ) -> crate::common::RegisterFieldBool<3, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
376        crate::common::RegisterFieldBool::<3,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
377    }
378
379    #[doc = "0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit.\n1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL."]
380    #[inline(always)]
381    pub fn gp_adc_cont(
382        self,
383    ) -> crate::common::RegisterFieldBool<2, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
384        crate::common::RegisterFieldBool::<2,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
385    }
386
387    #[doc = "0: ADC conversion ready.\n1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero."]
388    #[inline(always)]
389    pub fn gp_adc_start(
390        self,
391    ) -> crate::common::RegisterFieldBool<1, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
392        crate::common::RegisterFieldBool::<1,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
393    }
394
395    #[doc = "0: LDO is off and ADC is disabled..\n1: LDO is turned on and afterwards the ADC is enabled."]
396    #[inline(always)]
397    pub fn gp_adc_en(
398        self,
399    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpAdcCtrlReg_SPEC, crate::common::RW> {
400        crate::common::RegisterFieldBool::<0,1,0,GpAdcCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
401    }
402}
403impl ::core::default::Default for GpAdcCtrlReg {
404    #[inline(always)]
405    fn default() -> GpAdcCtrlReg {
406        <crate::RegValueT<GpAdcCtrlReg_SPEC> as RegisterValue<_>>::new(0)
407    }
408}
409
410#[doc(hidden)]
411#[derive(Copy, Clone, Eq, PartialEq)]
412pub struct GpAdcOffnReg_SPEC;
413impl crate::sealed::RegSpec for GpAdcOffnReg_SPEC {
414    type DataType = u32;
415}
416
417#[doc = "General Purpose ADC Negative Offset Register"]
418pub type GpAdcOffnReg = crate::RegValueT<GpAdcOffnReg_SPEC>;
419
420impl GpAdcOffnReg {
421    #[doc = "Offset adjust of \'negative\' array of ADC-network (effective if \"GP_ADC_SE=0\", or \"GP_ADC_SE=1 AND GP_ADC_SIGN=1\")"]
422    #[inline(always)]
423    pub fn gp_adc_offn(
424        self,
425    ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, GpAdcOffnReg_SPEC, crate::common::RW>
426    {
427        crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,GpAdcOffnReg_SPEC,crate::common::RW>::from_register(self,0)
428    }
429}
430impl ::core::default::Default for GpAdcOffnReg {
431    #[inline(always)]
432    fn default() -> GpAdcOffnReg {
433        <crate::RegValueT<GpAdcOffnReg_SPEC> as RegisterValue<_>>::new(512)
434    }
435}
436
437#[doc(hidden)]
438#[derive(Copy, Clone, Eq, PartialEq)]
439pub struct GpAdcOffpReg_SPEC;
440impl crate::sealed::RegSpec for GpAdcOffpReg_SPEC {
441    type DataType = u32;
442}
443
444#[doc = "General Purpose ADC Positive Offset Register"]
445pub type GpAdcOffpReg = crate::RegValueT<GpAdcOffpReg_SPEC>;
446
447impl GpAdcOffpReg {
448    #[doc = "Offset adjust of \'positive\' array of ADC-network (effective if \"GP_ADC_SE=0\", or \"GP_ADC_SE=1 AND GP_ADC_SIGN=0\")"]
449    #[inline(always)]
450    pub fn gp_adc_offp(
451        self,
452    ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, GpAdcOffpReg_SPEC, crate::common::RW>
453    {
454        crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,GpAdcOffpReg_SPEC,crate::common::RW>::from_register(self,0)
455    }
456}
457impl ::core::default::Default for GpAdcOffpReg {
458    #[inline(always)]
459    fn default() -> GpAdcOffpReg {
460        <crate::RegValueT<GpAdcOffpReg_SPEC> as RegisterValue<_>>::new(512)
461    }
462}
463
464#[doc(hidden)]
465#[derive(Copy, Clone, Eq, PartialEq)]
466pub struct GpAdcResultReg_SPEC;
467impl crate::sealed::RegSpec for GpAdcResultReg_SPEC {
468    type DataType = u32;
469}
470
471#[doc = "General Purpose ADC Result Register"]
472pub type GpAdcResultReg = crate::RegValueT<GpAdcResultReg_SPEC>;
473
474impl GpAdcResultReg {
475    #[doc = "Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits."]
476    #[inline(always)]
477    pub fn gp_adc_val(
478        self,
479    ) -> crate::common::RegisterField<
480        0,
481        0xffff,
482        1,
483        0,
484        u16,
485        u16,
486        GpAdcResultReg_SPEC,
487        crate::common::R,
488    > {
489        crate::common::RegisterField::<
490            0,
491            0xffff,
492            1,
493            0,
494            u16,
495            u16,
496            GpAdcResultReg_SPEC,
497            crate::common::R,
498        >::from_register(self, 0)
499    }
500}
501impl ::core::default::Default for GpAdcResultReg {
502    #[inline(always)]
503    fn default() -> GpAdcResultReg {
504        <crate::RegValueT<GpAdcResultReg_SPEC> as RegisterValue<_>>::new(0)
505    }
506}
da14697_pac/gpadc.rs

da14697_pac/
gpadc.rs
