da14697_pac/
sys_wdog.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"SYS_WDOG registers"]
28unsafe impl ::core::marker::Send for super::SysWdog {}
29unsafe impl ::core::marker::Sync for super::SysWdog {}
30impl super::SysWdog {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Watchdog control register."]
38    #[inline(always)]
39    pub const fn watchdog_ctrl_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::WatchdogCtrlReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::WatchdogCtrlReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(4usize),
45            )
46        }
47    }
48
49    #[doc = "Watchdog timer register."]
50    #[inline(always)]
51    pub const fn watchdog_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::WatchdogReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::WatchdogReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60}
61#[doc(hidden)]
62#[derive(Copy, Clone, Eq, PartialEq)]
63pub struct WatchdogCtrlReg_SPEC;
64impl crate::sealed::RegSpec for WatchdogCtrlReg_SPEC {
65    type DataType = u32;
66}
67
68#[doc = "Watchdog control register."]
69pub type WatchdogCtrlReg = crate::RegValueT<WatchdogCtrlReg_SPEC>;
70
71impl WatchdogCtrlReg {
72    #[doc = "0 = A new WATCHDOG_REG\\[WDOG_VAL\\] can be written.\n1 = No new WATCHDOG_REG\\[WDOG_VAL\\] can be written.\nNote: It takes some time before the programmed WDOG_VAL is updated in the (independent) Watchdog timer. During this time it is not possible to write a new value to WATCHDOG_REG\\[WDOG_VAL\\]."]
73    #[inline(always)]
74    pub fn write_busy(
75        self,
76    ) -> crate::common::RegisterFieldBool<3, 1, 0, WatchdogCtrlReg_SPEC, crate::common::R> {
77        crate::common::RegisterFieldBool::<3,1,0,WatchdogCtrlReg_SPEC,crate::common::R>::from_register(self,0)
78    }
79
80    #[doc = "0 = Watchdog timer can not be frozen when NMI_RST=0.\n1 = Watchdog timer can be frozen/resumed using\nSET_FREEZE_REG\\[FRZ_WDOG\\]/\nRESET_FREEZE_REG\\[FRZ_WDOG\\] when NMI_RST=0."]
81    #[inline(always)]
82    pub fn wdog_freeze_en(
83        self,
84    ) -> crate::common::RegisterFieldBool<2, 1, 0, WatchdogCtrlReg_SPEC, crate::common::RW> {
85        crate::common::RegisterFieldBool::<2,1,0,WatchdogCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
86    }
87
88    #[doc = "0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <= -16. Timer can be frozen/resumed using\nSET_FREEZE_REG\\[FRZ_WDOG\\]/\nRESET_FREEZE_REG\\[FRZ_WDOG\\].\n1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software.\nNote that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset.\nThe watchdog is always frozen when the Cortex-M33 is halted in DEBUG State."]
89    #[inline(always)]
90    pub fn nmi_rst(
91        self,
92    ) -> crate::common::RegisterFieldBool<0, 1, 0, WatchdogCtrlReg_SPEC, crate::common::RW> {
93        crate::common::RegisterFieldBool::<0,1,0,WatchdogCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
94    }
95}
96impl ::core::default::Default for WatchdogCtrlReg {
97    #[inline(always)]
98    fn default() -> WatchdogCtrlReg {
99        <crate::RegValueT<WatchdogCtrlReg_SPEC> as RegisterValue<_>>::new(6)
100    }
101}
102
103#[doc(hidden)]
104#[derive(Copy, Clone, Eq, PartialEq)]
105pub struct WatchdogReg_SPEC;
106impl crate::sealed::RegSpec for WatchdogReg_SPEC {
107    type DataType = u32;
108}
109
110#[doc = "Watchdog timer register."]
111pub type WatchdogReg = crate::RegValueT<WatchdogReg_SPEC>;
112
113impl WatchdogReg {
114    #[doc = "Bit \\[31:14\\] = 0 = Write enable for Watchdog timer\nelse Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away."]
115    #[inline(always)]
116    pub fn wdog_wen(
117        self,
118    ) -> crate::common::RegisterField<14, 0x3ffff, 1, 0, u32, u32, WatchdogReg_SPEC, crate::common::W>
119    {
120        crate::common::RegisterField::<
121            14,
122            0x3ffff,
123            1,
124            0,
125            u32,
126            u32,
127            WatchdogReg_SPEC,
128            crate::common::W,
129        >::from_register(self, 0)
130    }
131
132    #[doc = "0 = Watchdog timer value is positive.\n1 = Watchdog timer value is negative."]
133    #[inline(always)]
134    pub fn wdog_val_neg(
135        self,
136    ) -> crate::common::RegisterFieldBool<13, 1, 0, WatchdogReg_SPEC, crate::common::RW> {
137        crate::common::RegisterFieldBool::<13,1,0,WatchdogReg_SPEC,crate::common::RW>::from_register(self,0)
138    }
139
140    #[doc = "Write: Watchdog timer reload value. Note that all bits \\[31-14\\] must be 0 to reload this register.\nRead: Actual Watchdog timer value. Decremented by 1 every ~10 msec (RC32K) or ~29 msec(RCX).\nBit 13 indicates a negative counter value. 2, 1, 0, 3FFF16, 3FFE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions:\nIf WATCHDOG_CTRL_REG\\[NMI_RST\\] = 0 then\n  If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt)\n  if WDOG_VAL =3FF016 -> WDOG reset -> reload 1FFF16\nIf WATCHDOG_CTRL_REG\\[NMI_RST\\] = 1 then\n  if WDOG_VAL <= 0 -> WDOG reset -> reload 1FFF16\nNote 1: The programmed value WDOG_VAL is updated in the (independent) Watchdog timer at the 2nd next RC32K or RCX clock tick.\nNote 2: Select RC32K or RCX with CLK_RCX_REG\\[RCX_ENABLE\\]. The RC32K is selected by default."]
141    #[inline(always)]
142    pub fn wdog_val(
143        self,
144    ) -> crate::common::RegisterField<0, 0x1fff, 1, 0, u16, u16, WatchdogReg_SPEC, crate::common::RW>
145    {
146        crate::common::RegisterField::<0,0x1fff,1,0,u16,u16,WatchdogReg_SPEC,crate::common::RW>::from_register(self,0)
147    }
148}
149impl ::core::default::Default for WatchdogReg {
150    #[inline(always)]
151    fn default() -> WatchdogReg {
152        <crate::RegValueT<WatchdogReg_SPEC> as RegisterValue<_>>::new(8191)
153    }
154}
da14697_pac/sys_wdog.rs

da14697_pac/
sys_wdog.rs
