da14697_pac/
memctrl.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:38 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"MEMCTRL registers"]
28unsafe impl ::core::marker::Send for super::Memctrl {}
29unsafe impl ::core::marker::Sync for super::Memctrl {}
30impl super::Memctrl {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "BSR Reset Register"]
38    #[inline(always)]
39    pub const fn busy_reset_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::BusyResetReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::BusyResetReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(120usize),
45            )
46        }
47    }
48
49    #[doc = "BSR Set Register"]
50    #[inline(always)]
51    pub const fn busy_set_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::BusySetReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::BusySetReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(116usize),
57            )
58        }
59    }
60
61    #[doc = "BSR Status Register"]
62    #[inline(always)]
63    pub const fn busy_stat_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::BusyStatReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::BusyStatReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(124usize),
69            )
70        }
71    }
72
73    #[doc = "CMAC code Base Address Register"]
74    #[inline(always)]
75    pub const fn cmi_code_base_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::CmiCodeBaseReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::CmiCodeBaseReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(32usize),
81            )
82        }
83    }
84
85    #[doc = "CMAC data Base Address Register"]
86    #[inline(always)]
87    pub const fn cmi_data_base_reg(
88        &self,
89    ) -> &'static crate::common::Reg<self::CmiDataBaseReg_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::CmiDataBaseReg_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(36usize),
93            )
94        }
95    }
96
97    #[doc = "CMAC end Address Register"]
98    #[inline(always)]
99    pub const fn cmi_end_reg(
100        &self,
101    ) -> &'static crate::common::Reg<self::CmiEndReg_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::CmiEndReg_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(44usize),
105            )
106        }
107    }
108
109    #[doc = "CMAC shared data Base Address Register"]
110    #[inline(always)]
111    pub const fn cmi_shared_base_reg(
112        &self,
113    ) -> &'static crate::common::Reg<self::CmiSharedBaseReg_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::CmiSharedBaseReg_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(40usize),
117            )
118        }
119    }
120
121    #[doc = "Priority Control Register"]
122    #[inline(always)]
123    pub const fn mem_prio_reg(
124        &self,
125    ) -> &'static crate::common::Reg<self::MemPrioReg_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::MemPrioReg_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(4usize),
129            )
130        }
131    }
132
133    #[doc = "Maximum Stall cycles Control Register"]
134    #[inline(always)]
135    pub const fn mem_stall_reg(
136        &self,
137    ) -> &'static crate::common::Reg<self::MemStallReg_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::MemStallReg_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(8usize),
141            )
142        }
143    }
144
145    #[doc = "RAM cells Status Register"]
146    #[inline(always)]
147    pub const fn mem_status2_reg(
148        &self,
149    ) -> &'static crate::common::Reg<self::MemStatus2Reg_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::MemStatus2Reg_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(16usize),
153            )
154        }
155    }
156
157    #[doc = "Memory Arbiter Status Register"]
158    #[inline(always)]
159    pub const fn mem_status_reg(
160        &self,
161    ) -> &'static crate::common::Reg<self::MemStatusReg_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::MemStatusReg_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(12usize),
165            )
166        }
167    }
168
169    #[doc = "Sensor Node Controller Base Address Register"]
170    #[inline(always)]
171    pub const fn snc_base_reg(
172        &self,
173    ) -> &'static crate::common::Reg<self::SncBaseReg_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::SncBaseReg_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(48usize),
177            )
178        }
179    }
180}
181#[doc(hidden)]
182#[derive(Copy, Clone, Eq, PartialEq)]
183pub struct BusyResetReg_SPEC;
184impl crate::sealed::RegSpec for BusyResetReg_SPEC {
185    type DataType = u32;
186}
187
188#[doc = "BSR Reset Register"]
189pub type BusyResetReg = crate::RegValueT<BusyResetReg_SPEC>;
190
191impl BusyResetReg {
192    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
193    #[inline(always)]
194    pub fn busy_spare(
195        self,
196    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
197    {
198        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
199    }
200
201    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
202    #[inline(always)]
203    pub fn busy_motor(
204        self,
205    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
206    {
207        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
208    }
209
210    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
211    #[inline(always)]
212    pub fn busy_timer2(
213        self,
214    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
215    {
216        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
217    }
218
219    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
220    #[inline(always)]
221    pub fn busy_timer(
222        self,
223    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
224    {
225        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
226    }
227
228    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
229    #[inline(always)]
230    pub fn busy_uart3(
231        self,
232    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
233    {
234        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
235    }
236
237    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
238    #[inline(always)]
239    pub fn busy_gpadc(
240        self,
241    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
242    {
243        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
244    }
245
246    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
247    #[inline(always)]
248    pub fn busy_pdm(
249        self,
250    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
251    {
252        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
253    }
254
255    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
256    #[inline(always)]
257    pub fn busy_src(
258        self,
259    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
260    {
261        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
262    }
263
264    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
265    #[inline(always)]
266    pub fn busy_pcm(
267        self,
268    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
269    {
270        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
271    }
272
273    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
274    #[inline(always)]
275    pub fn busy_sdadc(
276        self,
277    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
278    {
279        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
280    }
281
282    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
283    #[inline(always)]
284    pub fn busy_i2c2(
285        self,
286    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
287    {
288        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
289    }
290
291    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
292    #[inline(always)]
293    pub fn busy_i2c(
294        self,
295    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
296    {
297        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
298    }
299
300    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
301    #[inline(always)]
302    pub fn busy_spi2(
303        self,
304    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
305    {
306        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
307    }
308
309    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
310    #[inline(always)]
311    pub fn busy_spi(
312        self,
313    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
314    {
315        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
316    }
317
318    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
319    #[inline(always)]
320    pub fn busy_uart2(
321        self,
322    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
323    {
324        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
325    }
326
327    #[doc = "Clear the BUSY bitfield, by writing the master code which has claimed to this field\nReading returns 0 to allow read/modify/write to the register."]
328    #[inline(always)]
329    pub fn busy_uart(
330        self,
331    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyResetReg_SPEC, crate::common::RW>
332    {
333        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyResetReg_SPEC,crate::common::RW>::from_register(self,0)
334    }
335}
336impl ::core::default::Default for BusyResetReg {
337    #[inline(always)]
338    fn default() -> BusyResetReg {
339        <crate::RegValueT<BusyResetReg_SPEC> as RegisterValue<_>>::new(0)
340    }
341}
342
343#[doc(hidden)]
344#[derive(Copy, Clone, Eq, PartialEq)]
345pub struct BusySetReg_SPEC;
346impl crate::sealed::RegSpec for BusySetReg_SPEC {
347    type DataType = u32;
348}
349
350#[doc = "BSR Set Register"]
351pub type BusySetReg = crate::RegValueT<BusySetReg_SPEC>;
352
353impl BusySetReg {
354    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
355    #[inline(always)]
356    pub fn busy_spare(
357        self,
358    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
359    {
360        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
361    }
362
363    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
364    #[inline(always)]
365    pub fn busy_motor(
366        self,
367    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
368    {
369        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
370    }
371
372    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
373    #[inline(always)]
374    pub fn busy_timer2(
375        self,
376    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
377    {
378        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
379    }
380
381    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
382    #[inline(always)]
383    pub fn busy_timer(
384        self,
385    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
386    {
387        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
388    }
389
390    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
391    #[inline(always)]
392    pub fn busy_uart3(
393        self,
394    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
395    {
396        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
397    }
398
399    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
400    #[inline(always)]
401    pub fn busy_gpadc(
402        self,
403    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
404    {
405        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
406    }
407
408    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
409    #[inline(always)]
410    pub fn busy_pdm(
411        self,
412    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
413    {
414        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
415    }
416
417    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
418    #[inline(always)]
419    pub fn busy_src(
420        self,
421    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
422    {
423        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
424    }
425
426    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
427    #[inline(always)]
428    pub fn busy_pcm(
429        self,
430    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
431    {
432        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
433    }
434
435    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
436    #[inline(always)]
437    pub fn busy_sdadc(
438        self,
439    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
440    {
441        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
442    }
443
444    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
445    #[inline(always)]
446    pub fn busy_i2c2(
447        self,
448    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
449    {
450        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
451    }
452
453    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
454    #[inline(always)]
455    pub fn busy_i2c(
456        self,
457    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
458    {
459        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
460    }
461
462    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
463    #[inline(always)]
464    pub fn busy_spi2(
465        self,
466    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
467    {
468        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
469    }
470
471    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
472    #[inline(always)]
473    pub fn busy_spi(
474        self,
475    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
476    {
477        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
478    }
479
480    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
481    #[inline(always)]
482    pub fn busy_uart2(
483        self,
484    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
485    {
486        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
487    }
488
489    #[doc = "Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0).\nReading returns 0 to allow read/modify/write to the register."]
490    #[inline(always)]
491    pub fn busy_uart(
492        self,
493    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusySetReg_SPEC, crate::common::RW>
494    {
495        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusySetReg_SPEC,crate::common::RW>::from_register(self,0)
496    }
497}
498impl ::core::default::Default for BusySetReg {
499    #[inline(always)]
500    fn default() -> BusySetReg {
501        <crate::RegValueT<BusySetReg_SPEC> as RegisterValue<_>>::new(0)
502    }
503}
504
505#[doc(hidden)]
506#[derive(Copy, Clone, Eq, PartialEq)]
507pub struct BusyStatReg_SPEC;
508impl crate::sealed::RegSpec for BusyStatReg_SPEC {
509    type DataType = u32;
510}
511
512#[doc = "BSR Status Register"]
513pub type BusyStatReg = crate::RegValueT<BusyStatReg_SPEC>;
514
515impl BusyStatReg {
516    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
517    #[inline(always)]
518    pub fn busy_spare(
519        self,
520    ) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
521    {
522        crate::common::RegisterField::<30,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
523    }
524
525    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
526    #[inline(always)]
527    pub fn busy_motor(
528        self,
529    ) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
530    {
531        crate::common::RegisterField::<28,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
532    }
533
534    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
535    #[inline(always)]
536    pub fn busy_timer2(
537        self,
538    ) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
539    {
540        crate::common::RegisterField::<26,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
541    }
542
543    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
544    #[inline(always)]
545    pub fn busy_timer(
546        self,
547    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
548    {
549        crate::common::RegisterField::<24,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
550    }
551
552    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
553    #[inline(always)]
554    pub fn busy_uart3(
555        self,
556    ) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
557    {
558        crate::common::RegisterField::<22,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
559    }
560
561    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
562    #[inline(always)]
563    pub fn busy_gpadc(
564        self,
565    ) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
566    {
567        crate::common::RegisterField::<20,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
568    }
569
570    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
571    #[inline(always)]
572    pub fn busy_pdm(
573        self,
574    ) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
575    {
576        crate::common::RegisterField::<18,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
577    }
578
579    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
580    #[inline(always)]
581    pub fn busy_src(
582        self,
583    ) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
584    {
585        crate::common::RegisterField::<16,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
586    }
587
588    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
589    #[inline(always)]
590    pub fn busy_pcm(
591        self,
592    ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
593    {
594        crate::common::RegisterField::<14,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
595    }
596
597    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
598    #[inline(always)]
599    pub fn busy_sdadc(
600        self,
601    ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
602    {
603        crate::common::RegisterField::<12,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
604    }
605
606    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
607    #[inline(always)]
608    pub fn busy_i2c2(
609        self,
610    ) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
611    {
612        crate::common::RegisterField::<10,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
613    }
614
615    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
616    #[inline(always)]
617    pub fn busy_i2c(
618        self,
619    ) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
620    {
621        crate::common::RegisterField::<8,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
622    }
623
624    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
625    #[inline(always)]
626    pub fn busy_spi2(
627        self,
628    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
629    {
630        crate::common::RegisterField::<6,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
631    }
632
633    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
634    #[inline(always)]
635    pub fn busy_spi(
636        self,
637    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
638    {
639        crate::common::RegisterField::<4,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
640    }
641
642    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
643    #[inline(always)]
644    pub fn busy_uart2(
645        self,
646    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
647    {
648        crate::common::RegisterField::<2,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
649    }
650
651    #[doc = "A non-zero value indicates the resource is busy. The value represents which master is using it."]
652    #[inline(always)]
653    pub fn busy_uart(
654        self,
655    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BusyStatReg_SPEC, crate::common::R>
656    {
657        crate::common::RegisterField::<0,0x3,1,0,u8,u8,BusyStatReg_SPEC,crate::common::R>::from_register(self,0)
658    }
659}
660impl ::core::default::Default for BusyStatReg {
661    #[inline(always)]
662    fn default() -> BusyStatReg {
663        <crate::RegValueT<BusyStatReg_SPEC> as RegisterValue<_>>::new(0)
664    }
665}
666
667#[doc(hidden)]
668#[derive(Copy, Clone, Eq, PartialEq)]
669pub struct CmiCodeBaseReg_SPEC;
670impl crate::sealed::RegSpec for CmiCodeBaseReg_SPEC {
671    type DataType = u32;
672}
673
674#[doc = "CMAC code Base Address Register"]
675pub type CmiCodeBaseReg = crate::RegValueT<CmiCodeBaseReg_SPEC>;
676
677impl CmiCodeBaseReg {
678    #[doc = "Base address for CMAC code with steps of 1 kB.\n0x001: 1 kB base address\n0x010: 16 kB base address\n0x100: 256 kB base address"]
679    #[inline(always)]
680    pub fn cmi_code_base_addr(
681        self,
682    ) -> crate::common::RegisterField<
683        10,
684        0x1ff,
685        1,
686        0,
687        u16,
688        u16,
689        CmiCodeBaseReg_SPEC,
690        crate::common::RW,
691    > {
692        crate::common::RegisterField::<
693            10,
694            0x1ff,
695            1,
696            0,
697            u16,
698            u16,
699            CmiCodeBaseReg_SPEC,
700            crate::common::RW,
701        >::from_register(self, 0)
702    }
703}
704impl ::core::default::Default for CmiCodeBaseReg {
705    #[inline(always)]
706    fn default() -> CmiCodeBaseReg {
707        <crate::RegValueT<CmiCodeBaseReg_SPEC> as RegisterValue<_>>::new(0)
708    }
709}
710
711#[doc(hidden)]
712#[derive(Copy, Clone, Eq, PartialEq)]
713pub struct CmiDataBaseReg_SPEC;
714impl crate::sealed::RegSpec for CmiDataBaseReg_SPEC {
715    type DataType = u32;
716}
717
718#[doc = "CMAC data Base Address Register"]
719pub type CmiDataBaseReg = crate::RegValueT<CmiDataBaseReg_SPEC>;
720
721impl CmiDataBaseReg {
722    #[doc = "Base address for CMAC data with steps of 4 bytes.\n0x00001: 4 byte base address\n0x00010: 64 byte base address\n0x00100: 1 kB base address\n0x01000: 16 kB base address\n0x10000: 256 kB base address"]
723    #[inline(always)]
724    pub fn cmi_data_base_addr(
725        self,
726    ) -> crate::common::RegisterField<
727        2,
728        0x1ffff,
729        1,
730        0,
731        u32,
732        u32,
733        CmiDataBaseReg_SPEC,
734        crate::common::RW,
735    > {
736        crate::common::RegisterField::<
737            2,
738            0x1ffff,
739            1,
740            0,
741            u32,
742            u32,
743            CmiDataBaseReg_SPEC,
744            crate::common::RW,
745        >::from_register(self, 0)
746    }
747}
748impl ::core::default::Default for CmiDataBaseReg {
749    #[inline(always)]
750    fn default() -> CmiDataBaseReg {
751        <crate::RegValueT<CmiDataBaseReg_SPEC> as RegisterValue<_>>::new(0)
752    }
753}
754
755#[doc(hidden)]
756#[derive(Copy, Clone, Eq, PartialEq)]
757pub struct CmiEndReg_SPEC;
758impl crate::sealed::RegSpec for CmiEndReg_SPEC {
759    type DataType = u32;
760}
761
762#[doc = "CMAC end Address Register"]
763pub type CmiEndReg = crate::RegValueT<CmiEndReg_SPEC>;
764
765impl CmiEndReg {
766    #[doc = "End address for CMAC code and data accesses with steps of 1 kB.\n0x000: accesses up to 1kB are allowed\n0x001: accesses up to 2kB are allowed\n0x01F: accesses up to 32kB are allowed\n0x1FF: accesses up to 512kB are allowed"]
767    #[inline(always)]
768    pub fn cmi_end_addr(
769        self,
770    ) -> crate::common::RegisterField<10, 0x1ff, 1, 0, u16, u16, CmiEndReg_SPEC, crate::common::RW>
771    {
772        crate::common::RegisterField::<10,0x1ff,1,0,u16,u16,CmiEndReg_SPEC,crate::common::RW>::from_register(self,0)
773    }
774}
775impl ::core::default::Default for CmiEndReg {
776    #[inline(always)]
777    fn default() -> CmiEndReg {
778        <crate::RegValueT<CmiEndReg_SPEC> as RegisterValue<_>>::new(524287)
779    }
780}
781
782#[doc(hidden)]
783#[derive(Copy, Clone, Eq, PartialEq)]
784pub struct CmiSharedBaseReg_SPEC;
785impl crate::sealed::RegSpec for CmiSharedBaseReg_SPEC {
786    type DataType = u32;
787}
788
789#[doc = "CMAC shared data Base Address Register"]
790pub type CmiSharedBaseReg = crate::RegValueT<CmiSharedBaseReg_SPEC>;
791
792impl CmiSharedBaseReg {
793    #[doc = "Base address for CMAC shared data with steps of 1 kB.\n0x001: 1 kB base address\n0x010: 16 kB base address\n0x100: 256 kB base address"]
794    #[inline(always)]
795    pub fn cmi_shared_base_addr(
796        self,
797    ) -> crate::common::RegisterField<
798        10,
799        0x1ff,
800        1,
801        0,
802        u16,
803        u16,
804        CmiSharedBaseReg_SPEC,
805        crate::common::RW,
806    > {
807        crate::common::RegisterField::<
808            10,
809            0x1ff,
810            1,
811            0,
812            u16,
813            u16,
814            CmiSharedBaseReg_SPEC,
815            crate::common::RW,
816        >::from_register(self, 0)
817    }
818}
819impl ::core::default::Default for CmiSharedBaseReg {
820    #[inline(always)]
821    fn default() -> CmiSharedBaseReg {
822        <crate::RegValueT<CmiSharedBaseReg_SPEC> as RegisterValue<_>>::new(0)
823    }
824}
825
826#[doc(hidden)]
827#[derive(Copy, Clone, Eq, PartialEq)]
828pub struct MemPrioReg_SPEC;
829impl crate::sealed::RegSpec for MemPrioReg_SPEC {
830    type DataType = u32;
831}
832
833#[doc = "Priority Control Register"]
834pub type MemPrioReg = crate::RegValueT<MemPrioReg_SPEC>;
835
836impl MemPrioReg {
837    #[doc = "Priority for the AHB interface.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
838    #[inline(always)]
839    pub fn ahb_prio(
840        self,
841    ) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, MemPrioReg_SPEC, crate::common::RW>
842    {
843        crate::common::RegisterField::<4,0x3,1,0,u8,u8,MemPrioReg_SPEC,crate::common::RW>::from_register(self,0)
844    }
845
846    #[doc = "Priority for the AHB2 interface.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
847    #[inline(always)]
848    pub fn ahb2_prio(
849        self,
850    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, MemPrioReg_SPEC, crate::common::RW>
851    {
852        crate::common::RegisterField::<2,0x3,1,0,u8,u8,MemPrioReg_SPEC,crate::common::RW>::from_register(self,0)
853    }
854
855    #[doc = "Priority for the SNC interface.\n00: low priority (default)\n01: mid priority\n1x: high priority"]
856    #[inline(always)]
857    pub fn snc_prio(
858        self,
859    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, MemPrioReg_SPEC, crate::common::RW>
860    {
861        crate::common::RegisterField::<0,0x3,1,0,u8,u8,MemPrioReg_SPEC,crate::common::RW>::from_register(self,0)
862    }
863}
864impl ::core::default::Default for MemPrioReg {
865    #[inline(always)]
866    fn default() -> MemPrioReg {
867        <crate::RegValueT<MemPrioReg_SPEC> as RegisterValue<_>>::new(0)
868    }
869}
870
871#[doc(hidden)]
872#[derive(Copy, Clone, Eq, PartialEq)]
873pub struct MemStallReg_SPEC;
874impl crate::sealed::RegSpec for MemStallReg_SPEC {
875    type DataType = u32;
876}
877
878#[doc = "Maximum Stall cycles Control Register"]
879pub type MemStallReg = crate::RegValueT<MemStallReg_SPEC>;
880
881impl MemStallReg {
882    #[doc = "Maximum allowed number of stall cycles for the AHB interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
883    #[inline(always)]
884    pub fn ahb_max_stall(
885        self,
886    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
887    {
888        crate::common::RegisterField::<8,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
889    }
890
891    #[doc = "Maximum allowed number of stall cycles for the AHB2 interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
892    #[inline(always)]
893    pub fn ahb2_max_stall(
894        self,
895    ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
896    {
897        crate::common::RegisterField::<4,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
898    }
899
900    #[doc = "Maximum allowed number of stall cycles for the SNC interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles.\n0: don\'t use, not feasible and can block other interfaces\n1: max 1 stall cycle\n15: max 15 stall cycles"]
901    #[inline(always)]
902    pub fn snc_max_stall(
903        self,
904    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, MemStallReg_SPEC, crate::common::RW>
905    {
906        crate::common::RegisterField::<0,0xf,1,0,u8,u8,MemStallReg_SPEC,crate::common::RW>::from_register(self,0)
907    }
908}
909impl ::core::default::Default for MemStallReg {
910    #[inline(always)]
911    fn default() -> MemStallReg {
912        <crate::RegValueT<MemStallReg_SPEC> as RegisterValue<_>>::new(4095)
913    }
914}
915
916#[doc(hidden)]
917#[derive(Copy, Clone, Eq, PartialEq)]
918pub struct MemStatus2Reg_SPEC;
919impl crate::sealed::RegSpec for MemStatus2Reg_SPEC {
920    type DataType = u32;
921}
922
923#[doc = "RAM cells Status Register"]
924pub type MemStatus2Reg = crate::RegValueT<MemStatus2Reg_SPEC>;
925
926impl MemStatus2Reg {
927    #[doc = "Reading a \'1\' indicates RAM8 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
928    #[inline(always)]
929    pub fn ram8_off_but_access(
930        self,
931    ) -> crate::common::RegisterFieldBool<7, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
932        crate::common::RegisterFieldBool::<7,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
933    }
934
935    #[doc = "Reading a \'1\' indicates RAM7 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
936    #[inline(always)]
937    pub fn ram7_off_but_access(
938        self,
939    ) -> crate::common::RegisterFieldBool<6, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
940        crate::common::RegisterFieldBool::<6,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
941    }
942
943    #[doc = "Reading a \'1\' indicates RAM6 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
944    #[inline(always)]
945    pub fn ram6_off_but_access(
946        self,
947    ) -> crate::common::RegisterFieldBool<5, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
948        crate::common::RegisterFieldBool::<5,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
949    }
950
951    #[doc = "Reading a \'1\' indicates RAM5 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
952    #[inline(always)]
953    pub fn ram5_off_but_access(
954        self,
955    ) -> crate::common::RegisterFieldBool<4, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
956        crate::common::RegisterFieldBool::<4,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
957    }
958
959    #[doc = "Reading a \'1\' indicates RAM4 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
960    #[inline(always)]
961    pub fn ram4_off_but_access(
962        self,
963    ) -> crate::common::RegisterFieldBool<3, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
964        crate::common::RegisterFieldBool::<3,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
965    }
966
967    #[doc = "Reading a \'1\' indicates RAM3 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
968    #[inline(always)]
969    pub fn ram3_off_but_access(
970        self,
971    ) -> crate::common::RegisterFieldBool<2, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
972        crate::common::RegisterFieldBool::<2,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
973    }
974
975    #[doc = "Reading a \'1\' indicates RAM2 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
976    #[inline(always)]
977    pub fn ram2_off_but_access(
978        self,
979    ) -> crate::common::RegisterFieldBool<1, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
980        crate::common::RegisterFieldBool::<1,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
981    }
982
983    #[doc = "Reading a \'1\' indicates RAM1 was off but still access was performed.\nWriting a \'1\' will clear the status back to \'0\'."]
984    #[inline(always)]
985    pub fn ram1_off_but_access(
986        self,
987    ) -> crate::common::RegisterFieldBool<0, 1, 0, MemStatus2Reg_SPEC, crate::common::RW> {
988        crate::common::RegisterFieldBool::<0,1,0,MemStatus2Reg_SPEC,crate::common::RW>::from_register(self,0)
989    }
990}
991impl ::core::default::Default for MemStatus2Reg {
992    #[inline(always)]
993    fn default() -> MemStatus2Reg {
994        <crate::RegValueT<MemStatus2Reg_SPEC> as RegisterValue<_>>::new(0)
995    }
996}
997
998#[doc(hidden)]
999#[derive(Copy, Clone, Eq, PartialEq)]
1000pub struct MemStatusReg_SPEC;
1001impl crate::sealed::RegSpec for MemStatusReg_SPEC {
1002    type DataType = u32;
1003}
1004
1005#[doc = "Memory Arbiter Status Register"]
1006pub type MemStatusReg = crate::RegValueT<MemStatusReg_SPEC>;
1007
1008impl MemStatusReg {
1009    #[doc = "Writing a \'1\' clears CMI_NOT_READY bit."]
1010    #[inline(always)]
1011    pub fn cmi_clear_ready(
1012        self,
1013    ) -> crate::common::RegisterFieldBool<13, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1014        crate::common::RegisterFieldBool::<13,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1015    }
1016
1017    #[doc = "0: Normal operation\n1: CMI access performed which couldn\'t be handled right away (interface doesn\'t allow wait cycles)"]
1018    #[inline(always)]
1019    pub fn cmi_not_ready(
1020        self,
1021    ) -> crate::common::RegisterFieldBool<12, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1022        crate::common::RegisterFieldBool::<12,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1023    }
1024
1025    #[doc = "The maximum number of arbiter clock cycles that an AHB2 access has been buffered."]
1026    #[inline(always)]
1027    pub fn ahb2_wr_buff_cnt(
1028        self,
1029    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1030    {
1031        crate::common::RegisterField::<8,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1032    }
1033
1034    #[doc = "The maximum number of arbiter clock cycles that an AHB access has been buffered."]
1035    #[inline(always)]
1036    pub fn ahb_wr_buff_cnt(
1037        self,
1038    ) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, MemStatusReg_SPEC, crate::common::R>
1039    {
1040        crate::common::RegisterField::<4,0xf,1,0,u8,u8,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1041    }
1042
1043    #[doc = "Writing a \'1\' clears AHB2_WR_BUFF_CNT."]
1044    #[inline(always)]
1045    pub fn ahb2_clr_wr_buff(
1046        self,
1047    ) -> crate::common::RegisterFieldBool<3, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1048        crate::common::RegisterFieldBool::<3,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1049    }
1050
1051    #[doc = "Writing a \'1\' clears AHB_WR_BUFF_CNT."]
1052    #[inline(always)]
1053    pub fn ahb_clr_wr_buff(
1054        self,
1055    ) -> crate::common::RegisterFieldBool<2, 1, 0, MemStatusReg_SPEC, crate::common::W> {
1056        crate::common::RegisterFieldBool::<2,1,0,MemStatusReg_SPEC,crate::common::W>::from_register(self,0)
1057    }
1058
1059    #[doc = "0: No AHB2 write access is buffered.\n1: Currently a single AHB2 write access is buffered in the arbiter."]
1060    #[inline(always)]
1061    pub fn ahb2_write_buff(
1062        self,
1063    ) -> crate::common::RegisterFieldBool<1, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1064        crate::common::RegisterFieldBool::<1,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1065    }
1066
1067    #[doc = "0: No AHB write access is buffered.\n1: Currently a single AHB write access is buffered in the arbiter."]
1068    #[inline(always)]
1069    pub fn ahb_write_buff(
1070        self,
1071    ) -> crate::common::RegisterFieldBool<0, 1, 0, MemStatusReg_SPEC, crate::common::R> {
1072        crate::common::RegisterFieldBool::<0,1,0,MemStatusReg_SPEC,crate::common::R>::from_register(self,0)
1073    }
1074}
1075impl ::core::default::Default for MemStatusReg {
1076    #[inline(always)]
1077    fn default() -> MemStatusReg {
1078        <crate::RegValueT<MemStatusReg_SPEC> as RegisterValue<_>>::new(0)
1079    }
1080}
1081
1082#[doc(hidden)]
1083#[derive(Copy, Clone, Eq, PartialEq)]
1084pub struct SncBaseReg_SPEC;
1085impl crate::sealed::RegSpec for SncBaseReg_SPEC {
1086    type DataType = u32;
1087}
1088
1089#[doc = "Sensor Node Controller Base Address Register"]
1090pub type SncBaseReg = crate::RegValueT<SncBaseReg_SPEC>;
1091
1092impl SncBaseReg {
1093    #[doc = "Base address for SNC interface with steps of 4 bytes.\n0x00001: 4 byte base address\n0x00010: 64 byte base address\n0x00100: 1 kB base address\n0x01000: 16 kB base address\n0x10000: 256 kB base address"]
1094    #[inline(always)]
1095    pub fn snc_base_address(
1096        self,
1097    ) -> crate::common::RegisterField<2, 0x1ffff, 1, 0, u32, u32, SncBaseReg_SPEC, crate::common::RW>
1098    {
1099        crate::common::RegisterField::<2,0x1ffff,1,0,u32,u32,SncBaseReg_SPEC,crate::common::RW>::from_register(self,0)
1100    }
1101}
1102impl ::core::default::Default for SncBaseReg {
1103    #[inline(always)]
1104    fn default() -> SncBaseReg {
1105        <crate::RegValueT<SncBaseReg_SPEC> as RegisterValue<_>>::new(0)
1106    }
1107}
da14697_pac/memctrl.rs

da14697_pac/
memctrl.rs
