da14682_pac/
spi.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:10 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"SPI registers"]
28unsafe impl ::core::marker::Send for super::Spi {}
29unsafe impl ::core::marker::Sync for super::Spi {}
30impl super::Spi {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "SPI clear interrupt register"]
38    #[inline(always)]
39    pub const fn spi_clear_int_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::SpiClearIntReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::SpiClearIntReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(6usize),
45            )
46        }
47    }
48
49    #[doc = "SPI control register 0"]
50    #[inline(always)]
51    pub const fn spi_ctrl_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::SpiCtrlReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::SpiCtrlReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0usize),
57            )
58        }
59    }
60
61    #[doc = "SPI control register 1"]
62    #[inline(always)]
63    pub const fn spi_ctrl_reg1(
64        &self,
65    ) -> &'static crate::common::Reg<self::SpiCtrlReg1_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::SpiCtrlReg1_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "SPI RX/TX register0"]
74    #[inline(always)]
75    pub const fn spi_rx_tx_reg0(
76        &self,
77    ) -> &'static crate::common::Reg<self::SpiRxTxReg0_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::SpiRxTxReg0_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(2usize),
81            )
82        }
83    }
84
85    #[doc = "SPI RX/TX register1"]
86    #[inline(always)]
87    pub const fn spi_rx_tx_reg1(
88        &self,
89    ) -> &'static crate::common::Reg<self::SpiRxTxReg1_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::SpiRxTxReg1_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(4usize),
93            )
94        }
95    }
96}
97#[doc(hidden)]
98#[derive(Copy, Clone, Eq, PartialEq)]
99pub struct SpiClearIntReg_SPEC;
100impl crate::sealed::RegSpec for SpiClearIntReg_SPEC {
101    type DataType = u16;
102}
103
104#[doc = "SPI clear interrupt register"]
105pub type SpiClearIntReg = crate::RegValueT<SpiClearIntReg_SPEC>;
106
107impl SpiClearIntReg {
108    #[doc = "Writing any value to this register will clear the SPI_CTRL_REG\\[SPI_INT_BIT\\]\nReading returns 0."]
109    #[inline(always)]
110    pub fn spi_clear_int(
111        self,
112    ) -> crate::common::RegisterField<
113        0,
114        0xffff,
115        1,
116        0,
117        u16,
118        u16,
119        SpiClearIntReg_SPEC,
120        crate::common::W,
121    > {
122        crate::common::RegisterField::<
123            0,
124            0xffff,
125            1,
126            0,
127            u16,
128            u16,
129            SpiClearIntReg_SPEC,
130            crate::common::W,
131        >::from_register(self, 0)
132    }
133}
134impl ::core::default::Default for SpiClearIntReg {
135    #[inline(always)]
136    fn default() -> SpiClearIntReg {
137        <crate::RegValueT<SpiClearIntReg_SPEC> as RegisterValue<_>>::new(0)
138    }
139}
140
141#[doc(hidden)]
142#[derive(Copy, Clone, Eq, PartialEq)]
143pub struct SpiCtrlReg_SPEC;
144impl crate::sealed::RegSpec for SpiCtrlReg_SPEC {
145    type DataType = u16;
146}
147
148#[doc = "SPI control register 0"]
149pub type SpiCtrlReg = crate::RegValueT<SpiCtrlReg_SPEC>;
150
151impl SpiCtrlReg {
152    #[doc = "0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don\'t care.\n1 = SPI_EN pin enabled in slave mode."]
153    #[inline(always)]
154    pub fn spi_en_ctrl(
155        self,
156    ) -> crate::common::RegisterFieldBool<15, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
157        crate::common::RegisterFieldBool::<15,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
158    }
159
160    #[doc = "0 = Disable SPI_INT_BIT to ICU\n1 = Enable SPI_INT_BIT to ICU.\nNote that the SPI_INT interrupt is shared with AD_INT interrupt"]
161    #[inline(always)]
162    pub fn spi_mint(
163        self,
164    ) -> crate::common::RegisterFieldBool<14, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
165        crate::common::RegisterFieldBool::<14,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
166    }
167
168    #[doc = "0 = RX Register or FIFO is empty.\n1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG."]
169    #[inline(always)]
170    pub fn spi_int_bit(
171        self,
172    ) -> crate::common::RegisterFieldBool<13, 1, 0, SpiCtrlReg_SPEC, crate::common::R> {
173        crate::common::RegisterFieldBool::<13,1,0,SpiCtrlReg_SPEC,crate::common::R>::from_register(self,0)
174    }
175
176    #[doc = "Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)"]
177    #[inline(always)]
178    pub fn spi_di(
179        self,
180    ) -> crate::common::RegisterFieldBool<12, 1, 0, SpiCtrlReg_SPEC, crate::common::R> {
181        crate::common::RegisterFieldBool::<12,1,0,SpiCtrlReg_SPEC,crate::common::R>::from_register(self,0)
182    }
183
184    #[doc = "0 = TX-FIFO is not full, data can be written.\n1 = TX-FIFO is full, data can not be written."]
185    #[inline(always)]
186    pub fn spi_txh(
187        self,
188    ) -> crate::common::RegisterFieldBool<11, 1, 0, SpiCtrlReg_SPEC, crate::common::R> {
189        crate::common::RegisterFieldBool::<11,1,0,SpiCtrlReg_SPEC,crate::common::R>::from_register(self,0)
190    }
191
192    #[doc = "0 = normal operation\n1 = Force SPIDO output level to value of SPI_DO."]
193    #[inline(always)]
194    pub fn spi_force_do(
195        self,
196    ) -> crate::common::RegisterFieldBool<10, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
197        crate::common::RegisterFieldBool::<10,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
198    }
199
200    #[doc = "0 = normal operation\n1 = Reset SPI. Same function as SPI_ON except that internal clock remain active."]
201    #[inline(always)]
202    pub fn spi_rst(
203        self,
204    ) -> crate::common::RegisterFieldBool<9, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
205        crate::common::RegisterFieldBool::<9,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
206    }
207
208    #[doc = "00 = 8 bits mode, only SPI_RX_TX_REG0 used\n01 = 16 bit mode, only SPI_RX_TX_REG0 used\n10 = 32 bits mode, SPI_RX_TX_REG0 & SPI_RX_TX_REG1 used\n11 = 9 bits mode. Only valid in master mode."]
209    #[inline(always)]
210    pub fn spi_word(
211        self,
212    ) -> crate::common::RegisterField<7, 0x3, 1, 0, u8, u8, SpiCtrlReg_SPEC, crate::common::RW>
213    {
214        crate::common::RegisterField::<7,0x3,1,0,u8,u8,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
215    }
216
217    #[doc = "Master/slave mode\n0 = Master,\n1 = Slave(SPI1 only)"]
218    #[inline(always)]
219    pub fn spi_smn(
220        self,
221    ) -> crate::common::RegisterFieldBool<6, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
222        crate::common::RegisterFieldBool::<6,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
223    }
224
225    #[doc = "Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1"]
226    #[inline(always)]
227    pub fn spi_do(
228        self,
229    ) -> crate::common::RegisterFieldBool<5, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
230        crate::common::RegisterFieldBool::<5,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
231    }
232
233    #[doc = "Select SPI_CLK clock output frequency in master mode:\n00 = SPI_CLK / 8\n01 = SPI_CLK / 4\n10 = SPI_CLK / 2\n11 = SPI_CLK / 14"]
234    #[inline(always)]
235    pub fn spi_clk(
236        self,
237    ) -> crate::common::RegisterField<3, 0x3, 1, 0, u8, u8, SpiCtrlReg_SPEC, crate::common::RW>
238    {
239        crate::common::RegisterField::<3,0x3,1,0,u8,u8,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
240    }
241
242    #[doc = "Select SPI_CLK polarity.\n0 = SPI_CLK is initially low.\n1 = SPI_CLK is initially high."]
243    #[inline(always)]
244    pub fn spi_pol(
245        self,
246    ) -> crate::common::RegisterFieldBool<2, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
247        crate::common::RegisterFieldBool::<2,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
248    }
249
250    #[doc = "Select SPI_CLK phase. See functional timing diagrams in SPI chapter"]
251    #[inline(always)]
252    pub fn spi_pha(
253        self,
254    ) -> crate::common::RegisterFieldBool<1, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
255        crate::common::RegisterFieldBool::<1,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
256    }
257
258    #[doc = "0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG0 and SPI_CTRL_REG1. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty.\n1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!"]
259    #[inline(always)]
260    pub fn spi_on(
261        self,
262    ) -> crate::common::RegisterFieldBool<0, 1, 0, SpiCtrlReg_SPEC, crate::common::RW> {
263        crate::common::RegisterFieldBool::<0,1,0,SpiCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
264    }
265}
266impl ::core::default::Default for SpiCtrlReg {
267    #[inline(always)]
268    fn default() -> SpiCtrlReg {
269        <crate::RegValueT<SpiCtrlReg_SPEC> as RegisterValue<_>>::new(0)
270    }
271}
272
273#[doc(hidden)]
274#[derive(Copy, Clone, Eq, PartialEq)]
275pub struct SpiCtrlReg1_SPEC;
276impl crate::sealed::RegSpec for SpiCtrlReg1_SPEC {
277    type DataType = u16;
278}
279
280#[doc = "SPI control register 1"]
281pub type SpiCtrlReg1 = crate::RegValueT<SpiCtrlReg1_SPEC>;
282
283impl SpiCtrlReg1 {
284    #[doc = "Determines the value of the first bit in 9 bits SPI mode."]
285    #[inline(always)]
286    pub fn spi_9bit_val(
287        self,
288    ) -> crate::common::RegisterFieldBool<4, 1, 0, SpiCtrlReg1_SPEC, crate::common::RW> {
289        crate::common::RegisterFieldBool::<4,1,0,SpiCtrlReg1_SPEC,crate::common::RW>::from_register(self,0)
290    }
291
292    #[doc = "0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPIx_CTRL_REG0\\[SPI_INT_BIT\\] can be used to distinguish between these situations.\n1 = The SPI is busy with a transfer."]
293    #[inline(always)]
294    pub fn spi_busy(
295        self,
296    ) -> crate::common::RegisterFieldBool<3, 1, 0, SpiCtrlReg1_SPEC, crate::common::R> {
297        crate::common::RegisterFieldBool::<3,1,0,SpiCtrlReg1_SPEC,crate::common::R>::from_register(self,0)
298    }
299
300    #[doc = "0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge.\n1 = The SPI has high priority, DMA request signals remain\nactive until the FIFOS are filled/emptied, so the DMA holds the AHB bus."]
301    #[inline(always)]
302    pub fn spi_priority(
303        self,
304    ) -> crate::common::RegisterFieldBool<2, 1, 0, SpiCtrlReg1_SPEC, crate::common::RW> {
305        crate::common::RegisterFieldBool::<2,1,0,SpiCtrlReg1_SPEC,crate::common::RW>::from_register(self,0)
306    }
307
308    #[doc = "0: TX-FIFO and RX-FIFO used (Bidirectional mode).\n1: RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control\n2: TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control\n3: No FIFOs used (backwards compatible mode)"]
309    #[inline(always)]
310    pub fn spi_fifo_mode(
311        self,
312    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, SpiCtrlReg1_SPEC, crate::common::RW>
313    {
314        crate::common::RegisterField::<0,0x3,1,0,u8,u8,SpiCtrlReg1_SPEC,crate::common::RW>::from_register(self,0)
315    }
316}
317impl ::core::default::Default for SpiCtrlReg1 {
318    #[inline(always)]
319    fn default() -> SpiCtrlReg1 {
320        <crate::RegValueT<SpiCtrlReg1_SPEC> as RegisterValue<_>>::new(3)
321    }
322}
323
324#[doc(hidden)]
325#[derive(Copy, Clone, Eq, PartialEq)]
326pub struct SpiRxTxReg0_SPEC;
327impl crate::sealed::RegSpec for SpiRxTxReg0_SPEC {
328    type DataType = u16;
329}
330
331#[doc = "SPI RX/TX register0"]
332pub type SpiRxTxReg0 = crate::RegValueT<SpiRxTxReg0_SPEC>;
333
334impl SpiRxTxReg0 {
335    #[doc = "Write: SPI_TX_REG0 output register 0 (TX-FIFO)\nRead: SPI_RX_REG0 input register 0 (RX-FIFO)\nIn 8 or 9 bits mode bits 15 to 8 are not used, they contain old data."]
336    #[inline(always)]
337    pub fn spi_data0(
338        self,
339    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SpiRxTxReg0_SPEC, crate::common::W>
340    {
341        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,SpiRxTxReg0_SPEC,crate::common::W>::from_register(self,0)
342    }
343}
344impl ::core::default::Default for SpiRxTxReg0 {
345    #[inline(always)]
346    fn default() -> SpiRxTxReg0 {
347        <crate::RegValueT<SpiRxTxReg0_SPEC> as RegisterValue<_>>::new(0)
348    }
349}
350
351#[doc(hidden)]
352#[derive(Copy, Clone, Eq, PartialEq)]
353pub struct SpiRxTxReg1_SPEC;
354impl crate::sealed::RegSpec for SpiRxTxReg1_SPEC {
355    type DataType = u16;
356}
357
358#[doc = "SPI RX/TX register1"]
359pub type SpiRxTxReg1 = crate::RegValueT<SpiRxTxReg1_SPEC>;
360
361impl SpiRxTxReg1 {
362    #[doc = "Write: SPI_TX_REG1 output register 1 (MSB\'s of TX-FIFO)\nRead: SPI_RX_REG1 input register 1 (MSB\'s of RX-FIFO)\nIn 8 or 9 or 16 bits mode bits this register is not used."]
363    #[inline(always)]
364    pub fn spi_data1(
365        self,
366    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SpiRxTxReg1_SPEC, crate::common::W>
367    {
368        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,SpiRxTxReg1_SPEC,crate::common::W>::from_register(self,0)
369    }
370}
371impl ::core::default::Default for SpiRxTxReg1 {
372    #[inline(always)]
373    fn default() -> SpiRxTxReg1 {
374        <crate::RegValueT<SpiRxTxReg1_SPEC> as RegisterValue<_>>::new(0)
375    }
376}
da14682_pac/spi.rs

da14682_pac/
spi.rs
