1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"OTPC registers"]
28unsafe impl ::core::marker::Send for super::Otpc {}
29unsafe impl ::core::marker::Sync for super::Otpc {}
30impl super::Otpc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "AHB master start address"]
38 #[inline(always)]
39 pub const fn otpc_ahbadr_reg(
40 &self,
41 ) -> &'static crate::common::Reg<self::OtpcAhbadrReg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::OtpcAhbadrReg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(12usize),
45 )
46 }
47 }
48
49 #[doc = "Macrocell start address"]
50 #[inline(always)]
51 pub const fn otpc_celadr_reg(
52 &self,
53 ) -> &'static crate::common::Reg<self::OtpcCeladrReg_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::OtpcCeladrReg_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(16usize),
57 )
58 }
59 }
60
61 #[doc = "Ports access to fifo logic"]
62 #[inline(always)]
63 pub const fn otpc_ffprt_reg(
64 &self,
65 ) -> &'static crate::common::Reg<self::OtpcFfprtReg_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::OtpcFfprtReg_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(24usize),
69 )
70 }
71 }
72
73 #[doc = "The data which have taken with the latest read from the OTPC_FFPRT_REG"]
74 #[inline(always)]
75 pub const fn otpc_ffrd_reg(
76 &self,
77 ) -> &'static crate::common::Reg<self::OtpcFfrdReg_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::OtpcFfrdReg_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(28usize),
81 )
82 }
83 }
84
85 #[doc = "Mode register"]
86 #[inline(always)]
87 pub const fn otpc_mode_reg(
88 &self,
89 ) -> &'static crate::common::Reg<self::OtpcModeReg_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::OtpcModeReg_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(0usize),
93 )
94 }
95 }
96
97 #[doc = "Number of words"]
98 #[inline(always)]
99 pub const fn otpc_nwords_reg(
100 &self,
101 ) -> &'static crate::common::Reg<self::OtpcNwordsReg_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::OtpcNwordsReg_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(20usize),
105 )
106 }
107 }
108
109 #[doc = "Bit-programming control register"]
110 #[inline(always)]
111 pub const fn otpc_pctrl_reg(
112 &self,
113 ) -> &'static crate::common::Reg<self::OtpcPctrlReg_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::OtpcPctrlReg_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(4usize),
117 )
118 }
119 }
120
121 #[doc = "The 32 higher bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
122 #[inline(always)]
123 pub const fn otpc_pwordh_reg(
124 &self,
125 ) -> &'static crate::common::Reg<self::OtpcPwordhReg_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::OtpcPwordhReg_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(36usize),
129 )
130 }
131 }
132
133 #[doc = "The 32 lower bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
134 #[inline(always)]
135 pub const fn otpc_pwordl_reg(
136 &self,
137 ) -> &'static crate::common::Reg<self::OtpcPwordlReg_SPEC, crate::common::RW> {
138 unsafe {
139 crate::common::Reg::<self::OtpcPwordlReg_SPEC, crate::common::RW>::from_ptr(
140 self._svd2pac_as_ptr().add(32usize),
141 )
142 }
143 }
144
145 #[doc = "Status register"]
146 #[inline(always)]
147 pub const fn otpc_stat_reg(
148 &self,
149 ) -> &'static crate::common::Reg<self::OtpcStatReg_SPEC, crate::common::RW> {
150 unsafe {
151 crate::common::Reg::<self::OtpcStatReg_SPEC, crate::common::RW>::from_ptr(
152 self._svd2pac_as_ptr().add(8usize),
153 )
154 }
155 }
156
157 #[doc = "Various timing parameters of the OTP cell."]
158 #[inline(always)]
159 pub const fn otpc_tim1_reg(
160 &self,
161 ) -> &'static crate::common::Reg<self::OtpcTim1Reg_SPEC, crate::common::RW> {
162 unsafe {
163 crate::common::Reg::<self::OtpcTim1Reg_SPEC, crate::common::RW>::from_ptr(
164 self._svd2pac_as_ptr().add(40usize),
165 )
166 }
167 }
168
169 #[doc = "Various timing parameters of the OTP cell."]
170 #[inline(always)]
171 pub const fn otpc_tim2_reg(
172 &self,
173 ) -> &'static crate::common::Reg<self::OtpcTim2Reg_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::OtpcTim2Reg_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(44usize),
177 )
178 }
179 }
180}
181#[doc(hidden)]
182#[derive(Copy, Clone, Eq, PartialEq)]
183pub struct OtpcAhbadrReg_SPEC;
184impl crate::sealed::RegSpec for OtpcAhbadrReg_SPEC {
185 type DataType = u32;
186}
187
188#[doc = "AHB master start address"]
189pub type OtpcAhbadrReg = crate::RegValueT<OtpcAhbadrReg_SPEC>;
190
191impl OtpcAhbadrReg {
192 #[doc = "It is the AHB address used by the AHB master interface of the controller (the bits \\[31:2\\]). The bits \\[1:0\\] of the address are considered always as equal to zero.\nThe value of the register remains unchanged, by the internal logic of the controller."]
193 #[inline(always)]
194 pub fn otpc_ahbadr(
195 self,
196 ) -> crate::common::RegisterField<
197 2,
198 0x3fffffff,
199 1,
200 0,
201 u32,
202 u32,
203 OtpcAhbadrReg_SPEC,
204 crate::common::RW,
205 > {
206 crate::common::RegisterField::<
207 2,
208 0x3fffffff,
209 1,
210 0,
211 u32,
212 u32,
213 OtpcAhbadrReg_SPEC,
214 crate::common::RW,
215 >::from_register(self, 0)
216 }
217}
218impl ::core::default::Default for OtpcAhbadrReg {
219 #[inline(always)]
220 fn default() -> OtpcAhbadrReg {
221 <crate::RegValueT<OtpcAhbadrReg_SPEC> as RegisterValue<_>>::new(133955584)
222 }
223}
224
225#[doc(hidden)]
226#[derive(Copy, Clone, Eq, PartialEq)]
227pub struct OtpcCeladrReg_SPEC;
228impl crate::sealed::RegSpec for OtpcCeladrReg_SPEC {
229 type DataType = u32;
230}
231
232#[doc = "Macrocell start address"]
233pub type OtpcCeladrReg = crate::RegValueT<OtpcCeladrReg_SPEC>;
234
235impl OtpcCeladrReg {
236 #[doc = "This is a readonly field that contains the \"live\" value of the OTP cell address as it is used by the hardware of the OTPC controller during the AREAD and the APROG modes. The value of the register is updated only while the OTPC is in AREAD or the APROG mode."]
237 #[inline(always)]
238 pub fn otpc_celadr_lv(
239 self,
240 ) -> crate::common::RegisterField<
241 16,
242 0x3fff,
243 1,
244 0,
245 u16,
246 u16,
247 OtpcCeladrReg_SPEC,
248 crate::common::R,
249 > {
250 crate::common::RegisterField::<
251 16,
252 0x3fff,
253 1,
254 0,
255 u16,
256 u16,
257 OtpcCeladrReg_SPEC,
258 crate::common::R,
259 >::from_register(self, 0)
260 }
261
262 #[doc = "It represents an OTP address, where the OTP word width should be considered equal to 32-bits.\nThe physical word width of the OTP memory is 72 bits. The 8-bits of them are used for the implementation of an error correcting code and are not available for the application. The remaining 64 bits of the physical word are available for the application. \nThe OTPC_CELADDR can distinguish the upper 32 bits from the lower 32 bits of the available for the application bits of the OTP word.\nWhen OTPC_CELADDR\\[0\\] = 1 the address refers to the upper 32 bits of the physical OTP address OTPC_CELADDR\\[14:1\\].\nThe register is used during the modes: AREAD and APROG.\nThe value of the register remains unchanged, by the internal logic of the controller."]
263 #[inline(always)]
264 pub fn otpc_celadr(
265 self,
266 ) -> crate::common::RegisterField<
267 0,
268 0x3fff,
269 1,
270 0,
271 u16,
272 u16,
273 OtpcCeladrReg_SPEC,
274 crate::common::RW,
275 > {
276 crate::common::RegisterField::<
277 0,
278 0x3fff,
279 1,
280 0,
281 u16,
282 u16,
283 OtpcCeladrReg_SPEC,
284 crate::common::RW,
285 >::from_register(self, 0)
286 }
287}
288impl ::core::default::Default for OtpcCeladrReg {
289 #[inline(always)]
290 fn default() -> OtpcCeladrReg {
291 <crate::RegValueT<OtpcCeladrReg_SPEC> as RegisterValue<_>>::new(0)
292 }
293}
294
295#[doc(hidden)]
296#[derive(Copy, Clone, Eq, PartialEq)]
297pub struct OtpcFfprtReg_SPEC;
298impl crate::sealed::RegSpec for OtpcFfprtReg_SPEC {
299 type DataType = u32;
300}
301
302#[doc = "Ports access to fifo logic"]
303pub type OtpcFfprtReg = crate::RegValueT<OtpcFfprtReg_SPEC>;
304
305impl OtpcFfprtReg {
306 #[doc = "Provides access to the fifo through an access port.\nWrite to this register with the corresponding data, when the APROG mode is selected and the dma is disabled.\nRead from this register the corresponding data, when the AREAD mode is selected and the dma is disabled.\nThe software should check the OTPCC_STAT_FWORDS register for the availability of data/space, before accessing the fifo."]
307 #[inline(always)]
308 pub fn otpc_ffprt(
309 self,
310 ) -> crate::common::RegisterField<
311 0,
312 0xffffffff,
313 1,
314 0,
315 u32,
316 u32,
317 OtpcFfprtReg_SPEC,
318 crate::common::RW,
319 > {
320 crate::common::RegisterField::<
321 0,
322 0xffffffff,
323 1,
324 0,
325 u32,
326 u32,
327 OtpcFfprtReg_SPEC,
328 crate::common::RW,
329 >::from_register(self, 0)
330 }
331}
332impl ::core::default::Default for OtpcFfprtReg {
333 #[inline(always)]
334 fn default() -> OtpcFfprtReg {
335 <crate::RegValueT<OtpcFfprtReg_SPEC> as RegisterValue<_>>::new(0)
336 }
337}
338
339#[doc(hidden)]
340#[derive(Copy, Clone, Eq, PartialEq)]
341pub struct OtpcFfrdReg_SPEC;
342impl crate::sealed::RegSpec for OtpcFfrdReg_SPEC {
343 type DataType = u32;
344}
345
346#[doc = "The data which have taken with the latest read from the OTPC_FFPRT_REG"]
347pub type OtpcFfrdReg = crate::RegValueT<OtpcFfrdReg_SPEC>;
348
349impl OtpcFfrdReg {
350 #[doc = "Contains the value which taken from the fifo, after a read of the OTPC_FFPRT_REG register."]
351 #[inline(always)]
352 pub fn otpc_ffrd(
353 self,
354 ) -> crate::common::RegisterField<
355 0,
356 0xffffffff,
357 1,
358 0,
359 u32,
360 u32,
361 OtpcFfrdReg_SPEC,
362 crate::common::R,
363 > {
364 crate::common::RegisterField::<
365 0,
366 0xffffffff,
367 1,
368 0,
369 u32,
370 u32,
371 OtpcFfrdReg_SPEC,
372 crate::common::R,
373 >::from_register(self, 0)
374 }
375}
376impl ::core::default::Default for OtpcFfrdReg {
377 #[inline(always)]
378 fn default() -> OtpcFfrdReg {
379 <crate::RegValueT<OtpcFfrdReg_SPEC> as RegisterValue<_>>::new(0)
380 }
381}
382
383#[doc(hidden)]
384#[derive(Copy, Clone, Eq, PartialEq)]
385pub struct OtpcModeReg_SPEC;
386impl crate::sealed::RegSpec for OtpcModeReg_SPEC {
387 type DataType = u32;
388}
389
390#[doc = "Mode register"]
391pub type OtpcModeReg = crate::RegValueT<OtpcModeReg_SPEC>;
392
393impl OtpcModeReg {
394 #[doc = "Write with 1 in order to be requested the reloading of the repair records. The reloading of the repair records will be performed at the next enabling of the OTP cell. That means that first the controller should be configured to the STBY mode and after should be activated any other mode. The hardware will clear this register, when the reloading will be performed.\nThe reloading has meaning only if the repair records have been updated manually (MPROG mode)."]
395 #[inline(always)]
396 pub fn otpc_mode_rld_rr_req(
397 self,
398 ) -> crate::common::RegisterFieldBool<9, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
399 crate::common::RegisterFieldBool::<9,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
400 }
401
402 #[doc = "Selects the memory area of the OTP cell that will be used.\n0: Uses the normal memory area of the OTP cell\n1: Uses the spare rows of the OTP cell\nThis selection has meaning only if the mode of the controller is not TDEC and TWR. The controller should be in STBY mode, in order to takes into account this bit. The selection will take effect at the next mode that will be enabled."]
403 #[inline(always)]
404 pub fn otpc_mode_use_sp_rows(
405 self,
406 ) -> crate::common::RegisterFieldBool<8, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
407 crate::common::RegisterFieldBool::<8,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
408 }
409
410 #[doc = "When is performed a read from the OTP memory in the MREAD mode, a double error is likely be detected during the retrieving of the data from the OTP. This error condition is always indicated in the status bit OTPC_STAT_REG\\[OTPC_STAT_RERROR\\]. However, the OTP controller has also the ability to indicates this error condition, by generating an ERROR response in the AHB bus.\nThe generation of the ERROR response can be avoided with the help of this configuration bit.\n0: The OTP controller generates an ERROR response in the AHB bus, when a double error is detected during a reading in MREAD mode. The OTPC_STAT_REG\\[OTPC_STAT_RERROR\\] is also updated. The receiving of an ERROR response by the CPU causes a Hard Fault exception in the CPU.\n1: Only the OTPC_STAT_REG\\[OTPC_STAT_RERROR\\] is updated in a case of such error. The OTP controller will not generate an ERROR response in the AHB bus."]
411 #[inline(always)]
412 pub fn otpc_mode_err_resp_dis(
413 self,
414 ) -> crate::common::RegisterFieldBool<6, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
415 crate::common::RegisterFieldBool::<6,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
416 }
417
418 #[doc = "By writing with 1, removes any content from the fifo. This bit returns automatically to value 0."]
419 #[inline(always)]
420 pub fn otpc_mode_fifo_flush(
421 self,
422 ) -> crate::common::RegisterFieldBool<5, 1, 0, OtpcModeReg_SPEC, crate::common::W> {
423 crate::common::RegisterFieldBool::<5,1,0,OtpcModeReg_SPEC,crate::common::W>::from_register(self,0)
424 }
425
426 #[doc = "Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG.\n0: The dma is not used. The data should be transferred from/to controller through the register OTPC_FFPRT_REG.\n1: The dma is used. The data transfers from/to controller are performed automatically, with the help of the internal DMA of the OTP controller. The AHB base address should be configured in register OTPC_AHBADR_REG, before the selection of one of the two modes: AREAD or APROG."]
427 #[inline(always)]
428 pub fn otpc_mode_use_dma(
429 self,
430 ) -> crate::common::RegisterFieldBool<4, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
431 crate::common::RegisterFieldBool::<4,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
432 }
433
434 #[doc = "Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows:\n0x0: STBY mode\n0x1: MREAD mode\n0x2: MPROG mode\n0x3: AREAD mode\n0x4: APROG mode\n0x5: TBLANK mode\n0x6: TDEC mode\n0x7: TWR mode"]
435 #[inline(always)]
436 pub fn otpc_mode_mode(
437 self,
438 ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, OtpcModeReg_SPEC, crate::common::RW>
439 {
440 crate::common::RegisterField::<0,0x7,1,0,u8,u8,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
441 }
442}
443impl ::core::default::Default for OtpcModeReg {
444 #[inline(always)]
445 fn default() -> OtpcModeReg {
446 <crate::RegValueT<OtpcModeReg_SPEC> as RegisterValue<_>>::new(0)
447 }
448}
449
450#[doc(hidden)]
451#[derive(Copy, Clone, Eq, PartialEq)]
452pub struct OtpcNwordsReg_SPEC;
453impl crate::sealed::RegSpec for OtpcNwordsReg_SPEC {
454 type DataType = u32;
455}
456
457#[doc = "Number of words"]
458pub type OtpcNwordsReg = crate::RegValueT<OtpcNwordsReg_SPEC>;
459
460impl OtpcNwordsReg {
461 #[doc = "The number of words (minus one) for reading /programming during the AREAD/APROG mode.\nThe width of the word should be considered equal to 32-bits.\nThe value of the register remains unchanged, by the internal logic of the controller.\nDuring mirroring, this register reflects the current ammount of copied data."]
462 #[inline(always)]
463 pub fn otpc_nwords(
464 self,
465 ) -> crate::common::RegisterField<
466 0,
467 0x3fff,
468 1,
469 0,
470 u16,
471 u16,
472 OtpcNwordsReg_SPEC,
473 crate::common::RW,
474 > {
475 crate::common::RegisterField::<
476 0,
477 0x3fff,
478 1,
479 0,
480 u16,
481 u16,
482 OtpcNwordsReg_SPEC,
483 crate::common::RW,
484 >::from_register(self, 0)
485 }
486}
487impl ::core::default::Default for OtpcNwordsReg {
488 #[inline(always)]
489 fn default() -> OtpcNwordsReg {
490 <crate::RegValueT<OtpcNwordsReg_SPEC> as RegisterValue<_>>::new(0)
491 }
492}
493
494#[doc(hidden)]
495#[derive(Copy, Clone, Eq, PartialEq)]
496pub struct OtpcPctrlReg_SPEC;
497impl crate::sealed::RegSpec for OtpcPctrlReg_SPEC {
498 type DataType = u32;
499}
500
501#[doc = "Bit-programming control register"]
502pub type OtpcPctrlReg = crate::RegValueT<OtpcPctrlReg_SPEC>;
503
504impl OtpcPctrlReg {
505 #[doc = "Write with \'1\' to trigger the programming of one OTP word, in the case where the MPROG mode is selected. The bit is cleared automatically. The 64-bits that will be programmed into the OTP memory are contained into the two registers OTPC_PWORDx_REG.\nThis bit should be used when a new programming is initiated, but also when the programming must be retried.\nThe OTPC_PCTRL_WADDR defines the OTP position where will be performed the programming."]
506 #[inline(always)]
507 pub fn otpc_pctrl_pstart(
508 self,
509 ) -> crate::common::RegisterFieldBool<15, 1, 0, OtpcPctrlReg_SPEC, crate::common::W> {
510 crate::common::RegisterFieldBool::<15,1,0,OtpcPctrlReg_SPEC,crate::common::W>::from_register(self,0)
511 }
512
513 #[doc = "It distinguishes the first attempt of a programming of an OTP position, from a retry of programming.\n0: A new value will be programmed in a blank OTP position. The hardware will try to write all the bits that are equal to \'1\'.\n1: The programming that is applied is not the first attempt, but is a request for reprogramming. Will be processed only the bits that were failed to be programmed during the previous attempt. The hardware knows the bits that were failed during the previous attempt.\nThe registers OTPC_PWORDx_REG should contain the 64 bits of the value that should be programmed, independent of the value of the OTPC_PCTRL_PRETRY bit.\nAlso, the OTPC_PCTRL_WADDR should contain always the required OTP address.\nA retry of a programming should be requested only if the previous action was the first attempt of programming or a retry of programming. Should not be requested a retry if the first attempt has not been performed."]
514 #[inline(always)]
515 pub fn otpc_pctrl_pretry(
516 self,
517 ) -> crate::common::RegisterFieldBool<14, 1, 0, OtpcPctrlReg_SPEC, crate::common::RW> {
518 crate::common::RegisterFieldBool::<14,1,0,OtpcPctrlReg_SPEC,crate::common::RW>::from_register(self,0)
519 }
520
521 #[doc = "Defines the OTP position where will be programmed the 64-bits that are contained into the registers OTPC_PWORDx_REG. It points to a physical 72 bits OTP word."]
522 #[inline(always)]
523 pub fn otpc_pctrl_waddr(
524 self,
525 ) -> crate::common::RegisterField<0, 0x1fff, 1, 0, u16, u16, OtpcPctrlReg_SPEC, crate::common::RW>
526 {
527 crate::common::RegisterField::<
528 0,
529 0x1fff,
530 1,
531 0,
532 u16,
533 u16,
534 OtpcPctrlReg_SPEC,
535 crate::common::RW,
536 >::from_register(self, 0)
537 }
538}
539impl ::core::default::Default for OtpcPctrlReg {
540 #[inline(always)]
541 fn default() -> OtpcPctrlReg {
542 <crate::RegValueT<OtpcPctrlReg_SPEC> as RegisterValue<_>>::new(0)
543 }
544}
545
546#[doc(hidden)]
547#[derive(Copy, Clone, Eq, PartialEq)]
548pub struct OtpcPwordhReg_SPEC;
549impl crate::sealed::RegSpec for OtpcPwordhReg_SPEC {
550 type DataType = u32;
551}
552
553#[doc = "The 32 higher bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
554pub type OtpcPwordhReg = crate::RegValueT<OtpcPwordhReg_SPEC>;
555
556impl OtpcPwordhReg {
557 #[doc = "Contains the upper 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode."]
558 #[inline(always)]
559 pub fn otpc_pwordh(
560 self,
561 ) -> crate::common::RegisterField<
562 0,
563 0xffffffff,
564 1,
565 0,
566 u32,
567 u32,
568 OtpcPwordhReg_SPEC,
569 crate::common::RW,
570 > {
571 crate::common::RegisterField::<
572 0,
573 0xffffffff,
574 1,
575 0,
576 u32,
577 u32,
578 OtpcPwordhReg_SPEC,
579 crate::common::RW,
580 >::from_register(self, 0)
581 }
582}
583impl ::core::default::Default for OtpcPwordhReg {
584 #[inline(always)]
585 fn default() -> OtpcPwordhReg {
586 <crate::RegValueT<OtpcPwordhReg_SPEC> as RegisterValue<_>>::new(0)
587 }
588}
589
590#[doc(hidden)]
591#[derive(Copy, Clone, Eq, PartialEq)]
592pub struct OtpcPwordlReg_SPEC;
593impl crate::sealed::RegSpec for OtpcPwordlReg_SPEC {
594 type DataType = u32;
595}
596
597#[doc = "The 32 lower bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
598pub type OtpcPwordlReg = crate::RegValueT<OtpcPwordlReg_SPEC>;
599
600impl OtpcPwordlReg {
601 #[doc = "Contains the lower 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode."]
602 #[inline(always)]
603 pub fn otpc_pwordl(
604 self,
605 ) -> crate::common::RegisterField<
606 0,
607 0xffffffff,
608 1,
609 0,
610 u32,
611 u32,
612 OtpcPwordlReg_SPEC,
613 crate::common::RW,
614 > {
615 crate::common::RegisterField::<
616 0,
617 0xffffffff,
618 1,
619 0,
620 u32,
621 u32,
622 OtpcPwordlReg_SPEC,
623 crate::common::RW,
624 >::from_register(self, 0)
625 }
626}
627impl ::core::default::Default for OtpcPwordlReg {
628 #[inline(always)]
629 fn default() -> OtpcPwordlReg {
630 <crate::RegValueT<OtpcPwordlReg_SPEC> as RegisterValue<_>>::new(0)
631 }
632}
633
634#[doc(hidden)]
635#[derive(Copy, Clone, Eq, PartialEq)]
636pub struct OtpcStatReg_SPEC;
637impl crate::sealed::RegSpec for OtpcStatReg_SPEC {
638 type DataType = u32;
639}
640
641#[doc = "Status register"]
642pub type OtpcStatReg = crate::RegValueT<OtpcStatReg_SPEC>;
643
644impl OtpcStatReg {
645 #[doc = "It contains the \"live\" value of the number of (32 bits) words that remain to be processed by the controller."]
646 #[inline(always)]
647 pub fn otpc_stat_nwords(
648 self,
649 ) -> crate::common::RegisterField<16, 0x3fff, 1, 0, u16, u16, OtpcStatReg_SPEC, crate::common::R>
650 {
651 crate::common::RegisterField::<16,0x3fff,1,0,u16,u16,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
652 }
653
654 #[doc = "Indicates the number of words which contained in the fifo of the controller."]
655 #[inline(always)]
656 pub fn otpc_stat_fwords(
657 self,
658 ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, OtpcStatReg_SPEC, crate::common::R>
659 {
660 crate::common::RegisterField::<8,0xf,1,0,u8,u8,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
661 }
662
663 #[doc = "Indicates that during a normal reading (MREAD or AREAD) was reported a double error by the SECDED logic. That means that the data are corrupted.\n0: The read data are considered as correct.\n1: The SECDED logic detects a double error.\nThis bit can be cleared only with a write with \'1\'."]
664 #[inline(always)]
665 pub fn otpc_stat_rerror(
666 self,
667 ) -> crate::common::RegisterFieldBool<7, 1, 0, OtpcStatReg_SPEC, crate::common::RW> {
668 crate::common::RegisterFieldBool::<7,1,0,OtpcStatReg_SPEC,crate::common::RW>::from_register(self,0)
669 }
670
671 #[doc = "Should be used to monitor the progress of the AREAD and APROG modes.\n0: One of the APROG or AREAD mode is selected. The controller is busy.\n1: The controller is not in an active AREAD or APROG mode."]
672 #[inline(always)]
673 pub fn otpc_stat_ardy(
674 self,
675 ) -> crate::common::RegisterFieldBool<6, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
676 crate::common::RegisterFieldBool::<6,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
677 }
678
679 #[doc = "Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY = 1).\n0: The test sequence ends with no error.\n1: The test sequence has failed."]
680 #[inline(always)]
681 pub fn otpc_stat_terror(
682 self,
683 ) -> crate::common::RegisterFieldBool<5, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
684 crate::common::RegisterFieldBool::<5,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
685 }
686
687 #[doc = "Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes.\n0: The controller is busy. One of the test modes is in progress.\n1: There is no active test mode."]
688 #[inline(always)]
689 pub fn otpc_stat_trdy(
690 self,
691 ) -> crate::common::RegisterFieldBool<4, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
692 crate::common::RegisterFieldBool::<4,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
693 }
694
695 #[doc = "Indicates that the programming sequence has been avoided during a programming request, due to that the word that should be programmed is equal to zero.\n0: At least one bit has been programmed into the OTP.\n1: The programming has not been performed. All the bits of the word that should be programmed are equal to zero.\nWhen the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more of words that have been processed are equal to zero."]
696 #[inline(always)]
697 pub fn otpc_stat_pzero(
698 self,
699 ) -> crate::common::RegisterFieldBool<3, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
700 crate::common::RegisterFieldBool::<3,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
701 }
702
703 #[doc = "Indicates that a correctable error has been occurred during the word programming process.\n0: There is no correctable error in the word-programming process.\n1: The process of word - programming reported a correctable error.\nThe correctable error occurs when exactly one bit in an OTP position cannot take the required value. This is not a critical failure in the programming process. The data can still be retrieved correctly by the OTP memory, due to that the error correcting algorithm can repair the corrupted bit.\nWhen the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more words had a correctable error."]
704 #[inline(always)]
705 pub fn otpc_stat_perr_cor(
706 self,
707 ) -> crate::common::RegisterFieldBool<2, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
708 crate::common::RegisterFieldBool::<2,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
709 }
710
711 #[doc = "Indicates that an uncorrectable error has been occurred during the word programming process.\n0: There is no uncorrectable error in the word-programming process.\n1: The process of word-programming failed due to an uncorrectable error.\nAn uncorrectable error is considered when two or more of the bits in an OTP position cannot take the required values. This is a critical failure in the programming process, which means that the data cannot corrected by the single error correcting algorithm.\nWhen the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates if the programming was failed or ended successfully."]
712 #[inline(always)]
713 pub fn otpc_stat_perr_unc(
714 self,
715 ) -> crate::common::RegisterFieldBool<1, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
716 crate::common::RegisterFieldBool::<1,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
717 }
718
719 #[doc = "Indicates the state of a bit-programming process.\n0: The controller is busy. A bit-programming is in progress\n1: The logic which performs bit-programming is idle.\nWhen the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request.\nDuring APROG mode, the value of this field it is normal to changing periodically."]
720 #[inline(always)]
721 pub fn otpc_stat_prdy(
722 self,
723 ) -> crate::common::RegisterFieldBool<0, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
724 crate::common::RegisterFieldBool::<0,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
725 }
726}
727impl ::core::default::Default for OtpcStatReg {
728 #[inline(always)]
729 fn default() -> OtpcStatReg {
730 <crate::RegValueT<OtpcStatReg_SPEC> as RegisterValue<_>>::new(81)
731 }
732}
733
734#[doc(hidden)]
735#[derive(Copy, Clone, Eq, PartialEq)]
736pub struct OtpcTim1Reg_SPEC;
737impl crate::sealed::RegSpec for OtpcTim1Reg_SPEC {
738 type DataType = u32;
739}
740
741#[doc = "Various timing parameters of the OTP cell."]
742pub type OtpcTim1Reg = crate::RegValueT<OtpcTim1Reg_SPEC>;
743
744impl OtpcTim1Reg {
745 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 25 ns."]
746 #[inline(always)]
747 pub fn otpc_tim1_cc_t_25ns(
748 self,
749 ) -> crate::common::RegisterFieldBool<31, 1, 0, OtpcTim1Reg_SPEC, crate::common::RW> {
750 crate::common::RegisterFieldBool::<31,1,0,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
751 }
752
753 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 200 ns."]
754 #[inline(always)]
755 pub fn otpc_tim1_cc_t_200ns(
756 self,
757 ) -> crate::common::RegisterField<27, 0xf, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
758 {
759 crate::common::RegisterField::<27,0xf,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
760 }
761
762 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 500 ns"]
763 #[inline(always)]
764 pub fn otpc_tim1_cc_t_500ns(
765 self,
766 ) -> crate::common::RegisterField<22, 0x1f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
767 {
768 crate::common::RegisterField::<22,0x1f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
769 }
770
771 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 1 us."]
772 #[inline(always)]
773 pub fn otpc_tim1_cc_t_1us(
774 self,
775 ) -> crate::common::RegisterField<16, 0x3f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
776 {
777 crate::common::RegisterField::<16,0x3f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
778 }
779
780 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval that is\n- at least higher than 4.8 us\n- and lower than 5.2 us\nIt is preferred the programmed value to give a time interval equal to 5 us.\nIt defines the duration of the programming pulse for every bit that written in the OTP cell."]
781 #[inline(always)]
782 pub fn otpc_tim1_cc_t_pw(
783 self,
784 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
785 {
786 crate::common::RegisterField::<8,0xff,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
787 }
788
789 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 2 us. It is used as a wait time each time where the OTP cell is enabled."]
790 #[inline(always)]
791 pub fn otpc_tim1_cc_t_cadx(
792 self,
793 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
794 {
795 crate::common::RegisterField::<0,0xff,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
796 }
797}
798impl ::core::default::Default for OtpcTim1Reg {
799 #[inline(always)]
800 fn default() -> OtpcTim1Reg {
801 <crate::RegValueT<OtpcTim1Reg_SPEC> as RegisterValue<_>>::new(437276448)
802 }
803}
804
805#[doc(hidden)]
806#[derive(Copy, Clone, Eq, PartialEq)]
807pub struct OtpcTim2Reg_SPEC;
808impl crate::sealed::RegSpec for OtpcTim2Reg_SPEC {
809 type DataType = u32;
810}
811
812#[doc = "Various timing parameters of the OTP cell."]
813pub type OtpcTim2Reg = crate::RegValueT<OtpcTim2Reg_SPEC>;
814
815impl OtpcTim2Reg {
816 #[doc = "This bit has meaning only when the OTPC_TIM1_CC_T_25NS = 1, otherwise has no functionality. \n0: The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is one clock cycle. This is also applicable if OTPC_TIM1_CC_T_25NS = 0.\n1: The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is two clock cycles. The controller adds one extra wait state in the AHB access , if it is required, in order to achieves this constraint. This setting is applicable only if OTPC_TIM1_CC_T_25NS = 1."]
817 #[inline(always)]
818 pub fn otpc_tim2_rdenl_prot(
819 self,
820 ) -> crate::common::RegisterFieldBool<23, 1, 0, OtpcTim2Reg_SPEC, crate::common::RW> {
821 crate::common::RegisterFieldBool::<23,1,0,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
822 }
823
824 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval between 100 ns and 200 ns. This time interval is used for the reading of the contents of the OTP cell during the TBLANK mode."]
825 #[inline(always)]
826 pub fn otpc_tim2_cc_t_bchk(
827 self,
828 ) -> crate::common::RegisterField<16, 0x7f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
829 {
830 crate::common::RegisterField::<16,0x7f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
831 }
832
833 #[doc = "This register controls a power saving feature, which is applicable only in MREAD mode. The controller monitors the accesses in the OTP cell. If there is no access for more than OTPC_TIM2_CC_STBY_THR hclk_c clock cycles, the OTP cell goes to the standby while the controller itself remains in the MREAD mode. The OTP cell will be enabled again when will be applied a new read request. The enabling of the OTP cell has a cost of 2 us (OTPC_TIM1_CC_T_CADX hclk_c clock cycles).\nWhen OTPC_TIM2_CC_STBY_THR = 0 the power saving feature is disabled and the OTP cell remains active while the controller is in MREAD mode."]
834 #[inline(always)]
835 pub fn otpc_tim2_cc_stby_thr(
836 self,
837 ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, OtpcTim2Reg_SPEC, crate::common::RW>
838 {
839 crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
840 }
841}
842impl ::core::default::Default for OtpcTim2Reg {
843 #[inline(always)]
844 fn default() -> OtpcTim2Reg {
845 <crate::RegValueT<OtpcTim2Reg_SPEC> as RegisterValue<_>>::new(65536)
846 }
847}