1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"OTPC registers"]
28unsafe impl ::core::marker::Send for super::Otpc {}
29unsafe impl ::core::marker::Sync for super::Otpc {}
30impl super::Otpc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "AHB master start address"]
38 #[inline(always)]
39 pub const fn otpc_ahbadr_reg(
40 &self,
41 ) -> &'static crate::common::Reg<self::OtpcAhbadrReg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::OtpcAhbadrReg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(12usize),
45 )
46 }
47 }
48
49 #[doc = "Macrocell start address"]
50 #[inline(always)]
51 pub const fn otpc_celadr_reg(
52 &self,
53 ) -> &'static crate::common::Reg<self::OtpcCeladrReg_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::OtpcCeladrReg_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(16usize),
57 )
58 }
59 }
60
61 #[doc = "Ports access to fifo logic"]
62 #[inline(always)]
63 pub const fn otpc_ffprt_reg(
64 &self,
65 ) -> &'static crate::common::Reg<self::OtpcFfprtReg_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::OtpcFfprtReg_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(24usize),
69 )
70 }
71 }
72
73 #[doc = "The data which have taken with the latest read from the OTPC_FFPRT_REG"]
74 #[inline(always)]
75 pub const fn otpc_ffrd_reg(
76 &self,
77 ) -> &'static crate::common::Reg<self::OtpcFfrdReg_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::OtpcFfrdReg_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(28usize),
81 )
82 }
83 }
84
85 #[doc = "Mode register"]
86 #[inline(always)]
87 pub const fn otpc_mode_reg(
88 &self,
89 ) -> &'static crate::common::Reg<self::OtpcModeReg_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::OtpcModeReg_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(0usize),
93 )
94 }
95 }
96
97 #[doc = "Number of words"]
98 #[inline(always)]
99 pub const fn otpc_nwords_reg(
100 &self,
101 ) -> &'static crate::common::Reg<self::OtpcNwordsReg_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::OtpcNwordsReg_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(20usize),
105 )
106 }
107 }
108
109 #[doc = "Bit-programming control register"]
110 #[inline(always)]
111 pub const fn otpc_pctrl_reg(
112 &self,
113 ) -> &'static crate::common::Reg<self::OtpcPctrlReg_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::OtpcPctrlReg_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(4usize),
117 )
118 }
119 }
120
121 #[doc = "The 32 higher bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
122 #[inline(always)]
123 pub const fn otpc_pwordh_reg(
124 &self,
125 ) -> &'static crate::common::Reg<self::OtpcPwordhReg_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::OtpcPwordhReg_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(36usize),
129 )
130 }
131 }
132
133 #[doc = "The 32 lower bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
134 #[inline(always)]
135 pub const fn otpc_pwordl_reg(
136 &self,
137 ) -> &'static crate::common::Reg<self::OtpcPwordlReg_SPEC, crate::common::RW> {
138 unsafe {
139 crate::common::Reg::<self::OtpcPwordlReg_SPEC, crate::common::RW>::from_ptr(
140 self._svd2pac_as_ptr().add(32usize),
141 )
142 }
143 }
144
145 #[doc = "Status register"]
146 #[inline(always)]
147 pub const fn otpc_stat_reg(
148 &self,
149 ) -> &'static crate::common::Reg<self::OtpcStatReg_SPEC, crate::common::RW> {
150 unsafe {
151 crate::common::Reg::<self::OtpcStatReg_SPEC, crate::common::RW>::from_ptr(
152 self._svd2pac_as_ptr().add(8usize),
153 )
154 }
155 }
156
157 #[doc = "Various timing parameters of the OTP cell."]
158 #[inline(always)]
159 pub const fn otpc_tim1_reg(
160 &self,
161 ) -> &'static crate::common::Reg<self::OtpcTim1Reg_SPEC, crate::common::RW> {
162 unsafe {
163 crate::common::Reg::<self::OtpcTim1Reg_SPEC, crate::common::RW>::from_ptr(
164 self._svd2pac_as_ptr().add(40usize),
165 )
166 }
167 }
168
169 #[doc = "Various timing parameters of the OTP cell."]
170 #[inline(always)]
171 pub const fn otpc_tim2_reg(
172 &self,
173 ) -> &'static crate::common::Reg<self::OtpcTim2Reg_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::OtpcTim2Reg_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(44usize),
177 )
178 }
179 }
180}
181#[doc(hidden)]
182#[derive(Copy, Clone, Eq, PartialEq)]
183pub struct OtpcAhbadrReg_SPEC;
184impl crate::sealed::RegSpec for OtpcAhbadrReg_SPEC {
185 type DataType = u32;
186}
187
188#[doc = "AHB master start address"]
189pub type OtpcAhbadrReg = crate::RegValueT<OtpcAhbadrReg_SPEC>;
190
191impl OtpcAhbadrReg {
192 #[doc = "It is the AHB address used by the AHB master interface of the controller (the bits \\[31:2\\]). The bits \\[1:0\\] of the address are considered always as equal to zero."]
193 #[inline(always)]
194 pub fn otpc_ahbadr(
195 self,
196 ) -> crate::common::RegisterField<
197 2,
198 0x3fffffff,
199 1,
200 0,
201 u32,
202 u32,
203 OtpcAhbadrReg_SPEC,
204 crate::common::RW,
205 > {
206 crate::common::RegisterField::<
207 2,
208 0x3fffffff,
209 1,
210 0,
211 u32,
212 u32,
213 OtpcAhbadrReg_SPEC,
214 crate::common::RW,
215 >::from_register(self, 0)
216 }
217}
218impl ::core::default::Default for OtpcAhbadrReg {
219 #[inline(always)]
220 fn default() -> OtpcAhbadrReg {
221 <crate::RegValueT<OtpcAhbadrReg_SPEC> as RegisterValue<_>>::new(133955584)
222 }
223}
224
225#[doc(hidden)]
226#[derive(Copy, Clone, Eq, PartialEq)]
227pub struct OtpcCeladrReg_SPEC;
228impl crate::sealed::RegSpec for OtpcCeladrReg_SPEC {
229 type DataType = u32;
230}
231
232#[doc = "Macrocell start address"]
233pub type OtpcCeladrReg = crate::RegValueT<OtpcCeladrReg_SPEC>;
234
235impl OtpcCeladrReg {
236 #[doc = "It represents an OTP address, where the OTP word width should be considered equal to 32-bits.\nThe physical word width of the OTP memory is 72 bits. The 8-bits of them are used for the implementation of an error correcting code and are not available for the application. The remaining 64 bits of the physical word are available for the application. \nThe OTPC_CELADDR can distinguish the upper 32 bits from the lower 32 bits of the available for the application bits of the OTP word.\nWhen OTPC_CELADDR\\[0\\] = 1 the address refers to the upper 32 bits of the physical OTP address OTPC_CELADDR\\[14:1\\].\nThe register is used during the modes: AREAD and APROG."]
237 #[inline(always)]
238 pub fn otpc_celadr(
239 self,
240 ) -> crate::common::RegisterField<
241 0,
242 0x3fff,
243 1,
244 0,
245 u16,
246 u16,
247 OtpcCeladrReg_SPEC,
248 crate::common::RW,
249 > {
250 crate::common::RegisterField::<
251 0,
252 0x3fff,
253 1,
254 0,
255 u16,
256 u16,
257 OtpcCeladrReg_SPEC,
258 crate::common::RW,
259 >::from_register(self, 0)
260 }
261}
262impl ::core::default::Default for OtpcCeladrReg {
263 #[inline(always)]
264 fn default() -> OtpcCeladrReg {
265 <crate::RegValueT<OtpcCeladrReg_SPEC> as RegisterValue<_>>::new(0)
266 }
267}
268
269#[doc(hidden)]
270#[derive(Copy, Clone, Eq, PartialEq)]
271pub struct OtpcFfprtReg_SPEC;
272impl crate::sealed::RegSpec for OtpcFfprtReg_SPEC {
273 type DataType = u32;
274}
275
276#[doc = "Ports access to fifo logic"]
277pub type OtpcFfprtReg = crate::RegValueT<OtpcFfprtReg_SPEC>;
278
279impl OtpcFfprtReg {
280 #[doc = "Provides access to the fifo through an access port.\nWrite to this register with the corresponding data, when the APROG mode is selected and the dma is disabled.\nRead from this register the corresponding data, when the AREAD mode is selected and the dma is disabled.\nThe software should check the OTPCC_STAT_FWORDS register for the availability of data/space, before accessing the fifo."]
281 #[inline(always)]
282 pub fn otpc_ffprt(
283 self,
284 ) -> crate::common::RegisterField<
285 0,
286 0xffffffff,
287 1,
288 0,
289 u32,
290 u32,
291 OtpcFfprtReg_SPEC,
292 crate::common::RW,
293 > {
294 crate::common::RegisterField::<
295 0,
296 0xffffffff,
297 1,
298 0,
299 u32,
300 u32,
301 OtpcFfprtReg_SPEC,
302 crate::common::RW,
303 >::from_register(self, 0)
304 }
305}
306impl ::core::default::Default for OtpcFfprtReg {
307 #[inline(always)]
308 fn default() -> OtpcFfprtReg {
309 <crate::RegValueT<OtpcFfprtReg_SPEC> as RegisterValue<_>>::new(0)
310 }
311}
312
313#[doc(hidden)]
314#[derive(Copy, Clone, Eq, PartialEq)]
315pub struct OtpcFfrdReg_SPEC;
316impl crate::sealed::RegSpec for OtpcFfrdReg_SPEC {
317 type DataType = u32;
318}
319
320#[doc = "The data which have taken with the latest read from the OTPC_FFPRT_REG"]
321pub type OtpcFfrdReg = crate::RegValueT<OtpcFfrdReg_SPEC>;
322
323impl OtpcFfrdReg {
324 #[doc = "Contains the value which taken from the fifo, after a read of the OTPC_FFPRT_REG register."]
325 #[inline(always)]
326 pub fn otpc_ffrd(
327 self,
328 ) -> crate::common::RegisterField<
329 0,
330 0xffffffff,
331 1,
332 0,
333 u32,
334 u32,
335 OtpcFfrdReg_SPEC,
336 crate::common::R,
337 > {
338 crate::common::RegisterField::<
339 0,
340 0xffffffff,
341 1,
342 0,
343 u32,
344 u32,
345 OtpcFfrdReg_SPEC,
346 crate::common::R,
347 >::from_register(self, 0)
348 }
349}
350impl ::core::default::Default for OtpcFfrdReg {
351 #[inline(always)]
352 fn default() -> OtpcFfrdReg {
353 <crate::RegValueT<OtpcFfrdReg_SPEC> as RegisterValue<_>>::new(0)
354 }
355}
356
357#[doc(hidden)]
358#[derive(Copy, Clone, Eq, PartialEq)]
359pub struct OtpcModeReg_SPEC;
360impl crate::sealed::RegSpec for OtpcModeReg_SPEC {
361 type DataType = u32;
362}
363
364#[doc = "Mode register"]
365pub type OtpcModeReg = crate::RegValueT<OtpcModeReg_SPEC>;
366
367impl OtpcModeReg {
368 #[doc = "Write with 1 in order to be requested the reloading of the repair records. The reloading of the repair records will be performed at the next enabling of the OTP cell. That means that first the controller should be configured to the STBY mode and after should be activated any other mode. The hardware will clear this register, when the reloading will be performed.\nThe reloading has meaning only if the repair records have been updated manually (MPROG mode)."]
369 #[inline(always)]
370 pub fn otpc_mode_rld_rr_req(
371 self,
372 ) -> crate::common::RegisterFieldBool<9, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
373 crate::common::RegisterFieldBool::<9,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
374 }
375
376 #[doc = "Selects the memory area of the OTP cell that will be used.\n0 - Uses the normal memory area of the OTP cell\n1 - Uses the spare rows of the OTP cell\nThis selection has meaning only if the mode of the controller is not TDEC and TWR. The controller should be in STBY mode, in order to takes into account this bit. The selection will take effect at the next mode that will be enabled."]
377 #[inline(always)]
378 pub fn otpc_mode_use_sp_rows(
379 self,
380 ) -> crate::common::RegisterFieldBool<8, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
381 crate::common::RegisterFieldBool::<8,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
382 }
383
384 #[doc = "When is performed a read from the OTP memory in the MREAD mode, a double error is likely be detected during the retrieving of the data from the OTP. This error condition is always indicated in the status bit OTPC_STAT_REG\\[OTPC_STAT_RERROR\\]. However, the OTP controller has also the ability to indicates this error condition, by generating an ERROR response in the AHB bus.\nThe generation of the ERROR response can be avoided with the help of this configuration bit.\n0 - The OTP controller generates an ERROR response in the AHB bus, when a double error is detected during a reading in MREAD mode. The OTPC_STAT_REG\\[OTPC_STAT_RERROR\\] is also updated. The receiving of an ERROR response by the CPU causes a Hard Fault exception in the CPU.\n1 - Only the OTPC_STAT_REG\\[OTPC_STAT_RERROR\\] is updated in a case of such error. The OTP controller will not generate an ERROR response in the AHB bus."]
385 #[inline(always)]
386 pub fn otpc_mode_err_resp_dis(
387 self,
388 ) -> crate::common::RegisterFieldBool<6, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
389 crate::common::RegisterFieldBool::<6,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
390 }
391
392 #[doc = "By writing with 1, removes any content from the fifo. This bit returns automatically to value 0."]
393 #[inline(always)]
394 pub fn otpc_mode_fifo_flush(
395 self,
396 ) -> crate::common::RegisterFieldBool<5, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
397 crate::common::RegisterFieldBool::<5,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
398 }
399
400 #[doc = "Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG.\n0 - The dma is not used. The data should be transferred from/to controller through the register OTPC_FFPRT_REG.\n1 - The dma is used. The data transfers from/to controller are performed automatically, with the help of the internal DMA of the OTP controller. The AHB base address should be configured in register OTPC_AHBADR_REG, before the selection of one of the two modes: AREAD or APROG."]
401 #[inline(always)]
402 pub fn otpc_mode_use_dma(
403 self,
404 ) -> crate::common::RegisterFieldBool<4, 1, 0, OtpcModeReg_SPEC, crate::common::RW> {
405 crate::common::RegisterFieldBool::<4,1,0,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
406 }
407
408 #[doc = "Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows:\n000 - STBY mode\n001 - MREAD mode\n010 - MPROG mode\n011 - AREAD mode\n100 - APROG mode\n101 - TBLANK mode\n110 - TDEC mode\n111 - TWR mode"]
409 #[inline(always)]
410 pub fn otpc_mode_mode(
411 self,
412 ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, OtpcModeReg_SPEC, crate::common::RW>
413 {
414 crate::common::RegisterField::<0,0x7,1,0,u8,u8,OtpcModeReg_SPEC,crate::common::RW>::from_register(self,0)
415 }
416}
417impl ::core::default::Default for OtpcModeReg {
418 #[inline(always)]
419 fn default() -> OtpcModeReg {
420 <crate::RegValueT<OtpcModeReg_SPEC> as RegisterValue<_>>::new(0)
421 }
422}
423
424#[doc(hidden)]
425#[derive(Copy, Clone, Eq, PartialEq)]
426pub struct OtpcNwordsReg_SPEC;
427impl crate::sealed::RegSpec for OtpcNwordsReg_SPEC {
428 type DataType = u32;
429}
430
431#[doc = "Number of words"]
432pub type OtpcNwordsReg = crate::RegValueT<OtpcNwordsReg_SPEC>;
433
434impl OtpcNwordsReg {
435 #[doc = "The number of words (minus one) for reading /programming during the AREAD/APROG mode.\nThe width of the word should be considered equal to 32-bits.\nThe value of the register remains unchanged, by the internal logic of the controller.\nDuring mirroring, this register reflects the current ammount of copied data."]
436 #[inline(always)]
437 pub fn otpc_nwords(
438 self,
439 ) -> crate::common::RegisterField<
440 0,
441 0x3fff,
442 1,
443 0,
444 u16,
445 u16,
446 OtpcNwordsReg_SPEC,
447 crate::common::RW,
448 > {
449 crate::common::RegisterField::<
450 0,
451 0x3fff,
452 1,
453 0,
454 u16,
455 u16,
456 OtpcNwordsReg_SPEC,
457 crate::common::RW,
458 >::from_register(self, 0)
459 }
460}
461impl ::core::default::Default for OtpcNwordsReg {
462 #[inline(always)]
463 fn default() -> OtpcNwordsReg {
464 <crate::RegValueT<OtpcNwordsReg_SPEC> as RegisterValue<_>>::new(0)
465 }
466}
467
468#[doc(hidden)]
469#[derive(Copy, Clone, Eq, PartialEq)]
470pub struct OtpcPctrlReg_SPEC;
471impl crate::sealed::RegSpec for OtpcPctrlReg_SPEC {
472 type DataType = u32;
473}
474
475#[doc = "Bit-programming control register"]
476pub type OtpcPctrlReg = crate::RegValueT<OtpcPctrlReg_SPEC>;
477
478impl OtpcPctrlReg {
479 #[doc = "Write with \'1\' to trigger the programming of one OTP word, in the case where the MPROG mode is selected. The bit is cleared automatically. The 64-bits that will be programmed into the OTP memory are contained into the two registers OTPC_PWORDx_REG.\nThis bit should be used when a new programming is initiated, but also when the programming must be retried.\nThe OTPC_PCTRL_WADDR defines the OTP position where will be performed the programming."]
480 #[inline(always)]
481 pub fn otpc_pctrl_pstart(
482 self,
483 ) -> crate::common::RegisterFieldBool<15, 1, 0, OtpcPctrlReg_SPEC, crate::common::RW> {
484 crate::common::RegisterFieldBool::<15,1,0,OtpcPctrlReg_SPEC,crate::common::RW>::from_register(self,0)
485 }
486
487 #[doc = "It distinguishes the first attempt of a programming of an OTP position, from a retry of programming.\n0 - A new value will be programmed in a blank OTP position. The hardware will try to write all the bits that are equal to \'1\'.\n1 - The programming that is applied is not the first attempt, but is a request for reprogramming. Will be processed only the bits that were failed to be programmed during the previous attempt. The hardware knows the bits that were failed during the previous attempt.\nThe registers OTPC_PWORDx_REG should contain the 64 bits of the value that should be programmed, independent of the value of the OTPC_PCTRL_PRETRY bit.\nAlso, the OTPC_PCTRL_WADDR should contain always the required OTP address.\nA retry of a programming should be requested only if the previous action was the first attempt of programming or a retry of programming. Should not be requested a retry if the first attempt has not been performed."]
488 #[inline(always)]
489 pub fn otpc_pctrl_pretry(
490 self,
491 ) -> crate::common::RegisterFieldBool<14, 1, 0, OtpcPctrlReg_SPEC, crate::common::RW> {
492 crate::common::RegisterFieldBool::<14,1,0,OtpcPctrlReg_SPEC,crate::common::RW>::from_register(self,0)
493 }
494
495 #[doc = "Defines the OTP position where will be programmed the 64-bits that are contained into the registers OTPC_PWORDx_REG. It points to a physical 72 bits OTP word."]
496 #[inline(always)]
497 pub fn otpc_pctrl_waddr(
498 self,
499 ) -> crate::common::RegisterField<0, 0x1fff, 1, 0, u16, u16, OtpcPctrlReg_SPEC, crate::common::RW>
500 {
501 crate::common::RegisterField::<
502 0,
503 0x1fff,
504 1,
505 0,
506 u16,
507 u16,
508 OtpcPctrlReg_SPEC,
509 crate::common::RW,
510 >::from_register(self, 0)
511 }
512}
513impl ::core::default::Default for OtpcPctrlReg {
514 #[inline(always)]
515 fn default() -> OtpcPctrlReg {
516 <crate::RegValueT<OtpcPctrlReg_SPEC> as RegisterValue<_>>::new(0)
517 }
518}
519
520#[doc(hidden)]
521#[derive(Copy, Clone, Eq, PartialEq)]
522pub struct OtpcPwordhReg_SPEC;
523impl crate::sealed::RegSpec for OtpcPwordhReg_SPEC {
524 type DataType = u32;
525}
526
527#[doc = "The 32 higher bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
528pub type OtpcPwordhReg = crate::RegValueT<OtpcPwordhReg_SPEC>;
529
530impl OtpcPwordhReg {
531 #[doc = "Contains the upper 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode."]
532 #[inline(always)]
533 pub fn otpc_pwordh(
534 self,
535 ) -> crate::common::RegisterField<
536 0,
537 0xffffffff,
538 1,
539 0,
540 u32,
541 u32,
542 OtpcPwordhReg_SPEC,
543 crate::common::RW,
544 > {
545 crate::common::RegisterField::<
546 0,
547 0xffffffff,
548 1,
549 0,
550 u32,
551 u32,
552 OtpcPwordhReg_SPEC,
553 crate::common::RW,
554 >::from_register(self, 0)
555 }
556}
557impl ::core::default::Default for OtpcPwordhReg {
558 #[inline(always)]
559 fn default() -> OtpcPwordhReg {
560 <crate::RegValueT<OtpcPwordhReg_SPEC> as RegisterValue<_>>::new(0)
561 }
562}
563
564#[doc(hidden)]
565#[derive(Copy, Clone, Eq, PartialEq)]
566pub struct OtpcPwordlReg_SPEC;
567impl crate::sealed::RegSpec for OtpcPwordlReg_SPEC {
568 type DataType = u32;
569}
570
571#[doc = "The 32 lower bits of the 64-bit word that will be programmed, when the MPROG mode is used."]
572pub type OtpcPwordlReg = crate::RegValueT<OtpcPwordlReg_SPEC>;
573
574impl OtpcPwordlReg {
575 #[doc = "Contains the lower 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode."]
576 #[inline(always)]
577 pub fn otpc_pwordl(
578 self,
579 ) -> crate::common::RegisterField<
580 0,
581 0xffffffff,
582 1,
583 0,
584 u32,
585 u32,
586 OtpcPwordlReg_SPEC,
587 crate::common::RW,
588 > {
589 crate::common::RegisterField::<
590 0,
591 0xffffffff,
592 1,
593 0,
594 u32,
595 u32,
596 OtpcPwordlReg_SPEC,
597 crate::common::RW,
598 >::from_register(self, 0)
599 }
600}
601impl ::core::default::Default for OtpcPwordlReg {
602 #[inline(always)]
603 fn default() -> OtpcPwordlReg {
604 <crate::RegValueT<OtpcPwordlReg_SPEC> as RegisterValue<_>>::new(0)
605 }
606}
607
608#[doc(hidden)]
609#[derive(Copy, Clone, Eq, PartialEq)]
610pub struct OtpcStatReg_SPEC;
611impl crate::sealed::RegSpec for OtpcStatReg_SPEC {
612 type DataType = u32;
613}
614
615#[doc = "Status register"]
616pub type OtpcStatReg = crate::RegValueT<OtpcStatReg_SPEC>;
617
618impl OtpcStatReg {
619 #[doc = "It contains the \"live\" value of the number of (32 bits) words that remain to be processed by the controller."]
620 #[inline(always)]
621 pub fn otpc_stat_nwords(
622 self,
623 ) -> crate::common::RegisterField<16, 0x3fff, 1, 0, u16, u16, OtpcStatReg_SPEC, crate::common::R>
624 {
625 crate::common::RegisterField::<16,0x3fff,1,0,u16,u16,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
626 }
627
628 #[doc = "Indicates the number of words which contained in the fifo of the controller."]
629 #[inline(always)]
630 pub fn otpc_stat_fwords(
631 self,
632 ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, OtpcStatReg_SPEC, crate::common::R>
633 {
634 crate::common::RegisterField::<8,0xf,1,0,u8,u8,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
635 }
636
637 #[doc = "Indicates that during a normal reading (MREAD or AREAD) was reported a double error by the SECDED logic. That means that the data are corrupted.\n0 - The read data are considered as correct.\n1- The SECDED logic detects a double error.\nThis bit can be cleared only with a write with \'1\'."]
638 #[inline(always)]
639 pub fn otpc_stat_rerror(
640 self,
641 ) -> crate::common::RegisterFieldBool<7, 1, 0, OtpcStatReg_SPEC, crate::common::RW> {
642 crate::common::RegisterFieldBool::<7,1,0,OtpcStatReg_SPEC,crate::common::RW>::from_register(self,0)
643 }
644
645 #[doc = "Should be used to monitor the progress of the AREAD and APROG modes.\n0 - One of the APROG or AREAD mode is selected. The controller is busy.\n1 - The controller is not in an active AREAD or APROG mode."]
646 #[inline(always)]
647 pub fn otpc_stat_ardy(
648 self,
649 ) -> crate::common::RegisterFieldBool<6, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
650 crate::common::RegisterFieldBool::<6,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
651 }
652
653 #[doc = "Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY = 1).\n0 - The test sequence ends with no error.\n1 - The test sequence has failed."]
654 #[inline(always)]
655 pub fn otpc_stat_terror(
656 self,
657 ) -> crate::common::RegisterFieldBool<5, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
658 crate::common::RegisterFieldBool::<5,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
659 }
660
661 #[doc = "Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes.\n0 - The controller is busy. One of the test modes is in progress.\n1 - There is no active test mode."]
662 #[inline(always)]
663 pub fn otpc_stat_trdy(
664 self,
665 ) -> crate::common::RegisterFieldBool<4, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
666 crate::common::RegisterFieldBool::<4,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
667 }
668
669 #[doc = "Indicates that the programming sequence has been avoided during a programming request, due to that the word that should be programmed is equal to zero.\n0 - At least one bit has been programmed into the OTP.\n1 - The programming has not been performed. All the bits of the word that should be programmed are equal to zero.\nWhen the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more of words that have been processed are equal to zero."]
670 #[inline(always)]
671 pub fn otpc_stat_pzero(
672 self,
673 ) -> crate::common::RegisterFieldBool<3, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
674 crate::common::RegisterFieldBool::<3,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
675 }
676
677 #[doc = "Indicates that a correctable error has been occurred during the word programming process.\n0 - There is no correctable error in the word-programming process.\n1 - The process of word - programming reported a correctable error.\nThe correctable error occurs when exactly one bit in an OTP position cannot take the required value. This is not a critical failure in the programming process. The data can still be retrieved correctly by the OTP memory, due to that the error correcting algorithm can repair the corrupted bit.\nWhen the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more words had a correctable error."]
678 #[inline(always)]
679 pub fn otpc_stat_perr_cor(
680 self,
681 ) -> crate::common::RegisterFieldBool<2, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
682 crate::common::RegisterFieldBool::<2,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
683 }
684
685 #[doc = "Indicates that an uncorrectable error has been occurred during the word programming process.\n0 - There is no uncorrectable error in the word-programming process.\n1 - The process of word-programming failed due to an uncorrectable error.\nAn uncorrectable error is considered when two or more of the bits in an OTP position cannot take the required values. This is a critical failure in the programming process, which means that the data cannot corrected by the single error correcting algorithm.\nWhen the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY = 1).\nDuring APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates if the programming was failed or ended successfully."]
686 #[inline(always)]
687 pub fn otpc_stat_perr_unc(
688 self,
689 ) -> crate::common::RegisterFieldBool<1, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
690 crate::common::RegisterFieldBool::<1,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
691 }
692
693 #[doc = "Indicates the state of a bit-programming process.\n0 - The controller is busy. A bit-programming is in progress\n1 - The logic which performs bit-programming is idle.\nWhen the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request.\nDuring APROG mode, the value of this field it is normal to changing periodically."]
694 #[inline(always)]
695 pub fn otpc_stat_prdy(
696 self,
697 ) -> crate::common::RegisterFieldBool<0, 1, 0, OtpcStatReg_SPEC, crate::common::R> {
698 crate::common::RegisterFieldBool::<0,1,0,OtpcStatReg_SPEC,crate::common::R>::from_register(self,0)
699 }
700}
701impl ::core::default::Default for OtpcStatReg {
702 #[inline(always)]
703 fn default() -> OtpcStatReg {
704 <crate::RegValueT<OtpcStatReg_SPEC> as RegisterValue<_>>::new(81)
705 }
706}
707
708#[doc(hidden)]
709#[derive(Copy, Clone, Eq, PartialEq)]
710pub struct OtpcTim1Reg_SPEC;
711impl crate::sealed::RegSpec for OtpcTim1Reg_SPEC {
712 type DataType = u32;
713}
714
715#[doc = "Various timing parameters of the OTP cell."]
716pub type OtpcTim1Reg = crate::RegValueT<OtpcTim1Reg_SPEC>;
717
718impl OtpcTim1Reg {
719 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 25ns."]
720 #[inline(always)]
721 pub fn otpc_tim1_cc_t_25ns(
722 self,
723 ) -> crate::common::RegisterFieldBool<31, 1, 0, OtpcTim1Reg_SPEC, crate::common::RW> {
724 crate::common::RegisterFieldBool::<31,1,0,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
725 }
726
727 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 200ns."]
728 #[inline(always)]
729 pub fn otpc_tim1_cc_t_200ns(
730 self,
731 ) -> crate::common::RegisterField<27, 0xf, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
732 {
733 crate::common::RegisterField::<27,0xf,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
734 }
735
736 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 500ns"]
737 #[inline(always)]
738 pub fn otpc_tim1_cc_t_500ns(
739 self,
740 ) -> crate::common::RegisterField<22, 0x1f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
741 {
742 crate::common::RegisterField::<22,0x1f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
743 }
744
745 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 1us."]
746 #[inline(always)]
747 pub fn otpc_tim1_cc_t_1us(
748 self,
749 ) -> crate::common::RegisterField<16, 0x3f, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
750 {
751 crate::common::RegisterField::<16,0x3f,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
752 }
753
754 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval that is\n- at least higher than 4.8us\n- and lower than 5.2 us\nIt is preferred the programmed value to give a time interval equal to 5us.\nIt defines the duration of the programming pulse for every bit that written in the OTP cell."]
755 #[inline(always)]
756 pub fn otpc_tim1_cc_t_pw(
757 self,
758 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
759 {
760 crate::common::RegisterField::<8,0xff,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
761 }
762
763 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval at least higher than 2us.It is used as a wait time each time where the OTP cell is enabled."]
764 #[inline(always)]
765 pub fn otpc_tim1_cc_t_cadx(
766 self,
767 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, OtpcTim1Reg_SPEC, crate::common::RW>
768 {
769 crate::common::RegisterField::<0,0xff,1,0,u8,u8,OtpcTim1Reg_SPEC,crate::common::RW>::from_register(self,0)
770 }
771}
772impl ::core::default::Default for OtpcTim1Reg {
773 #[inline(always)]
774 fn default() -> OtpcTim1Reg {
775 <crate::RegValueT<OtpcTim1Reg_SPEC> as RegisterValue<_>>::new(437276448)
776 }
777}
778
779#[doc(hidden)]
780#[derive(Copy, Clone, Eq, PartialEq)]
781pub struct OtpcTim2Reg_SPEC;
782impl crate::sealed::RegSpec for OtpcTim2Reg_SPEC {
783 type DataType = u32;
784}
785
786#[doc = "Various timing parameters of the OTP cell."]
787pub type OtpcTim2Reg = crate::RegValueT<OtpcTim2Reg_SPEC>;
788
789impl OtpcTim2Reg {
790 #[doc = "This bit has meaning only when the OTPC_TIM1_CC_T_25NS = 1, otherwise has no functionality. \n0 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is one clock cycle. This is also applicable if OTPC_TIM1_CC_T_25NS = 0.\n1 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is two clock cycles. The controller adds one extra wait state in the AHB access , if it is required, in order to achieves this constraint. This setting is applicable only if OTPC_TIM1_CC_T_25NS = 1."]
791 #[inline(always)]
792 pub fn otpc_tim2_rdenl_prot(
793 self,
794 ) -> crate::common::RegisterFieldBool<23, 1, 0, OtpcTim2Reg_SPEC, crate::common::RW> {
795 crate::common::RegisterFieldBool::<23,1,0,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
796 }
797
798 #[doc = "The number of hclk_c clock periods (minus one) that give a time interval between 100ns and 200ns. This time interval is used for the reading of the contents of the OTP cell during the TBLANK mode."]
799 #[inline(always)]
800 pub fn otpc_tim2_cc_t_bchk(
801 self,
802 ) -> crate::common::RegisterField<16, 0x7f, 1, 0, u8, u8, OtpcTim2Reg_SPEC, crate::common::RW>
803 {
804 crate::common::RegisterField::<16,0x7f,1,0,u8,u8,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
805 }
806
807 #[doc = "This register controls a power saving feature, which is applicable only in MREAD mode. The controller monitors the accesses in the OTP cell. If there is no access for more than OTPC_TIM2_CC_STBY_THR hclk_c clock cycles, the OTP cell goes to the standby while the controller itself remains in the MREAD mode. The OTP cell will be enabled again when will be applied a new read request. The enabling of the OTP cell has a cost of 2us (OTPC_TIM1_CC_T_CADX hclk_c clock cycles).\nWhen OTPC_TIM2_CC_STBY_THR = 0 the power saving feature is disabled and the OTP cell remains active while the controller is in MREAD mode."]
808 #[inline(always)]
809 pub fn otpc_tim2_cc_stby_thr(
810 self,
811 ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, OtpcTim2Reg_SPEC, crate::common::RW>
812 {
813 crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,OtpcTim2Reg_SPEC,crate::common::RW>::from_register(self,0)
814 }
815}
816impl ::core::default::Default for OtpcTim2Reg {
817 #[inline(always)]
818 fn default() -> OtpcTim2Reg {
819 <crate::RegValueT<OtpcTim2Reg_SPEC> as RegisterValue<_>>::new(65536)
820 }
821}