#[doc = "Register `QDEC_CLOCKDIV_REG` reader"]
pub struct R(crate::R<QDEC_CLOCKDIV_REG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<QDEC_CLOCKDIV_REG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<QDEC_CLOCKDIV_REG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<QDEC_CLOCKDIV_REG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `QDEC_CLOCKDIV_REG` writer"]
pub struct W(crate::W<QDEC_CLOCKDIV_REG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<QDEC_CLOCKDIV_REG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<QDEC_CLOCKDIV_REG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<QDEC_CLOCKDIV_REG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `QDEC_PRESCALER_EN` reader - 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2"]
pub struct QDEC_PRESCALER_EN_R(crate::FieldReader<bool, bool>);
impl QDEC_PRESCALER_EN_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
QDEC_PRESCALER_EN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for QDEC_PRESCALER_EN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `QDEC_PRESCALER_EN` writer - 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2"]
pub struct QDEC_PRESCALER_EN_W<'a> {
w: &'a mut W,
}
impl<'a> QDEC_PRESCALER_EN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 10)) | ((value as u16 & 1) << 10);
self.w
}
}
#[doc = "Field `QDEC_CLOCKDIV` reader - Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK"]
pub struct QDEC_CLOCKDIV_R(crate::FieldReader<u16, u16>);
impl QDEC_CLOCKDIV_R {
#[inline(always)]
pub(crate) fn new(bits: u16) -> Self {
QDEC_CLOCKDIV_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for QDEC_CLOCKDIV_R {
type Target = crate::FieldReader<u16, u16>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `QDEC_CLOCKDIV` writer - Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK"]
pub struct QDEC_CLOCKDIV_W<'a> {
w: &'a mut W,
}
impl<'a> QDEC_CLOCKDIV_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03ff) | (value as u16 & 0x03ff);
self.w
}
}
impl R {
#[doc = "Bit 10 - 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2"]
#[inline(always)]
pub fn qdec_prescaler_en(&self) -> QDEC_PRESCALER_EN_R {
QDEC_PRESCALER_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 0:9 - Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK"]
#[inline(always)]
pub fn qdec_clockdiv(&self) -> QDEC_CLOCKDIV_R {
QDEC_CLOCKDIV_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bit 10 - 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2"]
#[inline(always)]
pub fn qdec_prescaler_en(&mut self) -> QDEC_PRESCALER_EN_W {
QDEC_PRESCALER_EN_W { w: self }
}
#[doc = "Bits 0:9 - Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK"]
#[inline(always)]
pub fn qdec_clockdiv(&mut self) -> QDEC_CLOCKDIV_W {
QDEC_CLOCKDIV_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Clock divider register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qdec_clockdiv_reg](index.html) module"]
pub struct QDEC_CLOCKDIV_REG_SPEC;
impl crate::RegisterSpec for QDEC_CLOCKDIV_REG_SPEC {
type Ux = u16;
}
#[doc = "`read()` method returns [qdec_clockdiv_reg::R](R) reader structure"]
impl crate::Readable for QDEC_CLOCKDIV_REG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [qdec_clockdiv_reg::W](W) writer structure"]
impl crate::Writable for QDEC_CLOCKDIV_REG_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets QDEC_CLOCKDIV_REG to value 0x03e7"]
impl crate::Resettable for QDEC_CLOCKDIV_REG_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0x03e7
}
}