da14531_pac/
gpreg.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:44:12 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"GPREG registers"]
28unsafe impl ::core::marker::Send for super::Gpreg {}
29unsafe impl ::core::marker::Sync for super::Gpreg {}
30impl super::Gpreg {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "BLE FINECNT sampled value while in deep sleep state."]
38    #[inline(always)]
39    pub const fn ble_timer_reg(
40        &self,
41    ) -> &'static crate::common::Reg<self::BleTimerReg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::BleTimerReg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(10usize),
45            )
46        }
47    }
48
49    #[doc = "Various debug information register."]
50    #[inline(always)]
51    pub const fn debug_reg(
52        &self,
53    ) -> &'static crate::common::Reg<self::DebugReg_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::DebugReg_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "General purpose system control register."]
62    #[inline(always)]
63    pub const fn gp_control_reg(
64        &self,
65    ) -> &'static crate::common::Reg<self::GpControlReg_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::GpControlReg_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "General purpose system status register."]
74    #[inline(always)]
75    pub const fn gp_status_reg(
76        &self,
77    ) -> &'static crate::common::Reg<self::GpStatusReg_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::GpStatusReg_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(6usize),
81            )
82        }
83    }
84
85    #[inline(always)]
86    pub const fn mem_ctrl_reg(
87        &self,
88    ) -> &'static crate::common::Reg<self::MemCtrlReg_SPEC, crate::common::RW> {
89        unsafe {
90            crate::common::Reg::<self::MemCtrlReg_SPEC, crate::common::RW>::from_ptr(
91                self._svd2pac_as_ptr().add(12usize),
92            )
93        }
94    }
95
96    #[doc = "Controls unfreezing of various timers/counters."]
97    #[inline(always)]
98    pub const fn reset_freeze_reg(
99        &self,
100    ) -> &'static crate::common::Reg<self::ResetFreezeReg_SPEC, crate::common::RW> {
101        unsafe {
102            crate::common::Reg::<self::ResetFreezeReg_SPEC, crate::common::RW>::from_ptr(
103                self._svd2pac_as_ptr().add(2usize),
104            )
105        }
106    }
107
108    #[doc = "Controls freezing of various timers/counters."]
109    #[inline(always)]
110    pub const fn set_freeze_reg(
111        &self,
112    ) -> &'static crate::common::Reg<self::SetFreezeReg_SPEC, crate::common::RW> {
113        unsafe {
114            crate::common::Reg::<self::SetFreezeReg_SPEC, crate::common::RW>::from_ptr(
115                self._svd2pac_as_ptr().add(0usize),
116            )
117        }
118    }
119}
120#[doc(hidden)]
121#[derive(Copy, Clone, Eq, PartialEq)]
122pub struct BleTimerReg_SPEC;
123impl crate::sealed::RegSpec for BleTimerReg_SPEC {
124    type DataType = u16;
125}
126
127#[doc = "BLE FINECNT sampled value while in deep sleep state."]
128pub type BleTimerReg = crate::RegValueT<BleTimerReg_SPEC>;
129
130impl BleTimerReg {
131    #[doc = "Operation depends on GP_CONTROL_REG->BLE_TIMER_DATA_CTRL.\nIf BLE_TIMER_DATA_CTRL = 0 then:\nThis register is located at the Always On Power Domain and it holds the automatically sampled value of the BLE FINECNT timer\nThe HW automatically samples the value into this register during the sequence of \"BLE Sleep On\" and restores automatically the value during the BLE Wake up sequence.\nThe Software may read and modify the value while the BLE is in Sleep state. While the BLE is awake, the value of the register has no meaning, while changing the value by writing another one will have no effect in the operation of the BLE core.\nThere is a constraint when the SW performs an write-read sequence where it has to inject a one cycle delay in between (e.g. write-NOP-read) in order to read back the correct value.\nIf BLE_TIMER_DATA_CTRL is non 0 then write operations have the same effect as when BLE_TIMER_DATA_CTRL=0, while for read operations:\nBLE_TIMER_DATA_CTRL= 1: then reading BLE_TIMER_REG returns \"deepsldur\\[9:0\\]\".\nBLE_TIMER_DATA_CTRL= 2: then reading BLE_TIMER_REG returns \"deepsltime_samp\\[9:0\\]\".\nBLE_TIMER_DATA_CTRL= 3: then reading BLE_TIMER_REG returns \"{deep_sleep_stat_monitor, deepsltime_samp\\[18:10\\]}.\n."]
132    #[inline(always)]
133    pub fn ble_timer_data(
134        self,
135    ) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, BleTimerReg_SPEC, crate::common::RW>
136    {
137        crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,BleTimerReg_SPEC,crate::common::RW>::from_register(self,0)
138    }
139}
140impl ::core::default::Default for BleTimerReg {
141    #[inline(always)]
142    fn default() -> BleTimerReg {
143        <crate::RegValueT<BleTimerReg_SPEC> as RegisterValue<_>>::new(0)
144    }
145}
146
147#[doc(hidden)]
148#[derive(Copy, Clone, Eq, PartialEq)]
149pub struct DebugReg_SPEC;
150impl crate::sealed::RegSpec for DebugReg_SPEC {
151    type DataType = u16;
152}
153
154#[doc = "Various debug information register."]
155pub type DebugReg = crate::RegValueT<DebugReg_SPEC>;
156
157impl DebugReg {
158    #[doc = "Default \'1\', freezing of the on-chip timers is enabled when the Cortex-M0Plus is halted in DEBUG State.\nIf \'0\', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0Plus is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0Plus is halted in DEBUG State."]
159    #[inline(always)]
160    pub fn debugs_freeze_en(
161        self,
162    ) -> crate::common::RegisterFieldBool<0, 1, 0, DebugReg_SPEC, crate::common::RW> {
163        crate::common::RegisterFieldBool::<0, 1, 0, DebugReg_SPEC, crate::common::RW>::from_register(
164            self, 0,
165        )
166    }
167}
168impl ::core::default::Default for DebugReg {
169    #[inline(always)]
170    fn default() -> DebugReg {
171        <crate::RegValueT<DebugReg_SPEC> as RegisterValue<_>>::new(1)
172    }
173}
174
175#[doc(hidden)]
176#[derive(Copy, Clone, Eq, PartialEq)]
177pub struct GpControlReg_SPEC;
178impl crate::sealed::RegSpec for GpControlReg_SPEC {
179    type DataType = u16;
180}
181
182#[doc = "General purpose system control register."]
183pub type GpControlReg = crate::RegValueT<GpControlReg_SPEC>;
184
185impl GpControlReg {
186    #[doc = "Refer to BLE_TIMER_REG."]
187    #[inline(always)]
188    pub fn ble_timer_data_ctrl(
189        self,
190    ) -> crate::common::RegisterField<5, 0x3, 1, 0, u8, u8, GpControlReg_SPEC, crate::common::RW>
191    {
192        crate::common::RegisterField::<5,0x3,1,0,u8,u8,GpControlReg_SPEC,crate::common::RW>::from_register(self,0)
193    }
194
195    #[doc = "Controls the CPU DMA system bus priority:\nIf \'0\', the CPU has highest priority.\nIf \'1\', the DMA has highest priority."]
196    #[inline(always)]
197    pub fn cpu_dma_bus_prio(
198        self,
199    ) -> crate::common::RegisterFieldBool<4, 1, 0, GpControlReg_SPEC, crate::common::RW> {
200        crate::common::RegisterFieldBool::<4,1,0,GpControlReg_SPEC,crate::common::RW>::from_register(self,0)
201    }
202
203    #[doc = "The current value of the BLE_WAKEUP_LP_IRQ interrupt request."]
204    #[inline(always)]
205    pub fn ble_wakeup_lp_irq(
206        self,
207    ) -> crate::common::RegisterFieldBool<2, 1, 0, GpControlReg_SPEC, crate::common::R> {
208        crate::common::RegisterFieldBool::<2,1,0,GpControlReg_SPEC,crate::common::R>::from_register(self,0)
209    }
210
211    #[doc = "If \'1\', the BLE wakes up. Must be kept high at least for 1 low power clock period. \nIf the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles."]
212    #[inline(always)]
213    pub fn ble_wakeup_req(
214        self,
215    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpControlReg_SPEC, crate::common::RW> {
216        crate::common::RegisterFieldBool::<0,1,0,GpControlReg_SPEC,crate::common::RW>::from_register(self,0)
217    }
218}
219impl ::core::default::Default for GpControlReg {
220    #[inline(always)]
221    fn default() -> GpControlReg {
222        <crate::RegValueT<GpControlReg_SPEC> as RegisterValue<_>>::new(0)
223    }
224}
225
226#[doc(hidden)]
227#[derive(Copy, Clone, Eq, PartialEq)]
228pub struct GpStatusReg_SPEC;
229impl crate::sealed::RegSpec for GpStatusReg_SPEC {
230    type DataType = u16;
231}
232
233#[doc = "General purpose system status register."]
234pub type GpStatusReg = crate::RegValueT<GpStatusReg_SPEC>;
235
236impl GpStatusReg {
237    #[doc = "If \'1\', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured."]
238    #[inline(always)]
239    pub fn cal_phase(
240        self,
241    ) -> crate::common::RegisterFieldBool<0, 1, 0, GpStatusReg_SPEC, crate::common::RW> {
242        crate::common::RegisterFieldBool::<0,1,0,GpStatusReg_SPEC,crate::common::RW>::from_register(self,0)
243    }
244}
245impl ::core::default::Default for GpStatusReg {
246    #[inline(always)]
247    fn default() -> GpStatusReg {
248        <crate::RegValueT<GpStatusReg_SPEC> as RegisterValue<_>>::new(0)
249    }
250}
251
252#[doc(hidden)]
253#[derive(Copy, Clone, Eq, PartialEq)]
254pub struct MemCtrlReg_SPEC;
255impl crate::sealed::RegSpec for MemCtrlReg_SPEC {
256    type DataType = u16;
257}
258
259pub type MemCtrlReg = crate::RegValueT<MemCtrlReg_SPEC>;
260
261impl MemCtrlReg {
262    #[inline(always)]
263    pub fn arb2_ahb2_wr_buff(
264        self,
265    ) -> crate::common::RegisterFieldBool<11, 1, 0, MemCtrlReg_SPEC, crate::common::R> {
266        crate::common::RegisterFieldBool::<11,1,0,MemCtrlReg_SPEC,crate::common::R>::from_register(self,0)
267    }
268
269    #[inline(always)]
270    pub fn arb2_ahb_wr_buff(
271        self,
272    ) -> crate::common::RegisterFieldBool<10, 1, 0, MemCtrlReg_SPEC, crate::common::R> {
273        crate::common::RegisterFieldBool::<10,1,0,MemCtrlReg_SPEC,crate::common::R>::from_register(self,0)
274    }
275
276    #[inline(always)]
277    pub fn arb1_ahb2_wr_buff(
278        self,
279    ) -> crate::common::RegisterFieldBool<9, 1, 0, MemCtrlReg_SPEC, crate::common::R> {
280        crate::common::RegisterFieldBool::<9,1,0,MemCtrlReg_SPEC,crate::common::R>::from_register(self,0)
281    }
282
283    #[inline(always)]
284    pub fn arb1_ahb_wr_buff(
285        self,
286    ) -> crate::common::RegisterFieldBool<8, 1, 0, MemCtrlReg_SPEC, crate::common::R> {
287        crate::common::RegisterFieldBool::<8,1,0,MemCtrlReg_SPEC,crate::common::R>::from_register(self,0)
288    }
289
290    #[inline(always)]
291    pub fn ram_margin(
292        self,
293    ) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, MemCtrlReg_SPEC, crate::common::RW>
294    {
295        crate::common::RegisterField::<6,0x3,1,0,u8,u8,MemCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
296    }
297
298    #[inline(always)]
299    pub fn ram_dst(
300        self,
301    ) -> crate::common::RegisterFieldBool<5, 1, 0, MemCtrlReg_SPEC, crate::common::RW> {
302        crate::common::RegisterFieldBool::<5,1,0,MemCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
303    }
304
305    #[inline(always)]
306    pub fn rom_margin_en(
307        self,
308    ) -> crate::common::RegisterFieldBool<4, 1, 0, MemCtrlReg_SPEC, crate::common::RW> {
309        crate::common::RegisterFieldBool::<4,1,0,MemCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
310    }
311
312    #[inline(always)]
313    pub fn rom_margin_ctrl(
314        self,
315    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, MemCtrlReg_SPEC, crate::common::RW>
316    {
317        crate::common::RegisterField::<0,0xf,1,0,u8,u8,MemCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
318    }
319}
320impl ::core::default::Default for MemCtrlReg {
321    #[inline(always)]
322    fn default() -> MemCtrlReg {
323        <crate::RegValueT<MemCtrlReg_SPEC> as RegisterValue<_>>::new(128)
324    }
325}
326
327#[doc(hidden)]
328#[derive(Copy, Clone, Eq, PartialEq)]
329pub struct ResetFreezeReg_SPEC;
330impl crate::sealed::RegSpec for ResetFreezeReg_SPEC {
331    type DataType = u16;
332}
333
334#[doc = "Controls unfreezing of various timers/counters."]
335pub type ResetFreezeReg = crate::RegValueT<ResetFreezeReg_SPEC>;
336
337impl ResetFreezeReg {
338    #[doc = "If \'1\', the DMA continues, \'0\' is discarded."]
339    #[inline(always)]
340    pub fn frz_dma(
341        self,
342    ) -> crate::common::RegisterFieldBool<4, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
343        crate::common::RegisterFieldBool::<4,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
344    }
345
346    #[doc = "If \'1\', the watchdog timer continues, \'0\' is discarded."]
347    #[inline(always)]
348    pub fn frz_wdog(
349        self,
350    ) -> crate::common::RegisterFieldBool<3, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
351        crate::common::RegisterFieldBool::<3,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
352    }
353
354    #[doc = "If \'1\', the the BLE master clock continues, \'0\' is discarded."]
355    #[inline(always)]
356    pub fn frz_bletim(
357        self,
358    ) -> crate::common::RegisterFieldBool<2, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
359        crate::common::RegisterFieldBool::<2,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
360    }
361
362    #[doc = "If \'1\', the SW Timer (TIMER0) continues, \'0\' is discarded."]
363    #[inline(always)]
364    pub fn frz_swtim(
365        self,
366    ) -> crate::common::RegisterFieldBool<1, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
367        crate::common::RegisterFieldBool::<1,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
368    }
369
370    #[doc = "If \'1\', the Wake Up Timer continues, \'0\' is discarded."]
371    #[inline(always)]
372    pub fn frz_wkuptim(
373        self,
374    ) -> crate::common::RegisterFieldBool<0, 1, 0, ResetFreezeReg_SPEC, crate::common::RW> {
375        crate::common::RegisterFieldBool::<0,1,0,ResetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
376    }
377}
378impl ::core::default::Default for ResetFreezeReg {
379    #[inline(always)]
380    fn default() -> ResetFreezeReg {
381        <crate::RegValueT<ResetFreezeReg_SPEC> as RegisterValue<_>>::new(0)
382    }
383}
384
385#[doc(hidden)]
386#[derive(Copy, Clone, Eq, PartialEq)]
387pub struct SetFreezeReg_SPEC;
388impl crate::sealed::RegSpec for SetFreezeReg_SPEC {
389    type DataType = u16;
390}
391
392#[doc = "Controls freezing of various timers/counters."]
393pub type SetFreezeReg = crate::RegValueT<SetFreezeReg_SPEC>;
394
395impl SetFreezeReg {
396    #[doc = "If \'1\', the DMA is frozen, \'0\' is discarded."]
397    #[inline(always)]
398    pub fn frz_dma(
399        self,
400    ) -> crate::common::RegisterFieldBool<4, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
401        crate::common::RegisterFieldBool::<4,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
402    }
403
404    #[doc = "If \'1\', the watchdog timer is frozen, \'0\' is discarded. WATCHDOG_CTRL_REG\\[NMI_RST\\] must be \'0\' to allow the freeze function."]
405    #[inline(always)]
406    pub fn frz_wdog(
407        self,
408    ) -> crate::common::RegisterFieldBool<3, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
409        crate::common::RegisterFieldBool::<3,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
410    }
411
412    #[doc = "If \'1\', the BLE master clock is frozen, \'0\' is discarded."]
413    #[inline(always)]
414    pub fn frz_bletim(
415        self,
416    ) -> crate::common::RegisterFieldBool<2, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
417        crate::common::RegisterFieldBool::<2,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
418    }
419
420    #[doc = "If \'1\', the SW Timer (TIMER0) is frozen, \'0\' is discarded."]
421    #[inline(always)]
422    pub fn frz_swtim(
423        self,
424    ) -> crate::common::RegisterFieldBool<1, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
425        crate::common::RegisterFieldBool::<1,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
426    }
427
428    #[doc = "If \'1\', the Wake Up Timer is frozen, \'0\' is discarded."]
429    #[inline(always)]
430    pub fn frz_wkuptim(
431        self,
432    ) -> crate::common::RegisterFieldBool<0, 1, 0, SetFreezeReg_SPEC, crate::common::RW> {
433        crate::common::RegisterFieldBool::<0,1,0,SetFreezeReg_SPEC,crate::common::RW>::from_register(self,0)
434    }
435}
436impl ::core::default::Default for SetFreezeReg {
437    #[inline(always)]
438    fn default() -> SetFreezeReg {
439        <crate::RegValueT<SetFreezeReg_SPEC> as RegisterValue<_>>::new(0)
440    }
441}
da14531_pac/gpreg.rs

da14531_pac/
gpreg.rs
