d1_pac/usb1/hci_controller_phy_interface/
phy_control.rs

1#[doc = "Register `phy_control` reader"]
2pub type R = crate::R<PHY_CONTROL_SPEC>;
3#[doc = "Register `phy_control` writer"]
4pub type W = crate::W<PHY_CONTROL_SPEC>;
5#[doc = "Field `vc_clk` reader - vc_clk"]
6pub type VC_CLK_R = crate::BitReader;
7#[doc = "Field `vc_clk` writer - vc_clk"]
8pub type VC_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `siddq` reader - "]
10pub type SIDDQ_R = crate::BitReader<SIDDQ_A>;
11#[doc = "\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum SIDDQ_A {
14    #[doc = "1: Write 1 to disable phy"]
15    DISABLE = 1,
16    #[doc = "0: Write 0 to enable phy"]
17    ENABLE = 0,
18}
19impl From<SIDDQ_A> for bool {
20    #[inline(always)]
21    fn from(variant: SIDDQ_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl SIDDQ_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> SIDDQ_A {
29        match self.bits {
30            true => SIDDQ_A::DISABLE,
31            false => SIDDQ_A::ENABLE,
32        }
33    }
34    #[doc = "Write 1 to disable phy"]
35    #[inline(always)]
36    pub fn is_disable(&self) -> bool {
37        *self == SIDDQ_A::DISABLE
38    }
39    #[doc = "Write 0 to enable phy"]
40    #[inline(always)]
41    pub fn is_enable(&self) -> bool {
42        *self == SIDDQ_A::ENABLE
43    }
44}
45#[doc = "Field `siddq` writer - "]
46pub type SIDDQ_W<'a, REG> = crate::BitWriter<'a, REG, SIDDQ_A>;
47impl<'a, REG> SIDDQ_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Write 1 to disable phy"]
52    #[inline(always)]
53    pub fn disable(self) -> &'a mut crate::W<REG> {
54        self.variant(SIDDQ_A::DISABLE)
55    }
56    #[doc = "Write 0 to enable phy"]
57    #[inline(always)]
58    pub fn enable(self) -> &'a mut crate::W<REG> {
59        self.variant(SIDDQ_A::ENABLE)
60    }
61}
62#[doc = "Field `vc_di` reader - vc_di"]
63pub type VC_DI_R = crate::BitReader;
64#[doc = "Field `vc_di` writer - vc_di"]
65pub type VC_DI_W<'a, REG> = crate::BitWriter<'a, REG>;
66#[doc = "Field `vc_addr` reader - vc_addr"]
67pub type VC_ADDR_R = crate::FieldReader;
68#[doc = "Field `vc_addr` writer - vc_addr"]
69pub type VC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
70#[doc = "Field `bist_en_a` reader - "]
71pub type BIST_EN_A_R = crate::BitReader;
72#[doc = "Field `bist_en_a` writer - "]
73pub type BIST_EN_A_W<'a, REG> = crate::BitWriter<'a, REG>;
74impl R {
75    #[doc = "Bit 0 - vc_clk"]
76    #[inline(always)]
77    pub fn vc_clk(&self) -> VC_CLK_R {
78        VC_CLK_R::new((self.bits & 1) != 0)
79    }
80    #[doc = "Bit 3"]
81    #[inline(always)]
82    pub fn siddq(&self) -> SIDDQ_R {
83        SIDDQ_R::new(((self.bits >> 3) & 1) != 0)
84    }
85    #[doc = "Bit 7 - vc_di"]
86    #[inline(always)]
87    pub fn vc_di(&self) -> VC_DI_R {
88        VC_DI_R::new(((self.bits >> 7) & 1) != 0)
89    }
90    #[doc = "Bits 8:15 - vc_addr"]
91    #[inline(always)]
92    pub fn vc_addr(&self) -> VC_ADDR_R {
93        VC_ADDR_R::new(((self.bits >> 8) & 0xff) as u8)
94    }
95    #[doc = "Bit 16"]
96    #[inline(always)]
97    pub fn bist_en_a(&self) -> BIST_EN_A_R {
98        BIST_EN_A_R::new(((self.bits >> 16) & 1) != 0)
99    }
100}
101impl W {
102    #[doc = "Bit 0 - vc_clk"]
103    #[inline(always)]
104    #[must_use]
105    pub fn vc_clk(&mut self) -> VC_CLK_W<PHY_CONTROL_SPEC> {
106        VC_CLK_W::new(self, 0)
107    }
108    #[doc = "Bit 3"]
109    #[inline(always)]
110    #[must_use]
111    pub fn siddq(&mut self) -> SIDDQ_W<PHY_CONTROL_SPEC> {
112        SIDDQ_W::new(self, 3)
113    }
114    #[doc = "Bit 7 - vc_di"]
115    #[inline(always)]
116    #[must_use]
117    pub fn vc_di(&mut self) -> VC_DI_W<PHY_CONTROL_SPEC> {
118        VC_DI_W::new(self, 7)
119    }
120    #[doc = "Bits 8:15 - vc_addr"]
121    #[inline(always)]
122    #[must_use]
123    pub fn vc_addr(&mut self) -> VC_ADDR_W<PHY_CONTROL_SPEC> {
124        VC_ADDR_W::new(self, 8)
125    }
126    #[doc = "Bit 16"]
127    #[inline(always)]
128    #[must_use]
129    pub fn bist_en_a(&mut self) -> BIST_EN_A_W<PHY_CONTROL_SPEC> {
130        BIST_EN_A_W::new(self, 16)
131    }
132    #[doc = r" Writes raw bits to the register."]
133    #[doc = r""]
134    #[doc = r" # Safety"]
135    #[doc = r""]
136    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
137    #[inline(always)]
138    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139        self.bits = bits;
140        self
141    }
142}
143#[doc = "PHY Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
144pub struct PHY_CONTROL_SPEC;
145impl crate::RegisterSpec for PHY_CONTROL_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [`phy_control::R`](R) reader structure"]
149impl crate::Readable for PHY_CONTROL_SPEC {}
150#[doc = "`write(|w| ..)` method takes [`phy_control::W`](W) writer structure"]
151impl crate::Writable for PHY_CONTROL_SPEC {
152    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
153    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
154}
155#[doc = "`reset()` method sets phy_control to value 0"]
156impl crate::Resettable for PHY_CONTROL_SPEC {
157    const RESET_VALUE: Self::Ux = 0;
158}
d1_pac/usb1/hci_controller_phy_interface/phy_control.rs

d1_pac/usb1/hci_controller_phy_interface/
phy_control.rs
