d1_pac/tcon_lcd0/
lcd_lvds_ana.rs

1#[doc = "Register `lcd_lvds_ana%s` reader"]
2pub type R = crate::R<LCD_LVDS_ANA_SPEC>;
3#[doc = "Register `lcd_lvds_ana%s` writer"]
4pub type W = crate::W<LCD_LVDS_ANA_SPEC>;
5#[doc = "Field `lvds_plr` reader - LVDS data channel \\[3:0\\] direction."]
6pub type LVDS_PLR_R = crate::FieldReader;
7#[doc = "Field `lvds_plr` writer - LVDS data channel \\[3:0\\] direction."]
8pub type LVDS_PLR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `lvds_plrc` reader - LVDS clock channel direction."]
10pub type LVDS_PLRC_R = crate::BitReader<LVDS_PLRC_A>;
11#[doc = "LVDS clock channel direction.\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum LVDS_PLRC_A {
14    #[doc = "0: Normal"]
15    NORMAL = 0,
16    #[doc = "1: Reverse"]
17    REVERSE = 1,
18}
19impl From<LVDS_PLRC_A> for bool {
20    #[inline(always)]
21    fn from(variant: LVDS_PLRC_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl LVDS_PLRC_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> LVDS_PLRC_A {
29        match self.bits {
30            false => LVDS_PLRC_A::NORMAL,
31            true => LVDS_PLRC_A::REVERSE,
32        }
33    }
34    #[doc = "Normal"]
35    #[inline(always)]
36    pub fn is_normal(&self) -> bool {
37        *self == LVDS_PLRC_A::NORMAL
38    }
39    #[doc = "Reverse"]
40    #[inline(always)]
41    pub fn is_reverse(&self) -> bool {
42        *self == LVDS_PLRC_A::REVERSE
43    }
44}
45#[doc = "Field `lvds_plrc` writer - LVDS clock channel direction."]
46pub type LVDS_PLRC_W<'a, REG> = crate::BitWriter<'a, REG, LVDS_PLRC_A>;
47impl<'a, REG> LVDS_PLRC_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Normal"]
52    #[inline(always)]
53    pub fn normal(self) -> &'a mut crate::W<REG> {
54        self.variant(LVDS_PLRC_A::NORMAL)
55    }
56    #[doc = "Reverse"]
57    #[inline(always)]
58    pub fn reverse(self) -> &'a mut crate::W<REG> {
59        self.variant(LVDS_PLRC_A::REVERSE)
60    }
61}
62#[doc = "Field `lvds_r` reader - Adjust current flowing through R of R to change the common signals amplitude."]
63pub type LVDS_R_R = crate::FieldReader<LVDS_R_A>;
64#[doc = "Adjust current flowing through R of R to change the common signals amplitude.\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum LVDS_R_A {
68    #[doc = "0: 0.925 V"]
69    _0_925_V = 0,
70    #[doc = "1: 0.950 V"]
71    _0_950_V = 1,
72    #[doc = "2: 0.975 V"]
73    _0_975_V = 2,
74    #[doc = "3: 1.000 V"]
75    _1_000_V = 3,
76    #[doc = "4: 1.025 V"]
77    _1_025_V = 4,
78    #[doc = "5: 1.050 V"]
79    _1_050_V = 5,
80    #[doc = "6: 1.075 V"]
81    _1_075_V = 6,
82    #[doc = "7: 1.100 V"]
83    _1_100_V = 7,
84}
85impl From<LVDS_R_A> for u8 {
86    #[inline(always)]
87    fn from(variant: LVDS_R_A) -> Self {
88        variant as _
89    }
90}
91impl crate::FieldSpec for LVDS_R_A {
92    type Ux = u8;
93}
94impl LVDS_R_R {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> LVDS_R_A {
98        match self.bits {
99            0 => LVDS_R_A::_0_925_V,
100            1 => LVDS_R_A::_0_950_V,
101            2 => LVDS_R_A::_0_975_V,
102            3 => LVDS_R_A::_1_000_V,
103            4 => LVDS_R_A::_1_025_V,
104            5 => LVDS_R_A::_1_050_V,
105            6 => LVDS_R_A::_1_075_V,
106            7 => LVDS_R_A::_1_100_V,
107            _ => unreachable!(),
108        }
109    }
110    #[doc = "0.925 V"]
111    #[inline(always)]
112    pub fn is_0_925_v(&self) -> bool {
113        *self == LVDS_R_A::_0_925_V
114    }
115    #[doc = "0.950 V"]
116    #[inline(always)]
117    pub fn is_0_950_v(&self) -> bool {
118        *self == LVDS_R_A::_0_950_V
119    }
120    #[doc = "0.975 V"]
121    #[inline(always)]
122    pub fn is_0_975_v(&self) -> bool {
123        *self == LVDS_R_A::_0_975_V
124    }
125    #[doc = "1.000 V"]
126    #[inline(always)]
127    pub fn is_1_000_v(&self) -> bool {
128        *self == LVDS_R_A::_1_000_V
129    }
130    #[doc = "1.025 V"]
131    #[inline(always)]
132    pub fn is_1_025_v(&self) -> bool {
133        *self == LVDS_R_A::_1_025_V
134    }
135    #[doc = "1.050 V"]
136    #[inline(always)]
137    pub fn is_1_050_v(&self) -> bool {
138        *self == LVDS_R_A::_1_050_V
139    }
140    #[doc = "1.075 V"]
141    #[inline(always)]
142    pub fn is_1_075_v(&self) -> bool {
143        *self == LVDS_R_A::_1_075_V
144    }
145    #[doc = "1.100 V"]
146    #[inline(always)]
147    pub fn is_1_100_v(&self) -> bool {
148        *self == LVDS_R_A::_1_100_V
149    }
150}
151#[doc = "Field `lvds_r` writer - Adjust current flowing through R of R to change the common signals amplitude."]
152pub type LVDS_R_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, LVDS_R_A>;
153impl<'a, REG> LVDS_R_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "0.925 V"]
159    #[inline(always)]
160    pub fn _0_925_v(self) -> &'a mut crate::W<REG> {
161        self.variant(LVDS_R_A::_0_925_V)
162    }
163    #[doc = "0.950 V"]
164    #[inline(always)]
165    pub fn _0_950_v(self) -> &'a mut crate::W<REG> {
166        self.variant(LVDS_R_A::_0_950_V)
167    }
168    #[doc = "0.975 V"]
169    #[inline(always)]
170    pub fn _0_975_v(self) -> &'a mut crate::W<REG> {
171        self.variant(LVDS_R_A::_0_975_V)
172    }
173    #[doc = "1.000 V"]
174    #[inline(always)]
175    pub fn _1_000_v(self) -> &'a mut crate::W<REG> {
176        self.variant(LVDS_R_A::_1_000_V)
177    }
178    #[doc = "1.025 V"]
179    #[inline(always)]
180    pub fn _1_025_v(self) -> &'a mut crate::W<REG> {
181        self.variant(LVDS_R_A::_1_025_V)
182    }
183    #[doc = "1.050 V"]
184    #[inline(always)]
185    pub fn _1_050_v(self) -> &'a mut crate::W<REG> {
186        self.variant(LVDS_R_A::_1_050_V)
187    }
188    #[doc = "1.075 V"]
189    #[inline(always)]
190    pub fn _1_075_v(self) -> &'a mut crate::W<REG> {
191        self.variant(LVDS_R_A::_1_075_V)
192    }
193    #[doc = "1.100 V"]
194    #[inline(always)]
195    pub fn _1_100_v(self) -> &'a mut crate::W<REG> {
196        self.variant(LVDS_R_A::_1_100_V)
197    }
198}
199#[doc = "Field `lvds_den` reader - Choose data output or PLL test clock output in LVDS_tx."]
200pub type LVDS_DEN_R = crate::FieldReader;
201#[doc = "Field `lvds_den` writer - Choose data output or PLL test clock output in LVDS_tx."]
202pub type LVDS_DEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
203#[doc = "Field `lvds_denc` reader - Choose data output or PLL test clock output in LVDS_tx."]
204pub type LVDS_DENC_R = crate::BitReader;
205#[doc = "Field `lvds_denc` writer - Choose data output or PLL test clock output in LVDS_tx."]
206pub type LVDS_DENC_W<'a, REG> = crate::BitWriter<'a, REG>;
207#[doc = "Field `lvds_c` reader - Adjust current flowing through Rload of Rx to change the differential signals amplitude."]
208pub type LVDS_C_R = crate::FieldReader<LVDS_C_A>;
209#[doc = "Adjust current flowing through Rload of Rx to change the differential signals amplitude.\n\nValue on reset: 0"]
210#[derive(Clone, Copy, Debug, PartialEq, Eq)]
211#[repr(u8)]
212pub enum LVDS_C_A {
213    #[doc = "0: 216 mV"]
214    _216MV = 0,
215    #[doc = "1: 252 mV"]
216    _252MV = 1,
217    #[doc = "2: 276 mV"]
218    _276MV = 2,
219    #[doc = "3: 312 mV"]
220    _312MV = 3,
221    #[doc = "4: 336 mV"]
222    _336MV = 4,
223    #[doc = "5: 372 mV"]
224    _372MV = 5,
225    #[doc = "6: 395 mV"]
226    _395MV = 6,
227    #[doc = "7: 432 mV"]
228    _432MV = 7,
229}
230impl From<LVDS_C_A> for u8 {
231    #[inline(always)]
232    fn from(variant: LVDS_C_A) -> Self {
233        variant as _
234    }
235}
236impl crate::FieldSpec for LVDS_C_A {
237    type Ux = u8;
238}
239impl LVDS_C_R {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub const fn variant(&self) -> LVDS_C_A {
243        match self.bits {
244            0 => LVDS_C_A::_216MV,
245            1 => LVDS_C_A::_252MV,
246            2 => LVDS_C_A::_276MV,
247            3 => LVDS_C_A::_312MV,
248            4 => LVDS_C_A::_336MV,
249            5 => LVDS_C_A::_372MV,
250            6 => LVDS_C_A::_395MV,
251            7 => LVDS_C_A::_432MV,
252            _ => unreachable!(),
253        }
254    }
255    #[doc = "216 mV"]
256    #[inline(always)]
257    pub fn is_216mv(&self) -> bool {
258        *self == LVDS_C_A::_216MV
259    }
260    #[doc = "252 mV"]
261    #[inline(always)]
262    pub fn is_252mv(&self) -> bool {
263        *self == LVDS_C_A::_252MV
264    }
265    #[doc = "276 mV"]
266    #[inline(always)]
267    pub fn is_276mv(&self) -> bool {
268        *self == LVDS_C_A::_276MV
269    }
270    #[doc = "312 mV"]
271    #[inline(always)]
272    pub fn is_312mv(&self) -> bool {
273        *self == LVDS_C_A::_312MV
274    }
275    #[doc = "336 mV"]
276    #[inline(always)]
277    pub fn is_336mv(&self) -> bool {
278        *self == LVDS_C_A::_336MV
279    }
280    #[doc = "372 mV"]
281    #[inline(always)]
282    pub fn is_372mv(&self) -> bool {
283        *self == LVDS_C_A::_372MV
284    }
285    #[doc = "395 mV"]
286    #[inline(always)]
287    pub fn is_395mv(&self) -> bool {
288        *self == LVDS_C_A::_395MV
289    }
290    #[doc = "432 mV"]
291    #[inline(always)]
292    pub fn is_432mv(&self) -> bool {
293        *self == LVDS_C_A::_432MV
294    }
295}
296#[doc = "Field `lvds_c` writer - Adjust current flowing through Rload of Rx to change the differential signals amplitude."]
297pub type LVDS_C_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, LVDS_C_A>;
298impl<'a, REG> LVDS_C_W<'a, REG>
299where
300    REG: crate::Writable + crate::RegisterSpec,
301    REG::Ux: From<u8>,
302{
303    #[doc = "216 mV"]
304    #[inline(always)]
305    pub fn _216mv(self) -> &'a mut crate::W<REG> {
306        self.variant(LVDS_C_A::_216MV)
307    }
308    #[doc = "252 mV"]
309    #[inline(always)]
310    pub fn _252mv(self) -> &'a mut crate::W<REG> {
311        self.variant(LVDS_C_A::_252MV)
312    }
313    #[doc = "276 mV"]
314    #[inline(always)]
315    pub fn _276mv(self) -> &'a mut crate::W<REG> {
316        self.variant(LVDS_C_A::_276MV)
317    }
318    #[doc = "312 mV"]
319    #[inline(always)]
320    pub fn _312mv(self) -> &'a mut crate::W<REG> {
321        self.variant(LVDS_C_A::_312MV)
322    }
323    #[doc = "336 mV"]
324    #[inline(always)]
325    pub fn _336mv(self) -> &'a mut crate::W<REG> {
326        self.variant(LVDS_C_A::_336MV)
327    }
328    #[doc = "372 mV"]
329    #[inline(always)]
330    pub fn _372mv(self) -> &'a mut crate::W<REG> {
331        self.variant(LVDS_C_A::_372MV)
332    }
333    #[doc = "395 mV"]
334    #[inline(always)]
335    pub fn _395mv(self) -> &'a mut crate::W<REG> {
336        self.variant(LVDS_C_A::_395MV)
337    }
338    #[doc = "432 mV"]
339    #[inline(always)]
340    pub fn _432mv(self) -> &'a mut crate::W<REG> {
341        self.variant(LVDS_C_A::_432MV)
342    }
343}
344#[doc = "Field `lvds_hpren_drv` reader - Enable data channel\\[3:0\\] drive"]
345pub type LVDS_HPREN_DRV_R = crate::FieldReader;
346#[doc = "Field `lvds_hpren_drv` writer - Enable data channel\\[3:0\\] drive"]
347pub type LVDS_HPREN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
348#[doc = "Field `lvds_hpren_drvc` reader - Enable clock channel drive"]
349pub type LVDS_HPREN_DRVC_R = crate::BitReader<LVDS_HPREN_DRVC_A>;
350#[doc = "Enable clock channel drive\n\nValue on reset: 0"]
351#[derive(Clone, Copy, Debug, PartialEq, Eq)]
352pub enum LVDS_HPREN_DRVC_A {
353    #[doc = "0: Disable"]
354    DISABLE = 0,
355    #[doc = "1: Enable"]
356    ENABLE = 1,
357}
358impl From<LVDS_HPREN_DRVC_A> for bool {
359    #[inline(always)]
360    fn from(variant: LVDS_HPREN_DRVC_A) -> Self {
361        variant as u8 != 0
362    }
363}
364impl LVDS_HPREN_DRVC_R {
365    #[doc = "Get enumerated values variant"]
366    #[inline(always)]
367    pub const fn variant(&self) -> LVDS_HPREN_DRVC_A {
368        match self.bits {
369            false => LVDS_HPREN_DRVC_A::DISABLE,
370            true => LVDS_HPREN_DRVC_A::ENABLE,
371        }
372    }
373    #[doc = "Disable"]
374    #[inline(always)]
375    pub fn is_disable(&self) -> bool {
376        *self == LVDS_HPREN_DRVC_A::DISABLE
377    }
378    #[doc = "Enable"]
379    #[inline(always)]
380    pub fn is_enable(&self) -> bool {
381        *self == LVDS_HPREN_DRVC_A::ENABLE
382    }
383}
384#[doc = "Field `lvds_hpren_drvc` writer - Enable clock channel drive"]
385pub type LVDS_HPREN_DRVC_W<'a, REG> = crate::BitWriter<'a, REG, LVDS_HPREN_DRVC_A>;
386impl<'a, REG> LVDS_HPREN_DRVC_W<'a, REG>
387where
388    REG: crate::Writable + crate::RegisterSpec,
389{
390    #[doc = "Disable"]
391    #[inline(always)]
392    pub fn disable(self) -> &'a mut crate::W<REG> {
393        self.variant(LVDS_HPREN_DRVC_A::DISABLE)
394    }
395    #[doc = "Enable"]
396    #[inline(always)]
397    pub fn enable(self) -> &'a mut crate::W<REG> {
398        self.variant(LVDS_HPREN_DRVC_A::ENABLE)
399    }
400}
401#[doc = "Field `en_24m` reader - Enable the 24M clock"]
402pub type EN_24M_R = crate::BitReader;
403#[doc = "Field `en_24m` writer - Enable the 24M clock"]
404pub type EN_24M_W<'a, REG> = crate::BitWriter<'a, REG>;
405#[doc = "Field `en_lvds` reader - Enable LVDS"]
406pub type EN_LVDS_R = crate::BitReader;
407#[doc = "Field `en_lvds` writer - Enable LVDS"]
408pub type EN_LVDS_W<'a, REG> = crate::BitWriter<'a, REG>;
409#[doc = "Field `lvds_en_mb` reader - Enable the bias circuit of the LVDS_Ana module."]
410pub type LVDS_EN_MB_R = crate::BitReader<LVDS_EN_MB_A>;
411#[doc = "Enable the bias circuit of the LVDS_Ana module.\n\nValue on reset: 0"]
412#[derive(Clone, Copy, Debug, PartialEq, Eq)]
413pub enum LVDS_EN_MB_A {
414    #[doc = "0: Disable"]
415    DISABLE = 0,
416    #[doc = "1: Enable"]
417    ENABLE = 1,
418}
419impl From<LVDS_EN_MB_A> for bool {
420    #[inline(always)]
421    fn from(variant: LVDS_EN_MB_A) -> Self {
422        variant as u8 != 0
423    }
424}
425impl LVDS_EN_MB_R {
426    #[doc = "Get enumerated values variant"]
427    #[inline(always)]
428    pub const fn variant(&self) -> LVDS_EN_MB_A {
429        match self.bits {
430            false => LVDS_EN_MB_A::DISABLE,
431            true => LVDS_EN_MB_A::ENABLE,
432        }
433    }
434    #[doc = "Disable"]
435    #[inline(always)]
436    pub fn is_disable(&self) -> bool {
437        *self == LVDS_EN_MB_A::DISABLE
438    }
439    #[doc = "Enable"]
440    #[inline(always)]
441    pub fn is_enable(&self) -> bool {
442        *self == LVDS_EN_MB_A::ENABLE
443    }
444}
445#[doc = "Field `lvds_en_mb` writer - Enable the bias circuit of the LVDS_Ana module."]
446pub type LVDS_EN_MB_W<'a, REG> = crate::BitWriter<'a, REG, LVDS_EN_MB_A>;
447impl<'a, REG> LVDS_EN_MB_W<'a, REG>
448where
449    REG: crate::Writable + crate::RegisterSpec,
450{
451    #[doc = "Disable"]
452    #[inline(always)]
453    pub fn disable(self) -> &'a mut crate::W<REG> {
454        self.variant(LVDS_EN_MB_A::DISABLE)
455    }
456    #[doc = "Enable"]
457    #[inline(always)]
458    pub fn enable(self) -> &'a mut crate::W<REG> {
459        self.variant(LVDS_EN_MB_A::ENABLE)
460    }
461}
462impl R {
463    #[doc = "Bits 0:3 - LVDS data channel \\[3:0\\] direction."]
464    #[inline(always)]
465    pub fn lvds_plr(&self) -> LVDS_PLR_R {
466        LVDS_PLR_R::new((self.bits & 0x0f) as u8)
467    }
468    #[doc = "Bit 4 - LVDS clock channel direction."]
469    #[inline(always)]
470    pub fn lvds_plrc(&self) -> LVDS_PLRC_R {
471        LVDS_PLRC_R::new(((self.bits >> 4) & 1) != 0)
472    }
473    #[doc = "Bits 8:10 - Adjust current flowing through R of R to change the common signals amplitude."]
474    #[inline(always)]
475    pub fn lvds_r(&self) -> LVDS_R_R {
476        LVDS_R_R::new(((self.bits >> 8) & 7) as u8)
477    }
478    #[doc = "Bits 12:15 - Choose data output or PLL test clock output in LVDS_tx."]
479    #[inline(always)]
480    pub fn lvds_den(&self) -> LVDS_DEN_R {
481        LVDS_DEN_R::new(((self.bits >> 12) & 0x0f) as u8)
482    }
483    #[doc = "Bit 16 - Choose data output or PLL test clock output in LVDS_tx."]
484    #[inline(always)]
485    pub fn lvds_denc(&self) -> LVDS_DENC_R {
486        LVDS_DENC_R::new(((self.bits >> 16) & 1) != 0)
487    }
488    #[doc = "Bits 17:19 - Adjust current flowing through Rload of Rx to change the differential signals amplitude."]
489    #[inline(always)]
490    pub fn lvds_c(&self) -> LVDS_C_R {
491        LVDS_C_R::new(((self.bits >> 17) & 7) as u8)
492    }
493    #[doc = "Bits 20:23 - Enable data channel\\[3:0\\] drive"]
494    #[inline(always)]
495    pub fn lvds_hpren_drv(&self) -> LVDS_HPREN_DRV_R {
496        LVDS_HPREN_DRV_R::new(((self.bits >> 20) & 0x0f) as u8)
497    }
498    #[doc = "Bit 24 - Enable clock channel drive"]
499    #[inline(always)]
500    pub fn lvds_hpren_drvc(&self) -> LVDS_HPREN_DRVC_R {
501        LVDS_HPREN_DRVC_R::new(((self.bits >> 24) & 1) != 0)
502    }
503    #[doc = "Bit 28 - Enable the 24M clock"]
504    #[inline(always)]
505    pub fn en_24m(&self) -> EN_24M_R {
506        EN_24M_R::new(((self.bits >> 28) & 1) != 0)
507    }
508    #[doc = "Bit 29 - Enable LVDS"]
509    #[inline(always)]
510    pub fn en_lvds(&self) -> EN_LVDS_R {
511        EN_LVDS_R::new(((self.bits >> 29) & 1) != 0)
512    }
513    #[doc = "Bit 31 - Enable the bias circuit of the LVDS_Ana module."]
514    #[inline(always)]
515    pub fn lvds_en_mb(&self) -> LVDS_EN_MB_R {
516        LVDS_EN_MB_R::new(((self.bits >> 31) & 1) != 0)
517    }
518}
519impl W {
520    #[doc = "Bits 0:3 - LVDS data channel \\[3:0\\] direction."]
521    #[inline(always)]
522    #[must_use]
523    pub fn lvds_plr(&mut self) -> LVDS_PLR_W<LCD_LVDS_ANA_SPEC> {
524        LVDS_PLR_W::new(self, 0)
525    }
526    #[doc = "Bit 4 - LVDS clock channel direction."]
527    #[inline(always)]
528    #[must_use]
529    pub fn lvds_plrc(&mut self) -> LVDS_PLRC_W<LCD_LVDS_ANA_SPEC> {
530        LVDS_PLRC_W::new(self, 4)
531    }
532    #[doc = "Bits 8:10 - Adjust current flowing through R of R to change the common signals amplitude."]
533    #[inline(always)]
534    #[must_use]
535    pub fn lvds_r(&mut self) -> LVDS_R_W<LCD_LVDS_ANA_SPEC> {
536        LVDS_R_W::new(self, 8)
537    }
538    #[doc = "Bits 12:15 - Choose data output or PLL test clock output in LVDS_tx."]
539    #[inline(always)]
540    #[must_use]
541    pub fn lvds_den(&mut self) -> LVDS_DEN_W<LCD_LVDS_ANA_SPEC> {
542        LVDS_DEN_W::new(self, 12)
543    }
544    #[doc = "Bit 16 - Choose data output or PLL test clock output in LVDS_tx."]
545    #[inline(always)]
546    #[must_use]
547    pub fn lvds_denc(&mut self) -> LVDS_DENC_W<LCD_LVDS_ANA_SPEC> {
548        LVDS_DENC_W::new(self, 16)
549    }
550    #[doc = "Bits 17:19 - Adjust current flowing through Rload of Rx to change the differential signals amplitude."]
551    #[inline(always)]
552    #[must_use]
553    pub fn lvds_c(&mut self) -> LVDS_C_W<LCD_LVDS_ANA_SPEC> {
554        LVDS_C_W::new(self, 17)
555    }
556    #[doc = "Bits 20:23 - Enable data channel\\[3:0\\] drive"]
557    #[inline(always)]
558    #[must_use]
559    pub fn lvds_hpren_drv(&mut self) -> LVDS_HPREN_DRV_W<LCD_LVDS_ANA_SPEC> {
560        LVDS_HPREN_DRV_W::new(self, 20)
561    }
562    #[doc = "Bit 24 - Enable clock channel drive"]
563    #[inline(always)]
564    #[must_use]
565    pub fn lvds_hpren_drvc(&mut self) -> LVDS_HPREN_DRVC_W<LCD_LVDS_ANA_SPEC> {
566        LVDS_HPREN_DRVC_W::new(self, 24)
567    }
568    #[doc = "Bit 28 - Enable the 24M clock"]
569    #[inline(always)]
570    #[must_use]
571    pub fn en_24m(&mut self) -> EN_24M_W<LCD_LVDS_ANA_SPEC> {
572        EN_24M_W::new(self, 28)
573    }
574    #[doc = "Bit 29 - Enable LVDS"]
575    #[inline(always)]
576    #[must_use]
577    pub fn en_lvds(&mut self) -> EN_LVDS_W<LCD_LVDS_ANA_SPEC> {
578        EN_LVDS_W::new(self, 29)
579    }
580    #[doc = "Bit 31 - Enable the bias circuit of the LVDS_Ana module."]
581    #[inline(always)]
582    #[must_use]
583    pub fn lvds_en_mb(&mut self) -> LVDS_EN_MB_W<LCD_LVDS_ANA_SPEC> {
584        LVDS_EN_MB_W::new(self, 31)
585    }
586    #[doc = r" Writes raw bits to the register."]
587    #[doc = r""]
588    #[doc = r" # Safety"]
589    #[doc = r""]
590    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
591    #[inline(always)]
592    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
593        self.bits = bits;
594        self
595    }
596}
597#[doc = "LCD LVDS Analog Register \\[i\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_lvds_ana::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_lvds_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
598pub struct LCD_LVDS_ANA_SPEC;
599impl crate::RegisterSpec for LCD_LVDS_ANA_SPEC {
600    type Ux = u32;
601}
602#[doc = "`read()` method returns [`lcd_lvds_ana::R`](R) reader structure"]
603impl crate::Readable for LCD_LVDS_ANA_SPEC {}
604#[doc = "`write(|w| ..)` method takes [`lcd_lvds_ana::W`](W) writer structure"]
605impl crate::Writable for LCD_LVDS_ANA_SPEC {
606    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
607    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
608}
609#[doc = "`reset()` method sets lcd_lvds_ana%s to value 0"]
610impl crate::Resettable for LCD_LVDS_ANA_SPEC {
611    const RESET_VALUE: Self::Ux = 0;
612}
d1_pac/tcon_lcd0/lcd_lvds_ana.rs

d1_pac/tcon_lcd0/
lcd_lvds_ana.rs
