d1_pac/ccu/
audio_codec_adc_clk.rs

1#[doc = "Register `audio_codec_adc_clk` reader"]
2pub type R = crate::R<AUDIO_CODEC_ADC_CLK_SPEC>;
3#[doc = "Register `audio_codec_adc_clk` writer"]
4pub type W = crate::W<AUDIO_CODEC_ADC_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    PLL_AUDIO0_1X = 0,
102    #[doc = "1: `1`"]
103    PLL_AUDIO1_DIV2 = 1,
104    #[doc = "2: `10`"]
105    PLL_AUDIO1_DIV5 = 2,
106}
107impl From<CLK_SRC_SEL_A> for u8 {
108    #[inline(always)]
109    fn from(variant: CLK_SRC_SEL_A) -> Self {
110        variant as _
111    }
112}
113impl crate::FieldSpec for CLK_SRC_SEL_A {
114    type Ux = u8;
115}
116impl CLK_SRC_SEL_R {
117    #[doc = "Get enumerated values variant"]
118    #[inline(always)]
119    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
120        match self.bits {
121            0 => Some(CLK_SRC_SEL_A::PLL_AUDIO0_1X),
122            1 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
123            2 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5),
124            _ => None,
125        }
126    }
127    #[doc = "`0`"]
128    #[inline(always)]
129    pub fn is_pll_audio0_1x(&self) -> bool {
130        *self == CLK_SRC_SEL_A::PLL_AUDIO0_1X
131    }
132    #[doc = "`1`"]
133    #[inline(always)]
134    pub fn is_pll_audio1_div2(&self) -> bool {
135        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
136    }
137    #[doc = "`10`"]
138    #[inline(always)]
139    pub fn is_pll_audio1_div5(&self) -> bool {
140        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV5
141    }
142}
143#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
144pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
145impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
146where
147    REG: crate::Writable + crate::RegisterSpec,
148    REG::Ux: From<u8>,
149{
150    #[doc = "`0`"]
151    #[inline(always)]
152    pub fn pll_audio0_1x(self) -> &'a mut crate::W<REG> {
153        self.variant(CLK_SRC_SEL_A::PLL_AUDIO0_1X)
154    }
155    #[doc = "`1`"]
156    #[inline(always)]
157    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
158        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
159    }
160    #[doc = "`10`"]
161    #[inline(always)]
162    pub fn pll_audio1_div5(self) -> &'a mut crate::W<REG> {
163        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5)
164    }
165}
166#[doc = "Field `clk_gating` reader - Gating Clock"]
167pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
168#[doc = "Gating Clock\n\nValue on reset: 0"]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum CLK_GATING_A {
171    #[doc = "0: `0`"]
172    OFF = 0,
173    #[doc = "1: `1`"]
174    ON = 1,
175}
176impl From<CLK_GATING_A> for bool {
177    #[inline(always)]
178    fn from(variant: CLK_GATING_A) -> Self {
179        variant as u8 != 0
180    }
181}
182impl CLK_GATING_R {
183    #[doc = "Get enumerated values variant"]
184    #[inline(always)]
185    pub const fn variant(&self) -> CLK_GATING_A {
186        match self.bits {
187            false => CLK_GATING_A::OFF,
188            true => CLK_GATING_A::ON,
189        }
190    }
191    #[doc = "`0`"]
192    #[inline(always)]
193    pub fn is_off(&self) -> bool {
194        *self == CLK_GATING_A::OFF
195    }
196    #[doc = "`1`"]
197    #[inline(always)]
198    pub fn is_on(&self) -> bool {
199        *self == CLK_GATING_A::ON
200    }
201}
202#[doc = "Field `clk_gating` writer - Gating Clock"]
203pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
204impl<'a, REG> CLK_GATING_W<'a, REG>
205where
206    REG: crate::Writable + crate::RegisterSpec,
207{
208    #[doc = "`0`"]
209    #[inline(always)]
210    pub fn off(self) -> &'a mut crate::W<REG> {
211        self.variant(CLK_GATING_A::OFF)
212    }
213    #[doc = "`1`"]
214    #[inline(always)]
215    pub fn on(self) -> &'a mut crate::W<REG> {
216        self.variant(CLK_GATING_A::ON)
217    }
218}
219impl R {
220    #[doc = "Bits 0:4 - Factor M"]
221    #[inline(always)]
222    pub fn factor_m(&self) -> FACTOR_M_R {
223        FACTOR_M_R::new((self.bits & 0x1f) as u8)
224    }
225    #[doc = "Bits 8:9 - Factor N"]
226    #[inline(always)]
227    pub fn factor_n(&self) -> FACTOR_N_R {
228        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
229    }
230    #[doc = "Bits 24:26 - Clock Source Select"]
231    #[inline(always)]
232    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
233        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
234    }
235    #[doc = "Bit 31 - Gating Clock"]
236    #[inline(always)]
237    pub fn clk_gating(&self) -> CLK_GATING_R {
238        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
239    }
240}
241impl W {
242    #[doc = "Bits 0:4 - Factor M"]
243    #[inline(always)]
244    #[must_use]
245    pub fn factor_m(&mut self) -> FACTOR_M_W<AUDIO_CODEC_ADC_CLK_SPEC> {
246        FACTOR_M_W::new(self, 0)
247    }
248    #[doc = "Bits 8:9 - Factor N"]
249    #[inline(always)]
250    #[must_use]
251    pub fn factor_n(&mut self) -> FACTOR_N_W<AUDIO_CODEC_ADC_CLK_SPEC> {
252        FACTOR_N_W::new(self, 8)
253    }
254    #[doc = "Bits 24:26 - Clock Source Select"]
255    #[inline(always)]
256    #[must_use]
257    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<AUDIO_CODEC_ADC_CLK_SPEC> {
258        CLK_SRC_SEL_W::new(self, 24)
259    }
260    #[doc = "Bit 31 - Gating Clock"]
261    #[inline(always)]
262    #[must_use]
263    pub fn clk_gating(&mut self) -> CLK_GATING_W<AUDIO_CODEC_ADC_CLK_SPEC> {
264        CLK_GATING_W::new(self, 31)
265    }
266    #[doc = r" Writes raw bits to the register."]
267    #[doc = r""]
268    #[doc = r" # Safety"]
269    #[doc = r""]
270    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
271    #[inline(always)]
272    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
273        self.bits = bits;
274        self
275    }
276}
277#[doc = "AUDIO_CODEC_ADC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_codec_adc_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_codec_adc_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
278pub struct AUDIO_CODEC_ADC_CLK_SPEC;
279impl crate::RegisterSpec for AUDIO_CODEC_ADC_CLK_SPEC {
280    type Ux = u32;
281}
282#[doc = "`read()` method returns [`audio_codec_adc_clk::R`](R) reader structure"]
283impl crate::Readable for AUDIO_CODEC_ADC_CLK_SPEC {}
284#[doc = "`write(|w| ..)` method takes [`audio_codec_adc_clk::W`](W) writer structure"]
285impl crate::Writable for AUDIO_CODEC_ADC_CLK_SPEC {
286    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
287    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
288}
289#[doc = "`reset()` method sets audio_codec_adc_clk to value 0"]
290impl crate::Resettable for AUDIO_CODEC_ADC_CLK_SPEC {
291    const RESET_VALUE: Self::Ux = 0;
292}
d1_pac/ccu/audio_codec_adc_clk.rs

d1_pac/ccu/
audio_codec_adc_clk.rs
