1#[doc = "Register `iommu_dm_aut_ctrl%s` reader"]
2pub type R = crate::R<IOMMU_DM_AUT_CTRL_SPEC>;
3#[doc = "Register `iommu_dm_aut_ctrl%s` writer"]
4pub type W = crate::W<IOMMU_DM_AUT_CTRL_SPEC>;
5#[doc = "Field `dm1_m_wt_aut_ctrl[0-6]` reader - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
6pub type DM1_M_WT_AUT_CTRL_R = crate::BitReader<DM1_M_WT_AUT_CTRL_A>;
7#[doc = "Domain \\[i + 1\\] write permission control for master \\[j\\]\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DM1_M_WT_AUT_CTRL_A {
10 #[doc = "0: The write-operation is permitted"]
11 PERMITTED = 0,
12 #[doc = "1: The write-operation is prohibited"]
13 PROHIBITED = 1,
14}
15impl From<DM1_M_WT_AUT_CTRL_A> for bool {
16 #[inline(always)]
17 fn from(variant: DM1_M_WT_AUT_CTRL_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl DM1_M_WT_AUT_CTRL_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> DM1_M_WT_AUT_CTRL_A {
25 match self.bits {
26 false => DM1_M_WT_AUT_CTRL_A::PERMITTED,
27 true => DM1_M_WT_AUT_CTRL_A::PROHIBITED,
28 }
29 }
30 #[doc = "The write-operation is permitted"]
31 #[inline(always)]
32 pub fn is_permitted(&self) -> bool {
33 *self == DM1_M_WT_AUT_CTRL_A::PERMITTED
34 }
35 #[doc = "The write-operation is prohibited"]
36 #[inline(always)]
37 pub fn is_prohibited(&self) -> bool {
38 *self == DM1_M_WT_AUT_CTRL_A::PROHIBITED
39 }
40}
41#[doc = "Field `dm1_m_wt_aut_ctrl[0-6]` writer - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
42pub type DM1_M_WT_AUT_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, DM1_M_WT_AUT_CTRL_A>;
43impl<'a, REG> DM1_M_WT_AUT_CTRL_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "The write-operation is permitted"]
48 #[inline(always)]
49 pub fn permitted(self) -> &'a mut crate::W<REG> {
50 self.variant(DM1_M_WT_AUT_CTRL_A::PERMITTED)
51 }
52 #[doc = "The write-operation is prohibited"]
53 #[inline(always)]
54 pub fn prohibited(self) -> &'a mut crate::W<REG> {
55 self.variant(DM1_M_WT_AUT_CTRL_A::PROHIBITED)
56 }
57}
58#[doc = "Field `dm1_m_rd_aut_ctrl[0-6]` reader - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
59pub type DM1_M_RD_AUT_CTRL_R = crate::BitReader<DM1_M_RD_AUT_CTRL_A>;
60#[doc = "Domain \\[i + 1\\] read permission control for master \\[j\\]\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum DM1_M_RD_AUT_CTRL_A {
63 #[doc = "0: The read-operation is permitted"]
64 PERMITTED = 0,
65 #[doc = "1: The read-operation is prohibited"]
66 PROHIBITED = 1,
67}
68impl From<DM1_M_RD_AUT_CTRL_A> for bool {
69 #[inline(always)]
70 fn from(variant: DM1_M_RD_AUT_CTRL_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl DM1_M_RD_AUT_CTRL_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> DM1_M_RD_AUT_CTRL_A {
78 match self.bits {
79 false => DM1_M_RD_AUT_CTRL_A::PERMITTED,
80 true => DM1_M_RD_AUT_CTRL_A::PROHIBITED,
81 }
82 }
83 #[doc = "The read-operation is permitted"]
84 #[inline(always)]
85 pub fn is_permitted(&self) -> bool {
86 *self == DM1_M_RD_AUT_CTRL_A::PERMITTED
87 }
88 #[doc = "The read-operation is prohibited"]
89 #[inline(always)]
90 pub fn is_prohibited(&self) -> bool {
91 *self == DM1_M_RD_AUT_CTRL_A::PROHIBITED
92 }
93}
94#[doc = "Field `dm1_m_rd_aut_ctrl[0-6]` writer - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
95pub type DM1_M_RD_AUT_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, DM1_M_RD_AUT_CTRL_A>;
96impl<'a, REG> DM1_M_RD_AUT_CTRL_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "The read-operation is permitted"]
101 #[inline(always)]
102 pub fn permitted(self) -> &'a mut crate::W<REG> {
103 self.variant(DM1_M_RD_AUT_CTRL_A::PERMITTED)
104 }
105 #[doc = "The read-operation is prohibited"]
106 #[inline(always)]
107 pub fn prohibited(self) -> &'a mut crate::W<REG> {
108 self.variant(DM1_M_RD_AUT_CTRL_A::PROHIBITED)
109 }
110}
111#[doc = "Field `dm0_m_wt_aut_ctrl[0-6]` reader - Domain \\[i\\] write permission control for master \\[j\\]"]
112pub type DM0_M_WT_AUT_CTRL_R = crate::BitReader<DM0_M_WT_AUT_CTRL_A>;
113#[doc = "Domain \\[i\\] write permission control for master \\[j\\]\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DM0_M_WT_AUT_CTRL_A {
116 #[doc = "0: The write-operation is permitted"]
117 PERMITTED = 0,
118 #[doc = "1: The write-operation is prohibited"]
119 PROHIBITED = 1,
120}
121impl From<DM0_M_WT_AUT_CTRL_A> for bool {
122 #[inline(always)]
123 fn from(variant: DM0_M_WT_AUT_CTRL_A) -> Self {
124 variant as u8 != 0
125 }
126}
127impl DM0_M_WT_AUT_CTRL_R {
128 #[doc = "Get enumerated values variant"]
129 #[inline(always)]
130 pub const fn variant(&self) -> DM0_M_WT_AUT_CTRL_A {
131 match self.bits {
132 false => DM0_M_WT_AUT_CTRL_A::PERMITTED,
133 true => DM0_M_WT_AUT_CTRL_A::PROHIBITED,
134 }
135 }
136 #[doc = "The write-operation is permitted"]
137 #[inline(always)]
138 pub fn is_permitted(&self) -> bool {
139 *self == DM0_M_WT_AUT_CTRL_A::PERMITTED
140 }
141 #[doc = "The write-operation is prohibited"]
142 #[inline(always)]
143 pub fn is_prohibited(&self) -> bool {
144 *self == DM0_M_WT_AUT_CTRL_A::PROHIBITED
145 }
146}
147#[doc = "Field `dm0_m_wt_aut_ctrl[0-6]` writer - Domain \\[i\\] write permission control for master \\[j\\]"]
148pub type DM0_M_WT_AUT_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, DM0_M_WT_AUT_CTRL_A>;
149impl<'a, REG> DM0_M_WT_AUT_CTRL_W<'a, REG>
150where
151 REG: crate::Writable + crate::RegisterSpec,
152{
153 #[doc = "The write-operation is permitted"]
154 #[inline(always)]
155 pub fn permitted(self) -> &'a mut crate::W<REG> {
156 self.variant(DM0_M_WT_AUT_CTRL_A::PERMITTED)
157 }
158 #[doc = "The write-operation is prohibited"]
159 #[inline(always)]
160 pub fn prohibited(self) -> &'a mut crate::W<REG> {
161 self.variant(DM0_M_WT_AUT_CTRL_A::PROHIBITED)
162 }
163}
164#[doc = "Field `dm0_m_rd_aut_ctrl[0-6]` reader - Domain \\[i\\] read permission control for master \\[j\\]"]
165pub type DM0_M_RD_AUT_CTRL_R = crate::BitReader<DM0_M_RD_AUT_CTRL_A>;
166#[doc = "Domain \\[i\\] read permission control for master \\[j\\]\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum DM0_M_RD_AUT_CTRL_A {
169 #[doc = "0: The read-operation is permitted"]
170 PERMITTED = 0,
171 #[doc = "1: The read-operation is prohibited"]
172 PROHIBITED = 1,
173}
174impl From<DM0_M_RD_AUT_CTRL_A> for bool {
175 #[inline(always)]
176 fn from(variant: DM0_M_RD_AUT_CTRL_A) -> Self {
177 variant as u8 != 0
178 }
179}
180impl DM0_M_RD_AUT_CTRL_R {
181 #[doc = "Get enumerated values variant"]
182 #[inline(always)]
183 pub const fn variant(&self) -> DM0_M_RD_AUT_CTRL_A {
184 match self.bits {
185 false => DM0_M_RD_AUT_CTRL_A::PERMITTED,
186 true => DM0_M_RD_AUT_CTRL_A::PROHIBITED,
187 }
188 }
189 #[doc = "The read-operation is permitted"]
190 #[inline(always)]
191 pub fn is_permitted(&self) -> bool {
192 *self == DM0_M_RD_AUT_CTRL_A::PERMITTED
193 }
194 #[doc = "The read-operation is prohibited"]
195 #[inline(always)]
196 pub fn is_prohibited(&self) -> bool {
197 *self == DM0_M_RD_AUT_CTRL_A::PROHIBITED
198 }
199}
200#[doc = "Field `dm0_m_rd_aut_ctrl[0-6]` writer - Domain \\[i\\] read permission control for master \\[j\\]"]
201pub type DM0_M_RD_AUT_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, DM0_M_RD_AUT_CTRL_A>;
202impl<'a, REG> DM0_M_RD_AUT_CTRL_W<'a, REG>
203where
204 REG: crate::Writable + crate::RegisterSpec,
205{
206 #[doc = "The read-operation is permitted"]
207 #[inline(always)]
208 pub fn permitted(self) -> &'a mut crate::W<REG> {
209 self.variant(DM0_M_RD_AUT_CTRL_A::PERMITTED)
210 }
211 #[doc = "The read-operation is prohibited"]
212 #[inline(always)]
213 pub fn prohibited(self) -> &'a mut crate::W<REG> {
214 self.variant(DM0_M_RD_AUT_CTRL_A::PROHIBITED)
215 }
216}
217impl R {
218 #[doc = "Domain \\[i + 1\\] write permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm1_m0_wt_aut_ctrl` field"]
219 #[inline(always)]
220 pub fn dm1_m_wt_aut_ctrl(&self, n: u8) -> DM1_M_WT_AUT_CTRL_R {
221 #[allow(clippy::no_effect)]
222 [(); 7][n as usize];
223 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> (n * 2 + 17)) & 1) != 0)
224 }
225 #[doc = "Bit 17 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
226 #[inline(always)]
227 pub fn dm1_m0_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
228 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 17) & 1) != 0)
229 }
230 #[doc = "Bit 19 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
231 #[inline(always)]
232 pub fn dm1_m1_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
233 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 19) & 1) != 0)
234 }
235 #[doc = "Bit 21 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
236 #[inline(always)]
237 pub fn dm1_m2_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
238 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 21) & 1) != 0)
239 }
240 #[doc = "Bit 23 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
241 #[inline(always)]
242 pub fn dm1_m3_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
243 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 23) & 1) != 0)
244 }
245 #[doc = "Bit 25 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
246 #[inline(always)]
247 pub fn dm1_m4_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
248 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 25) & 1) != 0)
249 }
250 #[doc = "Bit 27 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
251 #[inline(always)]
252 pub fn dm1_m5_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
253 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 27) & 1) != 0)
254 }
255 #[doc = "Bit 29 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
256 #[inline(always)]
257 pub fn dm1_m6_wt_aut_ctrl(&self) -> DM1_M_WT_AUT_CTRL_R {
258 DM1_M_WT_AUT_CTRL_R::new(((self.bits >> 29) & 1) != 0)
259 }
260 #[doc = "Domain \\[i + 1\\] read permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm1_m0_rd_aut_ctrl` field"]
261 #[inline(always)]
262 pub fn dm1_m_rd_aut_ctrl(&self, n: u8) -> DM1_M_RD_AUT_CTRL_R {
263 #[allow(clippy::no_effect)]
264 [(); 7][n as usize];
265 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> (n * 2 + 17)) & 1) != 0)
266 }
267 #[doc = "Bit 17 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
268 #[inline(always)]
269 pub fn dm1_m0_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
270 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 17) & 1) != 0)
271 }
272 #[doc = "Bit 19 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
273 #[inline(always)]
274 pub fn dm1_m1_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
275 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 19) & 1) != 0)
276 }
277 #[doc = "Bit 21 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
278 #[inline(always)]
279 pub fn dm1_m2_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
280 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 21) & 1) != 0)
281 }
282 #[doc = "Bit 23 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
283 #[inline(always)]
284 pub fn dm1_m3_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
285 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 23) & 1) != 0)
286 }
287 #[doc = "Bit 25 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
288 #[inline(always)]
289 pub fn dm1_m4_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
290 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 25) & 1) != 0)
291 }
292 #[doc = "Bit 27 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
293 #[inline(always)]
294 pub fn dm1_m5_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
295 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 27) & 1) != 0)
296 }
297 #[doc = "Bit 29 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
298 #[inline(always)]
299 pub fn dm1_m6_rd_aut_ctrl(&self) -> DM1_M_RD_AUT_CTRL_R {
300 DM1_M_RD_AUT_CTRL_R::new(((self.bits >> 29) & 1) != 0)
301 }
302 #[doc = "Domain \\[i\\] write permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm0_m0_wt_aut_ctrl` field"]
303 #[inline(always)]
304 pub fn dm0_m_wt_aut_ctrl(&self, n: u8) -> DM0_M_WT_AUT_CTRL_R {
305 #[allow(clippy::no_effect)]
306 [(); 7][n as usize];
307 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> (n * 2 + 17)) & 1) != 0)
308 }
309 #[doc = "Bit 17 - Domain \\[i\\] write permission control for master \\[j\\]"]
310 #[inline(always)]
311 pub fn dm0_m0_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
312 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 17) & 1) != 0)
313 }
314 #[doc = "Bit 19 - Domain \\[i\\] write permission control for master \\[j\\]"]
315 #[inline(always)]
316 pub fn dm0_m1_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
317 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 19) & 1) != 0)
318 }
319 #[doc = "Bit 21 - Domain \\[i\\] write permission control for master \\[j\\]"]
320 #[inline(always)]
321 pub fn dm0_m2_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
322 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 21) & 1) != 0)
323 }
324 #[doc = "Bit 23 - Domain \\[i\\] write permission control for master \\[j\\]"]
325 #[inline(always)]
326 pub fn dm0_m3_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
327 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 23) & 1) != 0)
328 }
329 #[doc = "Bit 25 - Domain \\[i\\] write permission control for master \\[j\\]"]
330 #[inline(always)]
331 pub fn dm0_m4_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
332 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 25) & 1) != 0)
333 }
334 #[doc = "Bit 27 - Domain \\[i\\] write permission control for master \\[j\\]"]
335 #[inline(always)]
336 pub fn dm0_m5_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
337 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 27) & 1) != 0)
338 }
339 #[doc = "Bit 29 - Domain \\[i\\] write permission control for master \\[j\\]"]
340 #[inline(always)]
341 pub fn dm0_m6_wt_aut_ctrl(&self) -> DM0_M_WT_AUT_CTRL_R {
342 DM0_M_WT_AUT_CTRL_R::new(((self.bits >> 29) & 1) != 0)
343 }
344 #[doc = "Domain \\[i\\] read permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm0_m0_rd_aut_ctrl` field"]
345 #[inline(always)]
346 pub fn dm0_m_rd_aut_ctrl(&self, n: u8) -> DM0_M_RD_AUT_CTRL_R {
347 #[allow(clippy::no_effect)]
348 [(); 7][n as usize];
349 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> (n * 2 + 17)) & 1) != 0)
350 }
351 #[doc = "Bit 17 - Domain \\[i\\] read permission control for master \\[j\\]"]
352 #[inline(always)]
353 pub fn dm0_m0_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
354 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 17) & 1) != 0)
355 }
356 #[doc = "Bit 19 - Domain \\[i\\] read permission control for master \\[j\\]"]
357 #[inline(always)]
358 pub fn dm0_m1_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
359 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 19) & 1) != 0)
360 }
361 #[doc = "Bit 21 - Domain \\[i\\] read permission control for master \\[j\\]"]
362 #[inline(always)]
363 pub fn dm0_m2_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
364 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 21) & 1) != 0)
365 }
366 #[doc = "Bit 23 - Domain \\[i\\] read permission control for master \\[j\\]"]
367 #[inline(always)]
368 pub fn dm0_m3_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
369 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 23) & 1) != 0)
370 }
371 #[doc = "Bit 25 - Domain \\[i\\] read permission control for master \\[j\\]"]
372 #[inline(always)]
373 pub fn dm0_m4_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
374 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 25) & 1) != 0)
375 }
376 #[doc = "Bit 27 - Domain \\[i\\] read permission control for master \\[j\\]"]
377 #[inline(always)]
378 pub fn dm0_m5_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
379 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 27) & 1) != 0)
380 }
381 #[doc = "Bit 29 - Domain \\[i\\] read permission control for master \\[j\\]"]
382 #[inline(always)]
383 pub fn dm0_m6_rd_aut_ctrl(&self) -> DM0_M_RD_AUT_CTRL_R {
384 DM0_M_RD_AUT_CTRL_R::new(((self.bits >> 29) & 1) != 0)
385 }
386}
387impl W {
388 #[doc = "Domain \\[i + 1\\] write permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm1_m0_wt_aut_ctrl` field"]
389 #[inline(always)]
390 #[must_use]
391 pub fn dm1_m_wt_aut_ctrl(&mut self, n: u8) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
392 #[allow(clippy::no_effect)]
393 [(); 7][n as usize];
394 DM1_M_WT_AUT_CTRL_W::new(self, n * 2 + 17)
395 }
396 #[doc = "Bit 17 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
397 #[inline(always)]
398 #[must_use]
399 pub fn dm1_m0_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
400 DM1_M_WT_AUT_CTRL_W::new(self, 17)
401 }
402 #[doc = "Bit 19 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
403 #[inline(always)]
404 #[must_use]
405 pub fn dm1_m1_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
406 DM1_M_WT_AUT_CTRL_W::new(self, 19)
407 }
408 #[doc = "Bit 21 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
409 #[inline(always)]
410 #[must_use]
411 pub fn dm1_m2_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
412 DM1_M_WT_AUT_CTRL_W::new(self, 21)
413 }
414 #[doc = "Bit 23 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
415 #[inline(always)]
416 #[must_use]
417 pub fn dm1_m3_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
418 DM1_M_WT_AUT_CTRL_W::new(self, 23)
419 }
420 #[doc = "Bit 25 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
421 #[inline(always)]
422 #[must_use]
423 pub fn dm1_m4_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
424 DM1_M_WT_AUT_CTRL_W::new(self, 25)
425 }
426 #[doc = "Bit 27 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
427 #[inline(always)]
428 #[must_use]
429 pub fn dm1_m5_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
430 DM1_M_WT_AUT_CTRL_W::new(self, 27)
431 }
432 #[doc = "Bit 29 - Domain \\[i + 1\\] write permission control for master \\[j\\]"]
433 #[inline(always)]
434 #[must_use]
435 pub fn dm1_m6_wt_aut_ctrl(&mut self) -> DM1_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
436 DM1_M_WT_AUT_CTRL_W::new(self, 29)
437 }
438 #[doc = "Domain \\[i + 1\\] read permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm1_m0_rd_aut_ctrl` field"]
439 #[inline(always)]
440 #[must_use]
441 pub fn dm1_m_rd_aut_ctrl(&mut self, n: u8) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
442 #[allow(clippy::no_effect)]
443 [(); 7][n as usize];
444 DM1_M_RD_AUT_CTRL_W::new(self, n * 2 + 17)
445 }
446 #[doc = "Bit 17 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
447 #[inline(always)]
448 #[must_use]
449 pub fn dm1_m0_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
450 DM1_M_RD_AUT_CTRL_W::new(self, 17)
451 }
452 #[doc = "Bit 19 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
453 #[inline(always)]
454 #[must_use]
455 pub fn dm1_m1_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
456 DM1_M_RD_AUT_CTRL_W::new(self, 19)
457 }
458 #[doc = "Bit 21 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
459 #[inline(always)]
460 #[must_use]
461 pub fn dm1_m2_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
462 DM1_M_RD_AUT_CTRL_W::new(self, 21)
463 }
464 #[doc = "Bit 23 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
465 #[inline(always)]
466 #[must_use]
467 pub fn dm1_m3_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
468 DM1_M_RD_AUT_CTRL_W::new(self, 23)
469 }
470 #[doc = "Bit 25 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
471 #[inline(always)]
472 #[must_use]
473 pub fn dm1_m4_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
474 DM1_M_RD_AUT_CTRL_W::new(self, 25)
475 }
476 #[doc = "Bit 27 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
477 #[inline(always)]
478 #[must_use]
479 pub fn dm1_m5_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
480 DM1_M_RD_AUT_CTRL_W::new(self, 27)
481 }
482 #[doc = "Bit 29 - Domain \\[i + 1\\] read permission control for master \\[j\\]"]
483 #[inline(always)]
484 #[must_use]
485 pub fn dm1_m6_rd_aut_ctrl(&mut self) -> DM1_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
486 DM1_M_RD_AUT_CTRL_W::new(self, 29)
487 }
488 #[doc = "Domain \\[i\\] write permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm0_m0_wt_aut_ctrl` field"]
489 #[inline(always)]
490 #[must_use]
491 pub fn dm0_m_wt_aut_ctrl(&mut self, n: u8) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
492 #[allow(clippy::no_effect)]
493 [(); 7][n as usize];
494 DM0_M_WT_AUT_CTRL_W::new(self, n * 2 + 17)
495 }
496 #[doc = "Bit 17 - Domain \\[i\\] write permission control for master \\[j\\]"]
497 #[inline(always)]
498 #[must_use]
499 pub fn dm0_m0_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
500 DM0_M_WT_AUT_CTRL_W::new(self, 17)
501 }
502 #[doc = "Bit 19 - Domain \\[i\\] write permission control for master \\[j\\]"]
503 #[inline(always)]
504 #[must_use]
505 pub fn dm0_m1_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
506 DM0_M_WT_AUT_CTRL_W::new(self, 19)
507 }
508 #[doc = "Bit 21 - Domain \\[i\\] write permission control for master \\[j\\]"]
509 #[inline(always)]
510 #[must_use]
511 pub fn dm0_m2_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
512 DM0_M_WT_AUT_CTRL_W::new(self, 21)
513 }
514 #[doc = "Bit 23 - Domain \\[i\\] write permission control for master \\[j\\]"]
515 #[inline(always)]
516 #[must_use]
517 pub fn dm0_m3_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
518 DM0_M_WT_AUT_CTRL_W::new(self, 23)
519 }
520 #[doc = "Bit 25 - Domain \\[i\\] write permission control for master \\[j\\]"]
521 #[inline(always)]
522 #[must_use]
523 pub fn dm0_m4_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
524 DM0_M_WT_AUT_CTRL_W::new(self, 25)
525 }
526 #[doc = "Bit 27 - Domain \\[i\\] write permission control for master \\[j\\]"]
527 #[inline(always)]
528 #[must_use]
529 pub fn dm0_m5_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
530 DM0_M_WT_AUT_CTRL_W::new(self, 27)
531 }
532 #[doc = "Bit 29 - Domain \\[i\\] write permission control for master \\[j\\]"]
533 #[inline(always)]
534 #[must_use]
535 pub fn dm0_m6_wt_aut_ctrl(&mut self) -> DM0_M_WT_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
536 DM0_M_WT_AUT_CTRL_W::new(self, 29)
537 }
538 #[doc = "Domain \\[i\\] read permission control for master \\[j\\]\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dm0_m0_rd_aut_ctrl` field"]
539 #[inline(always)]
540 #[must_use]
541 pub fn dm0_m_rd_aut_ctrl(&mut self, n: u8) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
542 #[allow(clippy::no_effect)]
543 [(); 7][n as usize];
544 DM0_M_RD_AUT_CTRL_W::new(self, n * 2 + 17)
545 }
546 #[doc = "Bit 17 - Domain \\[i\\] read permission control for master \\[j\\]"]
547 #[inline(always)]
548 #[must_use]
549 pub fn dm0_m0_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
550 DM0_M_RD_AUT_CTRL_W::new(self, 17)
551 }
552 #[doc = "Bit 19 - Domain \\[i\\] read permission control for master \\[j\\]"]
553 #[inline(always)]
554 #[must_use]
555 pub fn dm0_m1_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
556 DM0_M_RD_AUT_CTRL_W::new(self, 19)
557 }
558 #[doc = "Bit 21 - Domain \\[i\\] read permission control for master \\[j\\]"]
559 #[inline(always)]
560 #[must_use]
561 pub fn dm0_m2_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
562 DM0_M_RD_AUT_CTRL_W::new(self, 21)
563 }
564 #[doc = "Bit 23 - Domain \\[i\\] read permission control for master \\[j\\]"]
565 #[inline(always)]
566 #[must_use]
567 pub fn dm0_m3_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
568 DM0_M_RD_AUT_CTRL_W::new(self, 23)
569 }
570 #[doc = "Bit 25 - Domain \\[i\\] read permission control for master \\[j\\]"]
571 #[inline(always)]
572 #[must_use]
573 pub fn dm0_m4_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
574 DM0_M_RD_AUT_CTRL_W::new(self, 25)
575 }
576 #[doc = "Bit 27 - Domain \\[i\\] read permission control for master \\[j\\]"]
577 #[inline(always)]
578 #[must_use]
579 pub fn dm0_m5_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
580 DM0_M_RD_AUT_CTRL_W::new(self, 27)
581 }
582 #[doc = "Bit 29 - Domain \\[i\\] read permission control for master \\[j\\]"]
583 #[inline(always)]
584 #[must_use]
585 pub fn dm0_m6_rd_aut_ctrl(&mut self) -> DM0_M_RD_AUT_CTRL_W<IOMMU_DM_AUT_CTRL_SPEC> {
586 DM0_M_RD_AUT_CTRL_W::new(self, 29)
587 }
588 #[doc = r" Writes raw bits to the register."]
589 #[doc = r""]
590 #[doc = r" # Safety"]
591 #[doc = r""]
592 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
593 #[inline(always)]
594 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
595 self.bits = bits;
596 self
597 }
598}
599#[doc = "IOMMU Domain Authority Control \\[i\\] Register\n\nSoftware can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.\n\nSoftware needs to set the index of the permission control domain corresponding to the page table item in the bit\\[7:4\\] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.\n\nSetting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_dm_aut_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_dm_aut_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
600pub struct IOMMU_DM_AUT_CTRL_SPEC;
601impl crate::RegisterSpec for IOMMU_DM_AUT_CTRL_SPEC {
602 type Ux = u32;
603}
604#[doc = "`read()` method returns [`iommu_dm_aut_ctrl::R`](R) reader structure"]
605impl crate::Readable for IOMMU_DM_AUT_CTRL_SPEC {}
606#[doc = "`write(|w| ..)` method takes [`iommu_dm_aut_ctrl::W`](W) writer structure"]
607impl crate::Writable for IOMMU_DM_AUT_CTRL_SPEC {
608 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
609 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
610}
611#[doc = "`reset()` method sets iommu_dm_aut_ctrl%s to value 0"]
612impl crate::Resettable for IOMMU_DM_AUT_CTRL_SPEC {
613 const RESET_VALUE: Self::Ux = 0;
614}