d1_pac/uart/
hsk.rs

1#[doc = "Register `hsk` reader"]
2pub type R = crate::R<HSK_SPEC>;
3#[doc = "Register `hsk` writer"]
4pub type W = crate::W<HSK_SPEC>;
5#[doc = "Field `hsk` reader - Handshake configuration"]
6pub type HSK_R = crate::FieldReader<HSK_A>;
7#[doc = "Handshake configuration\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum HSK_A {
11    #[doc = "165: `10100101`"]
12    WAIT_CYCLE = 165,
13    #[doc = "229: `11100101`"]
14    HANDSHAKE = 229,
15}
16impl From<HSK_A> for u8 {
17    #[inline(always)]
18    fn from(variant: HSK_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for HSK_A {
23    type Ux = u8;
24}
25impl HSK_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<HSK_A> {
29        match self.bits {
30            165 => Some(HSK_A::WAIT_CYCLE),
31            229 => Some(HSK_A::HANDSHAKE),
32            _ => None,
33        }
34    }
35    #[doc = "`10100101`"]
36    #[inline(always)]
37    pub fn is_wait_cycle(&self) -> bool {
38        *self == HSK_A::WAIT_CYCLE
39    }
40    #[doc = "`11100101`"]
41    #[inline(always)]
42    pub fn is_handshake(&self) -> bool {
43        *self == HSK_A::HANDSHAKE
44    }
45}
46#[doc = "Field `hsk` writer - Handshake configuration"]
47pub type HSK_W<'a, REG> = crate::FieldWriter<'a, REG, 8, HSK_A>;
48impl<'a, REG> HSK_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u8>,
52{
53    #[doc = "`10100101`"]
54    #[inline(always)]
55    pub fn wait_cycle(self) -> &'a mut crate::W<REG> {
56        self.variant(HSK_A::WAIT_CYCLE)
57    }
58    #[doc = "`11100101`"]
59    #[inline(always)]
60    pub fn handshake(self) -> &'a mut crate::W<REG> {
61        self.variant(HSK_A::HANDSHAKE)
62    }
63}
64impl R {
65    #[doc = "Bits 0:7 - Handshake configuration"]
66    #[inline(always)]
67    pub fn hsk(&self) -> HSK_R {
68        HSK_R::new((self.bits & 0xff) as u8)
69    }
70}
71impl W {
72    #[doc = "Bits 0:7 - Handshake configuration"]
73    #[inline(always)]
74    #[must_use]
75    pub fn hsk(&mut self) -> HSK_W<HSK_SPEC> {
76        HSK_W::new(self, 0)
77    }
78    #[doc = r" Writes raw bits to the register."]
79    #[doc = r""]
80    #[doc = r" # Safety"]
81    #[doc = r""]
82    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.bits = bits;
86        self
87    }
88}
89#[doc = "UART DMA Handshake Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hsk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
90pub struct HSK_SPEC;
91impl crate::RegisterSpec for HSK_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [`hsk::R`](R) reader structure"]
95impl crate::Readable for HSK_SPEC {}
96#[doc = "`write(|w| ..)` method takes [`hsk::W`](W) writer structure"]
97impl crate::Writable for HSK_SPEC {
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100}
101#[doc = "`reset()` method sets hsk to value 0"]
102impl crate::Resettable for HSK_SPEC {
103    const RESET_VALUE: Self::Ux = 0;
104}
d1_pac/uart/hsk.rs

d1_pac/uart/
hsk.rs
