1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 cir_tglr: CIR_TGLR,
5 cir_tmcr: CIR_TMCR,
6 cir_tcr: CIR_TCR,
7 cir_idc_h: CIR_IDC_H,
8 cir_idc_l: CIR_IDC_L,
9 cir_ticr_h: CIR_TICR_H,
10 cir_ticr_l: CIR_TICR_L,
11 _reserved7: [u8; 0x04],
12 cir_tel: CIR_TEL,
13 cir_txint: CIR_TXINT,
14 cir_tac: CIR_TAC,
15 cir_txsta: CIR_TXSTA,
16 cir_txt: CIR_TXT,
17 cir_dma_ctl: CIR_DMA_CTL,
18 _reserved13: [u8; 0x48],
19 cir_txfifo: CIR_TXFIFO,
20}
21impl RegisterBlock {
22 #[doc = "0x00 - CIR Transmit Global Register"]
23 #[inline(always)]
24 pub const fn cir_tglr(&self) -> &CIR_TGLR {
25 &self.cir_tglr
26 }
27 #[doc = "0x04 - CIR Transmit Modulation Control Register"]
28 #[inline(always)]
29 pub const fn cir_tmcr(&self) -> &CIR_TMCR {
30 &self.cir_tmcr
31 }
32 #[doc = "0x08 - CIR Transmit Control Register"]
33 #[inline(always)]
34 pub const fn cir_tcr(&self) -> &CIR_TCR {
35 &self.cir_tcr
36 }
37 #[doc = "0x0c - CIR Transmit Idle Duration Threshold High Bit Register"]
38 #[inline(always)]
39 pub const fn cir_idc_h(&self) -> &CIR_IDC_H {
40 &self.cir_idc_h
41 }
42 #[doc = "0x10 - CIR Transmit Idle Duration Threshold Low Bit Register"]
43 #[inline(always)]
44 pub const fn cir_idc_l(&self) -> &CIR_IDC_L {
45 &self.cir_idc_l
46 }
47 #[doc = "0x14 - CIR Transmit Idle Counter High Bit Register"]
48 #[inline(always)]
49 pub const fn cir_ticr_h(&self) -> &CIR_TICR_H {
50 &self.cir_ticr_h
51 }
52 #[doc = "0x18 - CIR Transmit Idle Counter Low Bit Register"]
53 #[inline(always)]
54 pub const fn cir_ticr_l(&self) -> &CIR_TICR_L {
55 &self.cir_ticr_l
56 }
57 #[doc = "0x20 - CIR TX FIFO Empty Level Register"]
58 #[inline(always)]
59 pub const fn cir_tel(&self) -> &CIR_TEL {
60 &self.cir_tel
61 }
62 #[doc = "0x24 - CIR Transmit Interrupt Control Register"]
63 #[inline(always)]
64 pub const fn cir_txint(&self) -> &CIR_TXINT {
65 &self.cir_txint
66 }
67 #[doc = "0x28 - CIR Transmit FIFO Available Counter Register"]
68 #[inline(always)]
69 pub const fn cir_tac(&self) -> &CIR_TAC {
70 &self.cir_tac
71 }
72 #[doc = "0x2c - CIR Transmit Status Register"]
73 #[inline(always)]
74 pub const fn cir_txsta(&self) -> &CIR_TXSTA {
75 &self.cir_txsta
76 }
77 #[doc = "0x30 - CIR Transmit Threshold Register"]
78 #[inline(always)]
79 pub const fn cir_txt(&self) -> &CIR_TXT {
80 &self.cir_txt
81 }
82 #[doc = "0x34 - CIR DMA Control Register"]
83 #[inline(always)]
84 pub const fn cir_dma_ctl(&self) -> &CIR_DMA_CTL {
85 &self.cir_dma_ctl
86 }
87 #[doc = "0x80 - CIR Transmit FIFO Data Register"]
88 #[inline(always)]
89 pub const fn cir_txfifo(&self) -> &CIR_TXFIFO {
90 &self.cir_txfifo
91 }
92}
93#[doc = "cir_tglr (rw) register accessor: CIR Transmit Global Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tglr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tglr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_tglr`] module"]
94pub type CIR_TGLR = crate::Reg<cir_tglr::CIR_TGLR_SPEC>;
95#[doc = "CIR Transmit Global Register"]
96pub mod cir_tglr;
97#[doc = "cir_tmcr (rw) register accessor: CIR Transmit Modulation Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tmcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tmcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_tmcr`] module"]
98pub type CIR_TMCR = crate::Reg<cir_tmcr::CIR_TMCR_SPEC>;
99#[doc = "CIR Transmit Modulation Control Register"]
100pub mod cir_tmcr;
101#[doc = "cir_tcr (rw) register accessor: CIR Transmit Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_tcr`] module"]
102pub type CIR_TCR = crate::Reg<cir_tcr::CIR_TCR_SPEC>;
103#[doc = "CIR Transmit Control Register"]
104pub mod cir_tcr;
105#[doc = "cir_idc_h (rw) register accessor: CIR Transmit Idle Duration Threshold High Bit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_idc_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_idc_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_idc_h`] module"]
106pub type CIR_IDC_H = crate::Reg<cir_idc_h::CIR_IDC_H_SPEC>;
107#[doc = "CIR Transmit Idle Duration Threshold High Bit Register"]
108pub mod cir_idc_h;
109#[doc = "cir_idc_l (rw) register accessor: CIR Transmit Idle Duration Threshold Low Bit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_idc_l::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_idc_l::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_idc_l`] module"]
110pub type CIR_IDC_L = crate::Reg<cir_idc_l::CIR_IDC_L_SPEC>;
111#[doc = "CIR Transmit Idle Duration Threshold Low Bit Register"]
112pub mod cir_idc_l;
113#[doc = "cir_ticr_h (rw) register accessor: CIR Transmit Idle Counter High Bit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_ticr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_ticr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_ticr_h`] module"]
114pub type CIR_TICR_H = crate::Reg<cir_ticr_h::CIR_TICR_H_SPEC>;
115#[doc = "CIR Transmit Idle Counter High Bit Register"]
116pub mod cir_ticr_h;
117#[doc = "cir_ticr_l (rw) register accessor: CIR Transmit Idle Counter Low Bit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_ticr_l::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_ticr_l::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_ticr_l`] module"]
118pub type CIR_TICR_L = crate::Reg<cir_ticr_l::CIR_TICR_L_SPEC>;
119#[doc = "CIR Transmit Idle Counter Low Bit Register"]
120pub mod cir_ticr_l;
121#[doc = "cir_tel (rw) register accessor: CIR TX FIFO Empty Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_tel`] module"]
122pub type CIR_TEL = crate::Reg<cir_tel::CIR_TEL_SPEC>;
123#[doc = "CIR TX FIFO Empty Level Register"]
124pub mod cir_tel;
125#[doc = "cir_txint (rw) register accessor: CIR Transmit Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_txint`] module"]
126pub type CIR_TXINT = crate::Reg<cir_txint::CIR_TXINT_SPEC>;
127#[doc = "CIR Transmit Interrupt Control Register"]
128pub mod cir_txint;
129#[doc = "cir_tac (rw) register accessor: CIR Transmit FIFO Available Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_tac`] module"]
130pub type CIR_TAC = crate::Reg<cir_tac::CIR_TAC_SPEC>;
131#[doc = "CIR Transmit FIFO Available Counter Register"]
132pub mod cir_tac;
133#[doc = "cir_txsta (rw) register accessor: CIR Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txsta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txsta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_txsta`] module"]
134pub type CIR_TXSTA = crate::Reg<cir_txsta::CIR_TXSTA_SPEC>;
135#[doc = "CIR Transmit Status Register"]
136pub mod cir_txsta;
137#[doc = "cir_txt (rw) register accessor: CIR Transmit Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_txt`] module"]
138pub type CIR_TXT = crate::Reg<cir_txt::CIR_TXT_SPEC>;
139#[doc = "CIR Transmit Threshold Register"]
140pub mod cir_txt;
141#[doc = "cir_dma_ctl (rw) register accessor: CIR DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_dma_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_dma_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_dma_ctl`] module"]
142pub type CIR_DMA_CTL = crate::Reg<cir_dma_ctl::CIR_DMA_CTL_SPEC>;
143#[doc = "CIR DMA Control Register"]
144pub mod cir_dma_ctl;
145#[doc = "cir_txfifo (rw) register accessor: CIR Transmit FIFO Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txfifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txfifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir_txfifo`] module"]
146pub type CIR_TXFIFO = crate::Reg<cir_txfifo::CIR_TXFIFO_SPEC>;
147#[doc = "CIR Transmit FIFO Data Register"]
148pub mod cir_txfifo;