d1_pac/iommu/
iommu_pmu_ml.rs

1#[doc = "Register `iommu_pmu_ml%s` reader"]
2pub type R = crate::R<IOMMU_PMU_ML_SPEC>;
3#[doc = "Register `iommu_pmu_ml%s` writer"]
4pub type W = crate::W<IOMMU_PMU_ML_SPEC>;
5impl core::fmt::Debug for R {
6    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7        write!(f, "{}", self.bits())
8    }
9}
10impl core::fmt::Debug for crate::generic::Reg<IOMMU_PMU_ML_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        core::fmt::Debug::fmt(&self.read(), f)
13    }
14}
15impl W {
16    #[doc = r" Writes raw bits to the register."]
17    #[doc = r""]
18    #[doc = r" # Safety"]
19    #[doc = r""]
20    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
21    #[inline(always)]
22    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
23        self.bits = bits;
24        self
25    }
26}
27#[doc = "IOMMU Max Latency \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_ml::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_ml::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28pub struct IOMMU_PMU_ML_SPEC;
29impl crate::RegisterSpec for IOMMU_PMU_ML_SPEC {
30    type Ux = u32;
31}
32#[doc = "`read()` method returns [`iommu_pmu_ml::R`](R) reader structure"]
33impl crate::Readable for IOMMU_PMU_ML_SPEC {}
34#[doc = "`write(|w| ..)` method takes [`iommu_pmu_ml::W`](W) writer structure"]
35impl crate::Writable for IOMMU_PMU_ML_SPEC {
36    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
37    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
38}
39#[doc = "`reset()` method sets iommu_pmu_ml%s to value 0"]
40impl crate::Resettable for IOMMU_PMU_ML_SPEC {
41    const RESET_VALUE: Self::Ux = 0;
42}
d1_pac/iommu/iommu_pmu_ml.rs

d1_pac/iommu/
iommu_pmu_ml.rs
