d1_pac/ccu/
pll_ve_pat1_ctrl.rs

1#[doc = "Register `pll_ve_pat1_ctrl` reader"]
2pub type R = crate::R<PLL_VE_PAT1_CTRL_SPEC>;
3#[doc = "Register `pll_ve_pat1_ctrl` writer"]
4pub type W = crate::W<PLL_VE_PAT1_CTRL_SPEC>;
5#[doc = "Field `frac_in` reader - Fraction In"]
6pub type FRAC_IN_R = crate::FieldReader<u32>;
7#[doc = "Field `frac_in` writer - Fraction In"]
8pub type FRAC_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
9#[doc = "Field `frac_en` reader - Fraction Enable"]
10pub type FRAC_EN_R = crate::BitReader;
11#[doc = "Field `frac_en` writer - Fraction Enable"]
12pub type FRAC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `dither_en` reader - Dither Enable"]
14pub type DITHER_EN_R = crate::BitReader;
15#[doc = "Field `dither_en` writer - Dither Enable"]
16pub type DITHER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:16 - Fraction In"]
19    #[inline(always)]
20    pub fn frac_in(&self) -> FRAC_IN_R {
21        FRAC_IN_R::new(self.bits & 0x0001_ffff)
22    }
23    #[doc = "Bit 20 - Fraction Enable"]
24    #[inline(always)]
25    pub fn frac_en(&self) -> FRAC_EN_R {
26        FRAC_EN_R::new(((self.bits >> 20) & 1) != 0)
27    }
28    #[doc = "Bit 24 - Dither Enable"]
29    #[inline(always)]
30    pub fn dither_en(&self) -> DITHER_EN_R {
31        DITHER_EN_R::new(((self.bits >> 24) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bits 0:16 - Fraction In"]
36    #[inline(always)]
37    #[must_use]
38    pub fn frac_in(&mut self) -> FRAC_IN_W<PLL_VE_PAT1_CTRL_SPEC> {
39        FRAC_IN_W::new(self, 0)
40    }
41    #[doc = "Bit 20 - Fraction Enable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn frac_en(&mut self) -> FRAC_EN_W<PLL_VE_PAT1_CTRL_SPEC> {
45        FRAC_EN_W::new(self, 20)
46    }
47    #[doc = "Bit 24 - Dither Enable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn dither_en(&mut self) -> DITHER_EN_W<PLL_VE_PAT1_CTRL_SPEC> {
51        DITHER_EN_W::new(self, 24)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "PLL_VE Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ve_pat1_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ve_pat1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct PLL_VE_PAT1_CTRL_SPEC;
66impl crate::RegisterSpec for PLL_VE_PAT1_CTRL_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`pll_ve_pat1_ctrl::R`](R) reader structure"]
70impl crate::Readable for PLL_VE_PAT1_CTRL_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`pll_ve_pat1_ctrl::W`](W) writer structure"]
72impl crate::Writable for PLL_VE_PAT1_CTRL_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75}
76#[doc = "`reset()` method sets pll_ve_pat1_ctrl to value 0"]
77impl crate::Resettable for PLL_VE_PAT1_CTRL_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
d1_pac/ccu/pll_ve_pat1_ctrl.rs

d1_pac/ccu/
pll_ve_pat1_ctrl.rs
