d1-pac 0.0.32

Peripheral access API for Allwinner D1 SoC generated from unofficial SVD file
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

#[doc = "Register `iommu_int_sta` reader"]
pub type R = crate::R<IOMMU_INT_STA_SPEC>;
#[doc = "Register `iommu_int_sta` writer"]
pub type W = crate::W<IOMMU_INT_STA_SPEC>;
#[doc = "Field `micro_tlb_invalid_sta[0-6]` reader - Micro TLB\\[i\\] permission invalid interrupt status bit"]
pub type MICRO_TLB_INVALID_STA_R = crate::BitReader<MICRO_TLB_INVALID_STA_A>;
#[doc = "Micro TLB\\[i\\] permission invalid interrupt status bit\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MICRO_TLB_INVALID_STA_A {
    #[doc = "0: Interrupt does not happen or interrupt is cleared"]
    NOT_HAPPEN_OR_CLEARED = 0,
    #[doc = "1: Interrupt happens"]
    HAPPENS = 1,
}
impl From<MICRO_TLB_INVALID_STA_A> for bool {
    #[inline(always)]
    fn from(variant: MICRO_TLB_INVALID_STA_A) -> Self {
        variant as u8 != 0
    }
}
impl MICRO_TLB_INVALID_STA_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> MICRO_TLB_INVALID_STA_A {
        match self.bits {
            false => MICRO_TLB_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED,
            true => MICRO_TLB_INVALID_STA_A::HAPPENS,
        }
    }
    #[doc = "Interrupt does not happen or interrupt is cleared"]
    #[inline(always)]
    pub fn is_not_happen_or_cleared(&self) -> bool {
        *self == MICRO_TLB_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED
    }
    #[doc = "Interrupt happens"]
    #[inline(always)]
    pub fn is_happens(&self) -> bool {
        *self == MICRO_TLB_INVALID_STA_A::HAPPENS
    }
}
#[doc = "Field `l_page_table_invalid_sta[0-1]` reader - Level\\[i\\] page table invalid interrupt status bit"]
pub type L_PAGE_TABLE_INVALID_STA_R = crate::BitReader<L_PAGE_TABLE_INVALID_STA_A>;
#[doc = "Level\\[i\\] page table invalid interrupt status bit\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum L_PAGE_TABLE_INVALID_STA_A {
    #[doc = "0: Interrupt does not happen or interrupt is cleared"]
    NOT_HAPPEN_OR_CLEARED = 0,
    #[doc = "1: Interrupt happens"]
    HAPPENS = 1,
}
impl From<L_PAGE_TABLE_INVALID_STA_A> for bool {
    #[inline(always)]
    fn from(variant: L_PAGE_TABLE_INVALID_STA_A) -> Self {
        variant as u8 != 0
    }
}
impl L_PAGE_TABLE_INVALID_STA_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> L_PAGE_TABLE_INVALID_STA_A {
        match self.bits {
            false => L_PAGE_TABLE_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED,
            true => L_PAGE_TABLE_INVALID_STA_A::HAPPENS,
        }
    }
    #[doc = "Interrupt does not happen or interrupt is cleared"]
    #[inline(always)]
    pub fn is_not_happen_or_cleared(&self) -> bool {
        *self == L_PAGE_TABLE_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED
    }
    #[doc = "Interrupt happens"]
    #[inline(always)]
    pub fn is_happens(&self) -> bool {
        *self == L_PAGE_TABLE_INVALID_STA_A::HAPPENS
    }
}
impl R {
    #[doc = "Micro TLB\\[i\\] permission invalid interrupt status bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_invalid_sta` field"]
    #[inline(always)]
    pub fn micro_tlb_invalid_sta(&self, n: u8) -> MICRO_TLB_INVALID_STA_R {
        #[allow(clippy::no_effect)]
        [(); 7][n as usize];
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> (n * 2)) & 1) != 0)
    }
    #[doc = "Bit 0 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb0_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 2 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb1_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 4 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb2_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 6 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb3_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 8 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb4_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 10 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb5_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 12 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
    #[inline(always)]
    pub fn micro_tlb6_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Level\\[i\\] page table invalid interrupt status bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `l0_page_table_invalid_sta` field"]
    #[inline(always)]
    pub fn l_page_table_invalid_sta(&self, n: u8) -> L_PAGE_TABLE_INVALID_STA_R {
        #[allow(clippy::no_effect)]
        [(); 2][n as usize];
        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> (n + 16)) & 1) != 0)
    }
    #[doc = "Bit 16 - Level\\[i\\] page table invalid interrupt status bit"]
    #[inline(always)]
    pub fn l0_page_table_invalid_sta(&self) -> L_PAGE_TABLE_INVALID_STA_R {
        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17 - Level\\[i\\] page table invalid interrupt status bit"]
    #[inline(always)]
    pub fn l1_page_table_invalid_sta(&self) -> L_PAGE_TABLE_INVALID_STA_R {
        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> 17) & 1) != 0)
    }
}
impl W {
    #[doc = r" Writes raw bits to the register."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
}
#[doc = "IOMMU Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IOMMU_INT_STA_SPEC;
impl crate::RegisterSpec for IOMMU_INT_STA_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`iommu_int_sta::R`](R) reader structure"]
impl crate::Readable for IOMMU_INT_STA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`iommu_int_sta::W`](W) writer structure"]
impl crate::Writable for IOMMU_INT_STA_SPEC {
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets iommu_int_sta to value 0"]
impl crate::Resettable for IOMMU_INT_STA_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}