d1_pac/tcon_lcd0/
lcd_gint0.rs

1#[doc = "Register `lcd_gint0` reader"]
2pub type R = crate::R<LCD_GINT0_SPEC>;
3#[doc = "Register `lcd_gint0` writer"]
4pub type W = crate::W<LCD_GINT0_SPEC>;
5#[doc = "Field `fsync_int_flag` reader - Asserted at the fsync signal in every frame\n\nWrite 0 to clear it."]
6pub type FSYNC_INT_FLAG_R = crate::BitReader;
7#[doc = "Field `fsync_int_flag` writer - Asserted at the fsync signal in every frame\n\nWrite 0 to clear it."]
8pub type FSYNC_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
9#[doc = "Field `de_int_flag` reader - Asserted at the first valid line in every frame\n\nWrite 0 to clear it."]
10pub type DE_INT_FLAG_R = crate::BitReader;
11#[doc = "Field `de_int_flag` writer - Asserted at the first valid line in every frame\n\nWrite 0 to clear it."]
12pub type DE_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
13#[doc = "Field `fsync_int_inv` reader - Enable the fsync interrupt to set signal inverse polarity.\n\nWhen FSYNC is positive, this bit must be 1.\n\nAnd vice versa."]
14pub type FSYNC_INT_INV_R = crate::BitReader;
15#[doc = "Field `fsync_int_inv` writer - Enable the fsync interrupt to set signal inverse polarity.\n\nWhen FSYNC is positive, this bit must be 1.\n\nAnd vice versa."]
16pub type FSYNC_INT_INV_W<'a, REG> = crate::BitWriter0C<'a, REG>;
17#[doc = "Field `lcd_tri_underflow_flag` reader - Only used in dsi video mode, tri when sync by dsi but not finish\n\nWrite 0 to clear it."]
18pub type LCD_TRI_UNDERFLOW_FLAG_R = crate::BitReader;
19#[doc = "Field `lcd_tri_underflow_flag` writer - Only used in dsi video mode, tri when sync by dsi but not finish\n\nWrite 0 to clear it."]
20pub type LCD_TRI_UNDERFLOW_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
21#[doc = "Field `lcd_tri_counter_int_flag` reader - Trigger when tri counter reaches this value\n\nWrite 0 to clear it."]
22pub type LCD_TRI_COUNTER_INT_FLAG_R = crate::BitReader;
23#[doc = "Field `lcd_tri_counter_int_flag` writer - Trigger when tri counter reaches this value\n\nWrite 0 to clear it."]
24pub type LCD_TRI_COUNTER_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
25#[doc = "Field `lcd_tri_finish_int_flag` reader - Trigger when cpu trigger mode finished\n\nWrite 0 to clear it."]
26pub type LCD_TRI_FINISH_INT_FLAG_R = crate::BitReader;
27#[doc = "Field `lcd_tri_finish_int_flag` writer - Trigger when cpu trigger mode finished\n\nWrite 0 to clear it."]
28pub type LCD_TRI_FINISH_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
29#[doc = "Field `lcd_line_int_flag` reader - Trigger when SY0 match the current LCD scan line\n\nWrite 0 to clear it."]
30pub type LCD_LINE_INT_FLAG_R = crate::BitReader;
31#[doc = "Field `lcd_line_int_flag` writer - Trigger when SY0 match the current LCD scan line\n\nWrite 0 to clear it."]
32pub type LCD_LINE_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
33#[doc = "Field `lcd_vb_int_flag` reader - Asserted during vertical no-display period every frame\n\nWrite 0 to clear it."]
34pub type LCD_VB_INT_FLAG_R = crate::BitReader;
35#[doc = "Field `lcd_vb_int_flag` writer - Asserted during vertical no-display period every frame\n\nWrite 0 to clear it."]
36pub type LCD_VB_INT_FLAG_W<'a, REG> = crate::BitWriter0C<'a, REG>;
37#[doc = "Field `lcd_tri_counter_int_en` reader - Enable the trigger counter interrupt"]
38pub type LCD_TRI_COUNTER_INT_EN_R = crate::BitReader<LCD_TRI_COUNTER_INT_EN_A>;
39#[doc = "Enable the trigger counter interrupt\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum LCD_TRI_COUNTER_INT_EN_A {
42    #[doc = "0: Disable"]
43    DISABLE = 0,
44    #[doc = "1: Enable"]
45    ENABLE = 1,
46}
47impl From<LCD_TRI_COUNTER_INT_EN_A> for bool {
48    #[inline(always)]
49    fn from(variant: LCD_TRI_COUNTER_INT_EN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl LCD_TRI_COUNTER_INT_EN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub const fn variant(&self) -> LCD_TRI_COUNTER_INT_EN_A {
57        match self.bits {
58            false => LCD_TRI_COUNTER_INT_EN_A::DISABLE,
59            true => LCD_TRI_COUNTER_INT_EN_A::ENABLE,
60        }
61    }
62    #[doc = "Disable"]
63    #[inline(always)]
64    pub fn is_disable(&self) -> bool {
65        *self == LCD_TRI_COUNTER_INT_EN_A::DISABLE
66    }
67    #[doc = "Enable"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == LCD_TRI_COUNTER_INT_EN_A::ENABLE
71    }
72}
73#[doc = "Field `lcd_tri_counter_int_en` writer - Enable the trigger counter interrupt"]
74pub type LCD_TRI_COUNTER_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, LCD_TRI_COUNTER_INT_EN_A>;
75impl<'a, REG> LCD_TRI_COUNTER_INT_EN_W<'a, REG>
76where
77    REG: crate::Writable + crate::RegisterSpec,
78{
79    #[doc = "Disable"]
80    #[inline(always)]
81    pub fn disable(self) -> &'a mut crate::W<REG> {
82        self.variant(LCD_TRI_COUNTER_INT_EN_A::DISABLE)
83    }
84    #[doc = "Enable"]
85    #[inline(always)]
86    pub fn enable(self) -> &'a mut crate::W<REG> {
87        self.variant(LCD_TRI_COUNTER_INT_EN_A::ENABLE)
88    }
89}
90#[doc = "Field `lcd_tri_finish_int_en` reader - Enable the trigger finish interrupt"]
91pub type LCD_TRI_FINISH_INT_EN_R = crate::BitReader<LCD_TRI_FINISH_INT_EN_A>;
92#[doc = "Enable the trigger finish interrupt\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum LCD_TRI_FINISH_INT_EN_A {
95    #[doc = "0: Disable"]
96    DISABLE = 0,
97    #[doc = "1: Enable"]
98    ENABLE = 1,
99}
100impl From<LCD_TRI_FINISH_INT_EN_A> for bool {
101    #[inline(always)]
102    fn from(variant: LCD_TRI_FINISH_INT_EN_A) -> Self {
103        variant as u8 != 0
104    }
105}
106impl LCD_TRI_FINISH_INT_EN_R {
107    #[doc = "Get enumerated values variant"]
108    #[inline(always)]
109    pub const fn variant(&self) -> LCD_TRI_FINISH_INT_EN_A {
110        match self.bits {
111            false => LCD_TRI_FINISH_INT_EN_A::DISABLE,
112            true => LCD_TRI_FINISH_INT_EN_A::ENABLE,
113        }
114    }
115    #[doc = "Disable"]
116    #[inline(always)]
117    pub fn is_disable(&self) -> bool {
118        *self == LCD_TRI_FINISH_INT_EN_A::DISABLE
119    }
120    #[doc = "Enable"]
121    #[inline(always)]
122    pub fn is_enable(&self) -> bool {
123        *self == LCD_TRI_FINISH_INT_EN_A::ENABLE
124    }
125}
126#[doc = "Field `lcd_tri_finish_int_en` writer - Enable the trigger finish interrupt"]
127pub type LCD_TRI_FINISH_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, LCD_TRI_FINISH_INT_EN_A>;
128impl<'a, REG> LCD_TRI_FINISH_INT_EN_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    #[doc = "Disable"]
133    #[inline(always)]
134    pub fn disable(self) -> &'a mut crate::W<REG> {
135        self.variant(LCD_TRI_FINISH_INT_EN_A::DISABLE)
136    }
137    #[doc = "Enable"]
138    #[inline(always)]
139    pub fn enable(self) -> &'a mut crate::W<REG> {
140        self.variant(LCD_TRI_FINISH_INT_EN_A::ENABLE)
141    }
142}
143#[doc = "Field `lcd_line_int_en` reader - Enable the line interrupt"]
144pub type LCD_LINE_INT_EN_R = crate::BitReader<LCD_LINE_INT_EN_A>;
145#[doc = "Enable the line interrupt\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum LCD_LINE_INT_EN_A {
148    #[doc = "0: Disable"]
149    DISABLE = 0,
150    #[doc = "1: Enable"]
151    ENABLE = 1,
152}
153impl From<LCD_LINE_INT_EN_A> for bool {
154    #[inline(always)]
155    fn from(variant: LCD_LINE_INT_EN_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl LCD_LINE_INT_EN_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub const fn variant(&self) -> LCD_LINE_INT_EN_A {
163        match self.bits {
164            false => LCD_LINE_INT_EN_A::DISABLE,
165            true => LCD_LINE_INT_EN_A::ENABLE,
166        }
167    }
168    #[doc = "Disable"]
169    #[inline(always)]
170    pub fn is_disable(&self) -> bool {
171        *self == LCD_LINE_INT_EN_A::DISABLE
172    }
173    #[doc = "Enable"]
174    #[inline(always)]
175    pub fn is_enable(&self) -> bool {
176        *self == LCD_LINE_INT_EN_A::ENABLE
177    }
178}
179#[doc = "Field `lcd_line_int_en` writer - Enable the line interrupt"]
180pub type LCD_LINE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, LCD_LINE_INT_EN_A>;
181impl<'a, REG> LCD_LINE_INT_EN_W<'a, REG>
182where
183    REG: crate::Writable + crate::RegisterSpec,
184{
185    #[doc = "Disable"]
186    #[inline(always)]
187    pub fn disable(self) -> &'a mut crate::W<REG> {
188        self.variant(LCD_LINE_INT_EN_A::DISABLE)
189    }
190    #[doc = "Enable"]
191    #[inline(always)]
192    pub fn enable(self) -> &'a mut crate::W<REG> {
193        self.variant(LCD_LINE_INT_EN_A::ENABLE)
194    }
195}
196#[doc = "Field `lcd_vb_int_en` reader - Enable the Vb interrupt"]
197pub type LCD_VB_INT_EN_R = crate::BitReader<LCD_VB_INT_EN_A>;
198#[doc = "Enable the Vb interrupt\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200pub enum LCD_VB_INT_EN_A {
201    #[doc = "0: Disable"]
202    DISABLE = 0,
203    #[doc = "1: Enable"]
204    ENABLE = 1,
205}
206impl From<LCD_VB_INT_EN_A> for bool {
207    #[inline(always)]
208    fn from(variant: LCD_VB_INT_EN_A) -> Self {
209        variant as u8 != 0
210    }
211}
212impl LCD_VB_INT_EN_R {
213    #[doc = "Get enumerated values variant"]
214    #[inline(always)]
215    pub const fn variant(&self) -> LCD_VB_INT_EN_A {
216        match self.bits {
217            false => LCD_VB_INT_EN_A::DISABLE,
218            true => LCD_VB_INT_EN_A::ENABLE,
219        }
220    }
221    #[doc = "Disable"]
222    #[inline(always)]
223    pub fn is_disable(&self) -> bool {
224        *self == LCD_VB_INT_EN_A::DISABLE
225    }
226    #[doc = "Enable"]
227    #[inline(always)]
228    pub fn is_enable(&self) -> bool {
229        *self == LCD_VB_INT_EN_A::ENABLE
230    }
231}
232#[doc = "Field `lcd_vb_int_en` writer - Enable the Vb interrupt"]
233pub type LCD_VB_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, LCD_VB_INT_EN_A>;
234impl<'a, REG> LCD_VB_INT_EN_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "Disable"]
239    #[inline(always)]
240    pub fn disable(self) -> &'a mut crate::W<REG> {
241        self.variant(LCD_VB_INT_EN_A::DISABLE)
242    }
243    #[doc = "Enable"]
244    #[inline(always)]
245    pub fn enable(self) -> &'a mut crate::W<REG> {
246        self.variant(LCD_VB_INT_EN_A::ENABLE)
247    }
248}
249impl R {
250    #[doc = "Bit 0 - Asserted at the fsync signal in every frame\n\nWrite 0 to clear it."]
251    #[inline(always)]
252    pub fn fsync_int_flag(&self) -> FSYNC_INT_FLAG_R {
253        FSYNC_INT_FLAG_R::new((self.bits & 1) != 0)
254    }
255    #[doc = "Bit 1 - Asserted at the first valid line in every frame\n\nWrite 0 to clear it."]
256    #[inline(always)]
257    pub fn de_int_flag(&self) -> DE_INT_FLAG_R {
258        DE_INT_FLAG_R::new(((self.bits >> 1) & 1) != 0)
259    }
260    #[doc = "Bit 2 - Enable the fsync interrupt to set signal inverse polarity.\n\nWhen FSYNC is positive, this bit must be 1.\n\nAnd vice versa."]
261    #[inline(always)]
262    pub fn fsync_int_inv(&self) -> FSYNC_INT_INV_R {
263        FSYNC_INT_INV_R::new(((self.bits >> 2) & 1) != 0)
264    }
265    #[doc = "Bit 9 - Only used in dsi video mode, tri when sync by dsi but not finish\n\nWrite 0 to clear it."]
266    #[inline(always)]
267    pub fn lcd_tri_underflow_flag(&self) -> LCD_TRI_UNDERFLOW_FLAG_R {
268        LCD_TRI_UNDERFLOW_FLAG_R::new(((self.bits >> 9) & 1) != 0)
269    }
270    #[doc = "Bit 10 - Trigger when tri counter reaches this value\n\nWrite 0 to clear it."]
271    #[inline(always)]
272    pub fn lcd_tri_counter_int_flag(&self) -> LCD_TRI_COUNTER_INT_FLAG_R {
273        LCD_TRI_COUNTER_INT_FLAG_R::new(((self.bits >> 10) & 1) != 0)
274    }
275    #[doc = "Bit 11 - Trigger when cpu trigger mode finished\n\nWrite 0 to clear it."]
276    #[inline(always)]
277    pub fn lcd_tri_finish_int_flag(&self) -> LCD_TRI_FINISH_INT_FLAG_R {
278        LCD_TRI_FINISH_INT_FLAG_R::new(((self.bits >> 11) & 1) != 0)
279    }
280    #[doc = "Bit 13 - Trigger when SY0 match the current LCD scan line\n\nWrite 0 to clear it."]
281    #[inline(always)]
282    pub fn lcd_line_int_flag(&self) -> LCD_LINE_INT_FLAG_R {
283        LCD_LINE_INT_FLAG_R::new(((self.bits >> 13) & 1) != 0)
284    }
285    #[doc = "Bit 15 - Asserted during vertical no-display period every frame\n\nWrite 0 to clear it."]
286    #[inline(always)]
287    pub fn lcd_vb_int_flag(&self) -> LCD_VB_INT_FLAG_R {
288        LCD_VB_INT_FLAG_R::new(((self.bits >> 15) & 1) != 0)
289    }
290    #[doc = "Bit 26 - Enable the trigger counter interrupt"]
291    #[inline(always)]
292    pub fn lcd_tri_counter_int_en(&self) -> LCD_TRI_COUNTER_INT_EN_R {
293        LCD_TRI_COUNTER_INT_EN_R::new(((self.bits >> 26) & 1) != 0)
294    }
295    #[doc = "Bit 27 - Enable the trigger finish interrupt"]
296    #[inline(always)]
297    pub fn lcd_tri_finish_int_en(&self) -> LCD_TRI_FINISH_INT_EN_R {
298        LCD_TRI_FINISH_INT_EN_R::new(((self.bits >> 27) & 1) != 0)
299    }
300    #[doc = "Bit 29 - Enable the line interrupt"]
301    #[inline(always)]
302    pub fn lcd_line_int_en(&self) -> LCD_LINE_INT_EN_R {
303        LCD_LINE_INT_EN_R::new(((self.bits >> 29) & 1) != 0)
304    }
305    #[doc = "Bit 31 - Enable the Vb interrupt"]
306    #[inline(always)]
307    pub fn lcd_vb_int_en(&self) -> LCD_VB_INT_EN_R {
308        LCD_VB_INT_EN_R::new(((self.bits >> 31) & 1) != 0)
309    }
310}
311impl W {
312    #[doc = "Bit 0 - Asserted at the fsync signal in every frame\n\nWrite 0 to clear it."]
313    #[inline(always)]
314    #[must_use]
315    pub fn fsync_int_flag(&mut self) -> FSYNC_INT_FLAG_W<LCD_GINT0_SPEC> {
316        FSYNC_INT_FLAG_W::new(self, 0)
317    }
318    #[doc = "Bit 1 - Asserted at the first valid line in every frame\n\nWrite 0 to clear it."]
319    #[inline(always)]
320    #[must_use]
321    pub fn de_int_flag(&mut self) -> DE_INT_FLAG_W<LCD_GINT0_SPEC> {
322        DE_INT_FLAG_W::new(self, 1)
323    }
324    #[doc = "Bit 2 - Enable the fsync interrupt to set signal inverse polarity.\n\nWhen FSYNC is positive, this bit must be 1.\n\nAnd vice versa."]
325    #[inline(always)]
326    #[must_use]
327    pub fn fsync_int_inv(&mut self) -> FSYNC_INT_INV_W<LCD_GINT0_SPEC> {
328        FSYNC_INT_INV_W::new(self, 2)
329    }
330    #[doc = "Bit 9 - Only used in dsi video mode, tri when sync by dsi but not finish\n\nWrite 0 to clear it."]
331    #[inline(always)]
332    #[must_use]
333    pub fn lcd_tri_underflow_flag(&mut self) -> LCD_TRI_UNDERFLOW_FLAG_W<LCD_GINT0_SPEC> {
334        LCD_TRI_UNDERFLOW_FLAG_W::new(self, 9)
335    }
336    #[doc = "Bit 10 - Trigger when tri counter reaches this value\n\nWrite 0 to clear it."]
337    #[inline(always)]
338    #[must_use]
339    pub fn lcd_tri_counter_int_flag(&mut self) -> LCD_TRI_COUNTER_INT_FLAG_W<LCD_GINT0_SPEC> {
340        LCD_TRI_COUNTER_INT_FLAG_W::new(self, 10)
341    }
342    #[doc = "Bit 11 - Trigger when cpu trigger mode finished\n\nWrite 0 to clear it."]
343    #[inline(always)]
344    #[must_use]
345    pub fn lcd_tri_finish_int_flag(&mut self) -> LCD_TRI_FINISH_INT_FLAG_W<LCD_GINT0_SPEC> {
346        LCD_TRI_FINISH_INT_FLAG_W::new(self, 11)
347    }
348    #[doc = "Bit 13 - Trigger when SY0 match the current LCD scan line\n\nWrite 0 to clear it."]
349    #[inline(always)]
350    #[must_use]
351    pub fn lcd_line_int_flag(&mut self) -> LCD_LINE_INT_FLAG_W<LCD_GINT0_SPEC> {
352        LCD_LINE_INT_FLAG_W::new(self, 13)
353    }
354    #[doc = "Bit 15 - Asserted during vertical no-display period every frame\n\nWrite 0 to clear it."]
355    #[inline(always)]
356    #[must_use]
357    pub fn lcd_vb_int_flag(&mut self) -> LCD_VB_INT_FLAG_W<LCD_GINT0_SPEC> {
358        LCD_VB_INT_FLAG_W::new(self, 15)
359    }
360    #[doc = "Bit 26 - Enable the trigger counter interrupt"]
361    #[inline(always)]
362    #[must_use]
363    pub fn lcd_tri_counter_int_en(&mut self) -> LCD_TRI_COUNTER_INT_EN_W<LCD_GINT0_SPEC> {
364        LCD_TRI_COUNTER_INT_EN_W::new(self, 26)
365    }
366    #[doc = "Bit 27 - Enable the trigger finish interrupt"]
367    #[inline(always)]
368    #[must_use]
369    pub fn lcd_tri_finish_int_en(&mut self) -> LCD_TRI_FINISH_INT_EN_W<LCD_GINT0_SPEC> {
370        LCD_TRI_FINISH_INT_EN_W::new(self, 27)
371    }
372    #[doc = "Bit 29 - Enable the line interrupt"]
373    #[inline(always)]
374    #[must_use]
375    pub fn lcd_line_int_en(&mut self) -> LCD_LINE_INT_EN_W<LCD_GINT0_SPEC> {
376        LCD_LINE_INT_EN_W::new(self, 29)
377    }
378    #[doc = "Bit 31 - Enable the Vb interrupt"]
379    #[inline(always)]
380    #[must_use]
381    pub fn lcd_vb_int_en(&mut self) -> LCD_VB_INT_EN_W<LCD_GINT0_SPEC> {
382        LCD_VB_INT_EN_W::new(self, 31)
383    }
384    #[doc = r" Writes raw bits to the register."]
385    #[doc = r""]
386    #[doc = r" # Safety"]
387    #[doc = r""]
388    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
389    #[inline(always)]
390    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
391        self.bits = bits;
392        self
393    }
394}
395#[doc = "LCD Global Interrupt Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_gint0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_gint0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
396pub struct LCD_GINT0_SPEC;
397impl crate::RegisterSpec for LCD_GINT0_SPEC {
398    type Ux = u32;
399}
400#[doc = "`read()` method returns [`lcd_gint0::R`](R) reader structure"]
401impl crate::Readable for LCD_GINT0_SPEC {}
402#[doc = "`write(|w| ..)` method takes [`lcd_gint0::W`](W) writer structure"]
403impl crate::Writable for LCD_GINT0_SPEC {
404    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xae07;
405    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
406}
407#[doc = "`reset()` method sets lcd_gint0 to value 0"]
408impl crate::Resettable for LCD_GINT0_SPEC {
409    const RESET_VALUE: Self::Ux = 0;
410}
d1_pac/tcon_lcd0/lcd_gint0.rs

d1_pac/tcon_lcd0/
lcd_gint0.rs
