d1_pac/gpio/
pb_eint_cfg0.rs1#[doc = "Register `pb_eint_cfg0` reader"]
2pub type R = crate::R<PB_EINT_CFG0_SPEC>;
3#[doc = "Register `pb_eint_cfg0` writer"]
4pub type W = crate::W<PB_EINT_CFG0_SPEC>;
5#[doc = "Field `eint_cfg[0-7]` reader - External INT Mode"]
6pub type EINT_CFG_R = crate::FieldReader<EINT_CFG_A>;
7#[doc = "External INT Mode\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum EINT_CFG_A {
11 #[doc = "0: `0`"]
12 POSITIVE_EDGE = 0,
13 #[doc = "1: `1`"]
14 NEGATIVE_EDGE = 1,
15 #[doc = "2: `10`"]
16 HIGH_LEVEL = 2,
17 #[doc = "3: `11`"]
18 LOW_LEVEL = 3,
19 #[doc = "4: `100`"]
20 DOUBLE_EDGE = 4,
21}
22impl From<EINT_CFG_A> for u8 {
23 #[inline(always)]
24 fn from(variant: EINT_CFG_A) -> Self {
25 variant as _
26 }
27}
28impl crate::FieldSpec for EINT_CFG_A {
29 type Ux = u8;
30}
31impl EINT_CFG_R {
32 #[doc = "Get enumerated values variant"]
33 #[inline(always)]
34 pub const fn variant(&self) -> Option<EINT_CFG_A> {
35 match self.bits {
36 0 => Some(EINT_CFG_A::POSITIVE_EDGE),
37 1 => Some(EINT_CFG_A::NEGATIVE_EDGE),
38 2 => Some(EINT_CFG_A::HIGH_LEVEL),
39 3 => Some(EINT_CFG_A::LOW_LEVEL),
40 4 => Some(EINT_CFG_A::DOUBLE_EDGE),
41 _ => None,
42 }
43 }
44 #[doc = "`0`"]
45 #[inline(always)]
46 pub fn is_positive_edge(&self) -> bool {
47 *self == EINT_CFG_A::POSITIVE_EDGE
48 }
49 #[doc = "`1`"]
50 #[inline(always)]
51 pub fn is_negative_edge(&self) -> bool {
52 *self == EINT_CFG_A::NEGATIVE_EDGE
53 }
54 #[doc = "`10`"]
55 #[inline(always)]
56 pub fn is_high_level(&self) -> bool {
57 *self == EINT_CFG_A::HIGH_LEVEL
58 }
59 #[doc = "`11`"]
60 #[inline(always)]
61 pub fn is_low_level(&self) -> bool {
62 *self == EINT_CFG_A::LOW_LEVEL
63 }
64 #[doc = "`100`"]
65 #[inline(always)]
66 pub fn is_double_edge(&self) -> bool {
67 *self == EINT_CFG_A::DOUBLE_EDGE
68 }
69}
70#[doc = "Field `eint_cfg[0-7]` writer - External INT Mode"]
71pub type EINT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4, EINT_CFG_A>;
72impl<'a, REG> EINT_CFG_W<'a, REG>
73where
74 REG: crate::Writable + crate::RegisterSpec,
75 REG::Ux: From<u8>,
76{
77 #[doc = "`0`"]
78 #[inline(always)]
79 pub fn positive_edge(self) -> &'a mut crate::W<REG> {
80 self.variant(EINT_CFG_A::POSITIVE_EDGE)
81 }
82 #[doc = "`1`"]
83 #[inline(always)]
84 pub fn negative_edge(self) -> &'a mut crate::W<REG> {
85 self.variant(EINT_CFG_A::NEGATIVE_EDGE)
86 }
87 #[doc = "`10`"]
88 #[inline(always)]
89 pub fn high_level(self) -> &'a mut crate::W<REG> {
90 self.variant(EINT_CFG_A::HIGH_LEVEL)
91 }
92 #[doc = "`11`"]
93 #[inline(always)]
94 pub fn low_level(self) -> &'a mut crate::W<REG> {
95 self.variant(EINT_CFG_A::LOW_LEVEL)
96 }
97 #[doc = "`100`"]
98 #[inline(always)]
99 pub fn double_edge(self) -> &'a mut crate::W<REG> {
100 self.variant(EINT_CFG_A::DOUBLE_EDGE)
101 }
102}
103impl R {
104 #[doc = "External INT Mode\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_cfg` field"]
105 #[inline(always)]
106 pub fn eint_cfg(&self, n: u8) -> EINT_CFG_R {
107 #[allow(clippy::no_effect)]
108 [(); 8][n as usize];
109 EINT_CFG_R::new(((self.bits >> (n * 4)) & 0x0f) as u8)
110 }
111 #[doc = "Bits 0:3 - External INT Mode"]
112 #[inline(always)]
113 pub fn eint0_cfg(&self) -> EINT_CFG_R {
114 EINT_CFG_R::new((self.bits & 0x0f) as u8)
115 }
116 #[doc = "Bits 4:7 - External INT Mode"]
117 #[inline(always)]
118 pub fn eint1_cfg(&self) -> EINT_CFG_R {
119 EINT_CFG_R::new(((self.bits >> 4) & 0x0f) as u8)
120 }
121 #[doc = "Bits 8:11 - External INT Mode"]
122 #[inline(always)]
123 pub fn eint2_cfg(&self) -> EINT_CFG_R {
124 EINT_CFG_R::new(((self.bits >> 8) & 0x0f) as u8)
125 }
126 #[doc = "Bits 12:15 - External INT Mode"]
127 #[inline(always)]
128 pub fn eint3_cfg(&self) -> EINT_CFG_R {
129 EINT_CFG_R::new(((self.bits >> 12) & 0x0f) as u8)
130 }
131 #[doc = "Bits 16:19 - External INT Mode"]
132 #[inline(always)]
133 pub fn eint4_cfg(&self) -> EINT_CFG_R {
134 EINT_CFG_R::new(((self.bits >> 16) & 0x0f) as u8)
135 }
136 #[doc = "Bits 20:23 - External INT Mode"]
137 #[inline(always)]
138 pub fn eint5_cfg(&self) -> EINT_CFG_R {
139 EINT_CFG_R::new(((self.bits >> 20) & 0x0f) as u8)
140 }
141 #[doc = "Bits 24:27 - External INT Mode"]
142 #[inline(always)]
143 pub fn eint6_cfg(&self) -> EINT_CFG_R {
144 EINT_CFG_R::new(((self.bits >> 24) & 0x0f) as u8)
145 }
146 #[doc = "Bits 28:31 - External INT Mode"]
147 #[inline(always)]
148 pub fn eint7_cfg(&self) -> EINT_CFG_R {
149 EINT_CFG_R::new(((self.bits >> 28) & 0x0f) as u8)
150 }
151}
152impl W {
153 #[doc = "External INT Mode\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_cfg` field"]
154 #[inline(always)]
155 #[must_use]
156 pub fn eint_cfg(&mut self, n: u8) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
157 #[allow(clippy::no_effect)]
158 [(); 8][n as usize];
159 EINT_CFG_W::new(self, n * 4)
160 }
161 #[doc = "Bits 0:3 - External INT Mode"]
162 #[inline(always)]
163 #[must_use]
164 pub fn eint0_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
165 EINT_CFG_W::new(self, 0)
166 }
167 #[doc = "Bits 4:7 - External INT Mode"]
168 #[inline(always)]
169 #[must_use]
170 pub fn eint1_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
171 EINT_CFG_W::new(self, 4)
172 }
173 #[doc = "Bits 8:11 - External INT Mode"]
174 #[inline(always)]
175 #[must_use]
176 pub fn eint2_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
177 EINT_CFG_W::new(self, 8)
178 }
179 #[doc = "Bits 12:15 - External INT Mode"]
180 #[inline(always)]
181 #[must_use]
182 pub fn eint3_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
183 EINT_CFG_W::new(self, 12)
184 }
185 #[doc = "Bits 16:19 - External INT Mode"]
186 #[inline(always)]
187 #[must_use]
188 pub fn eint4_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
189 EINT_CFG_W::new(self, 16)
190 }
191 #[doc = "Bits 20:23 - External INT Mode"]
192 #[inline(always)]
193 #[must_use]
194 pub fn eint5_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
195 EINT_CFG_W::new(self, 20)
196 }
197 #[doc = "Bits 24:27 - External INT Mode"]
198 #[inline(always)]
199 #[must_use]
200 pub fn eint6_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
201 EINT_CFG_W::new(self, 24)
202 }
203 #[doc = "Bits 28:31 - External INT Mode"]
204 #[inline(always)]
205 #[must_use]
206 pub fn eint7_cfg(&mut self) -> EINT_CFG_W<PB_EINT_CFG0_SPEC> {
207 EINT_CFG_W::new(self, 28)
208 }
209 #[doc = r" Writes raw bits to the register."]
210 #[doc = r""]
211 #[doc = r" # Safety"]
212 #[doc = r""]
213 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
214 #[inline(always)]
215 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
216 self.bits = bits;
217 self
218 }
219}
220#[doc = "PB External Interrupt Configure Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pb_eint_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pb_eint_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
221pub struct PB_EINT_CFG0_SPEC;
222impl crate::RegisterSpec for PB_EINT_CFG0_SPEC {
223 type Ux = u32;
224}
225#[doc = "`read()` method returns [`pb_eint_cfg0::R`](R) reader structure"]
226impl crate::Readable for PB_EINT_CFG0_SPEC {}
227#[doc = "`write(|w| ..)` method takes [`pb_eint_cfg0::W`](W) writer structure"]
228impl crate::Writable for PB_EINT_CFG0_SPEC {
229 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
230 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
231}
232#[doc = "`reset()` method sets pb_eint_cfg0 to value 0"]
233impl crate::Resettable for PB_EINT_CFG0_SPEC {
234 const RESET_VALUE: Self::Ux = 0;
235}