1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x04],
5 riscv_sta_add0: RISCV_STA_ADD0,
6 riscv_sta_add1: RISCV_STA_ADD1,
7 _reserved2: [u8; 0x04],
8 rf1p_cfg: RF1P_CFG,
9 _reserved3: [u8; 0x08],
10 rom_cfg: ROM_CFG,
11 wakeup_en: WAKEUP_EN,
12 wakeup_mask: [WAKEUP_MASK; 5],
13 _reserved6: [u8; 0x08],
14 ts_tmode_sel: TS_TMODE_SEL,
15 sram_addr_twist: SRAM_ADDR_TWIST,
16 work_mode: WORK_MODE,
17 _reserved9: [u8; 0x04],
18 retite_pc0: RETITE_PC0,
19 retite_pc1: RETITE_PC1,
20 _reserved11: [u8; 0x08],
21 irq_mode: [IRQ_MODE; 5],
22 _reserved12: [u8; 0x90],
23 riscv_axi_pmu_ctrl: RISCV_AXI_PMU_CTRL,
24 riscv_axi_pmu_prd: RISCV_AXI_PMU_PRD,
25 riscv_axi_pmu_lat_rd: RISCV_AXI_PMU_LAT_RD,
26 riscv_axi_pmu_lat_wr: RISCV_AXI_PMU_LAT_WR,
27 riscv_axi_pmu_req_rd: RISCV_AXI_PMU_REQ_RD,
28 riscv_axi_pmu_req_wr: RISCV_AXI_PMU_REQ_WR,
29 riscv_axi_pmu_bw_rd: RISCV_AXI_PMU_BW_RD,
30 riscv_axi_pmu_bw_wr: RISCV_AXI_PMU_BW_WR,
31}
32impl RegisterBlock {
33 #[doc = "0x04 - RISCV Start Address0 Register"]
34 #[inline(always)]
35 pub const fn riscv_sta_add0(&self) -> &RISCV_STA_ADD0 {
36 &self.riscv_sta_add0
37 }
38 #[doc = "0x08 - RISCV Start Address1 Register"]
39 #[inline(always)]
40 pub const fn riscv_sta_add1(&self) -> &RISCV_STA_ADD1 {
41 &self.riscv_sta_add1
42 }
43 #[doc = "0x10 - RF1P Configuration Register"]
44 #[inline(always)]
45 pub const fn rf1p_cfg(&self) -> &RF1P_CFG {
46 &self.rf1p_cfg
47 }
48 #[doc = "0x1c - ROM Configuration Register"]
49 #[inline(always)]
50 pub const fn rom_cfg(&self) -> &ROM_CFG {
51 &self.rom_cfg
52 }
53 #[doc = "0x20 - Wakeup Enable Register"]
54 #[inline(always)]
55 pub const fn wakeup_en(&self) -> &WAKEUP_EN {
56 &self.wakeup_en
57 }
58 #[doc = "0x24..0x38 - Wakeup Mask Register"]
59 #[inline(always)]
60 pub const fn wakeup_mask(&self, n: usize) -> &WAKEUP_MASK {
61 &self.wakeup_mask[n]
62 }
63 #[doc = "0x40 - Timestamp Test Mode Select Register"]
64 #[inline(always)]
65 pub const fn ts_tmode_sel(&self) -> &TS_TMODE_SEL {
66 &self.ts_tmode_sel
67 }
68 #[doc = "0x44 - SRAM Address Twist Register"]
69 #[inline(always)]
70 pub const fn sram_addr_twist(&self) -> &SRAM_ADDR_TWIST {
71 &self.sram_addr_twist
72 }
73 #[doc = "0x48 - Work Mode Register"]
74 #[inline(always)]
75 pub const fn work_mode(&self) -> &WORK_MODE {
76 &self.work_mode
77 }
78 #[doc = "0x50 - Retire PC0 Register"]
79 #[inline(always)]
80 pub const fn retite_pc0(&self) -> &RETITE_PC0 {
81 &self.retite_pc0
82 }
83 #[doc = "0x54 - Retire PC1 Register"]
84 #[inline(always)]
85 pub const fn retite_pc1(&self) -> &RETITE_PC1 {
86 &self.retite_pc1
87 }
88 #[doc = "0x60..0x74 - IRQ Mode Register"]
89 #[inline(always)]
90 pub const fn irq_mode(&self, n: usize) -> &IRQ_MODE {
91 &self.irq_mode[n]
92 }
93 #[doc = "0x104 - RISCV AXI PMU Control Register"]
94 #[inline(always)]
95 pub const fn riscv_axi_pmu_ctrl(&self) -> &RISCV_AXI_PMU_CTRL {
96 &self.riscv_axi_pmu_ctrl
97 }
98 #[doc = "0x108 - RISCV AXI PMU Period Register"]
99 #[inline(always)]
100 pub const fn riscv_axi_pmu_prd(&self) -> &RISCV_AXI_PMU_PRD {
101 &self.riscv_axi_pmu_prd
102 }
103 #[doc = "0x10c - RISCV AXI PMU Read Latency Register"]
104 #[inline(always)]
105 pub const fn riscv_axi_pmu_lat_rd(&self) -> &RISCV_AXI_PMU_LAT_RD {
106 &self.riscv_axi_pmu_lat_rd
107 }
108 #[doc = "0x110 - RISCV AXI PMU Write Latency Register"]
109 #[inline(always)]
110 pub const fn riscv_axi_pmu_lat_wr(&self) -> &RISCV_AXI_PMU_LAT_WR {
111 &self.riscv_axi_pmu_lat_wr
112 }
113 #[doc = "0x114 - RISCV AXI PMU Read Request Register"]
114 #[inline(always)]
115 pub const fn riscv_axi_pmu_req_rd(&self) -> &RISCV_AXI_PMU_REQ_RD {
116 &self.riscv_axi_pmu_req_rd
117 }
118 #[doc = "0x118 - RISCV AXI PMU Write Request Register"]
119 #[inline(always)]
120 pub const fn riscv_axi_pmu_req_wr(&self) -> &RISCV_AXI_PMU_REQ_WR {
121 &self.riscv_axi_pmu_req_wr
122 }
123 #[doc = "0x11c - RISCV AXI PMU Read Bandwidth Register"]
124 #[inline(always)]
125 pub const fn riscv_axi_pmu_bw_rd(&self) -> &RISCV_AXI_PMU_BW_RD {
126 &self.riscv_axi_pmu_bw_rd
127 }
128 #[doc = "0x120 - RISCV AXI PMU Write Bandwidth Register"]
129 #[inline(always)]
130 pub const fn riscv_axi_pmu_bw_wr(&self) -> &RISCV_AXI_PMU_BW_WR {
131 &self.riscv_axi_pmu_bw_wr
132 }
133}
134#[doc = "riscv_sta_add0 (rw) register accessor: RISCV Start Address0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_sta_add0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_sta_add0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_sta_add0`] module"]
135pub type RISCV_STA_ADD0 = crate::Reg<riscv_sta_add0::RISCV_STA_ADD0_SPEC>;
136#[doc = "RISCV Start Address0 Register"]
137pub mod riscv_sta_add0;
138#[doc = "riscv_sta_add1 (rw) register accessor: RISCV Start Address1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_sta_add1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_sta_add1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_sta_add1`] module"]
139pub type RISCV_STA_ADD1 = crate::Reg<riscv_sta_add1::RISCV_STA_ADD1_SPEC>;
140#[doc = "RISCV Start Address1 Register"]
141pub mod riscv_sta_add1;
142#[doc = "rf1p_cfg (rw) register accessor: RF1P Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rf1p_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rf1p_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf1p_cfg`] module"]
143pub type RF1P_CFG = crate::Reg<rf1p_cfg::RF1P_CFG_SPEC>;
144#[doc = "RF1P Configuration Register"]
145pub mod rf1p_cfg;
146#[doc = "rom_cfg (rw) register accessor: ROM Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_cfg`] module"]
147pub type ROM_CFG = crate::Reg<rom_cfg::ROM_CFG_SPEC>;
148#[doc = "ROM Configuration Register"]
149pub mod rom_cfg;
150#[doc = "wakeup_en (rw) register accessor: Wakeup Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_en`] module"]
151pub type WAKEUP_EN = crate::Reg<wakeup_en::WAKEUP_EN_SPEC>;
152#[doc = "Wakeup Enable Register"]
153pub mod wakeup_en;
154#[doc = "wakeup_mask (rw) register accessor: Wakeup Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_mask`] module"]
155pub type WAKEUP_MASK = crate::Reg<wakeup_mask::WAKEUP_MASK_SPEC>;
156#[doc = "Wakeup Mask Register"]
157pub mod wakeup_mask;
158#[doc = "ts_tmode_sel (rw) register accessor: Timestamp Test Mode Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_tmode_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_tmode_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ts_tmode_sel`] module"]
159pub type TS_TMODE_SEL = crate::Reg<ts_tmode_sel::TS_TMODE_SEL_SPEC>;
160#[doc = "Timestamp Test Mode Select Register"]
161pub mod ts_tmode_sel;
162#[doc = "sram_addr_twist (rw) register accessor: SRAM Address Twist Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_addr_twist::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_addr_twist::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_addr_twist`] module"]
163pub type SRAM_ADDR_TWIST = crate::Reg<sram_addr_twist::SRAM_ADDR_TWIST_SPEC>;
164#[doc = "SRAM Address Twist Register"]
165pub mod sram_addr_twist;
166#[doc = "work_mode (r) register accessor: Work Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`work_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@work_mode`] module"]
167pub type WORK_MODE = crate::Reg<work_mode::WORK_MODE_SPEC>;
168#[doc = "Work Mode Register"]
169pub mod work_mode;
170#[doc = "retite_pc0 (r) register accessor: Retire PC0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`retite_pc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retite_pc0`] module"]
171pub type RETITE_PC0 = crate::Reg<retite_pc0::RETITE_PC0_SPEC>;
172#[doc = "Retire PC0 Register"]
173pub mod retite_pc0;
174#[doc = "retite_pc1 (r) register accessor: Retire PC1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`retite_pc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retite_pc1`] module"]
175pub type RETITE_PC1 = crate::Reg<retite_pc1::RETITE_PC1_SPEC>;
176#[doc = "Retire PC1 Register"]
177pub mod retite_pc1;
178#[doc = "irq_mode (rw) register accessor: IRQ Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_mode`] module"]
179pub type IRQ_MODE = crate::Reg<irq_mode::IRQ_MODE_SPEC>;
180#[doc = "IRQ Mode Register"]
181pub mod irq_mode;
182#[doc = "riscv_axi_pmu_ctrl (rw) register accessor: RISCV AXI PMU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_axi_pmu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_ctrl`] module"]
183pub type RISCV_AXI_PMU_CTRL = crate::Reg<riscv_axi_pmu_ctrl::RISCV_AXI_PMU_CTRL_SPEC>;
184#[doc = "RISCV AXI PMU Control Register"]
185pub mod riscv_axi_pmu_ctrl;
186#[doc = "riscv_axi_pmu_prd (rw) register accessor: RISCV AXI PMU Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_prd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_axi_pmu_prd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_prd`] module"]
187pub type RISCV_AXI_PMU_PRD = crate::Reg<riscv_axi_pmu_prd::RISCV_AXI_PMU_PRD_SPEC>;
188#[doc = "RISCV AXI PMU Period Register"]
189pub mod riscv_axi_pmu_prd;
190#[doc = "riscv_axi_pmu_lat_rd (r) register accessor: RISCV AXI PMU Read Latency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_lat_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_lat_rd`] module"]
191pub type RISCV_AXI_PMU_LAT_RD = crate::Reg<riscv_axi_pmu_lat_rd::RISCV_AXI_PMU_LAT_RD_SPEC>;
192#[doc = "RISCV AXI PMU Read Latency Register"]
193pub mod riscv_axi_pmu_lat_rd;
194#[doc = "riscv_axi_pmu_lat_wr (r) register accessor: RISCV AXI PMU Write Latency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_lat_wr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_lat_wr`] module"]
195pub type RISCV_AXI_PMU_LAT_WR = crate::Reg<riscv_axi_pmu_lat_wr::RISCV_AXI_PMU_LAT_WR_SPEC>;
196#[doc = "RISCV AXI PMU Write Latency Register"]
197pub mod riscv_axi_pmu_lat_wr;
198#[doc = "riscv_axi_pmu_req_rd (r) register accessor: RISCV AXI PMU Read Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_req_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_req_rd`] module"]
199pub type RISCV_AXI_PMU_REQ_RD = crate::Reg<riscv_axi_pmu_req_rd::RISCV_AXI_PMU_REQ_RD_SPEC>;
200#[doc = "RISCV AXI PMU Read Request Register"]
201pub mod riscv_axi_pmu_req_rd;
202#[doc = "riscv_axi_pmu_req_wr (r) register accessor: RISCV AXI PMU Write Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_req_wr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_req_wr`] module"]
203pub type RISCV_AXI_PMU_REQ_WR = crate::Reg<riscv_axi_pmu_req_wr::RISCV_AXI_PMU_REQ_WR_SPEC>;
204#[doc = "RISCV AXI PMU Write Request Register"]
205pub mod riscv_axi_pmu_req_wr;
206#[doc = "riscv_axi_pmu_bw_rd (r) register accessor: RISCV AXI PMU Read Bandwidth Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_bw_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_bw_rd`] module"]
207pub type RISCV_AXI_PMU_BW_RD = crate::Reg<riscv_axi_pmu_bw_rd::RISCV_AXI_PMU_BW_RD_SPEC>;
208#[doc = "RISCV AXI PMU Read Bandwidth Register"]
209pub mod riscv_axi_pmu_bw_rd;
210#[doc = "riscv_axi_pmu_bw_wr (r) register accessor: RISCV AXI PMU Write Bandwidth Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_axi_pmu_bw_wr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_axi_pmu_bw_wr`] module"]
211pub type RISCV_AXI_PMU_BW_WR = crate::Reg<riscv_axi_pmu_bw_wr::RISCV_AXI_PMU_BW_WR_SPEC>;
212#[doc = "RISCV AXI PMU Write Bandwidth Register"]
213pub mod riscv_axi_pmu_bw_wr;