d1_pac/uart/
lcr.rs

1#[doc = "Register `lcr` reader"]
2pub type R = crate::R<LCR_SPEC>;
3#[doc = "Register `lcr` writer"]
4pub type W = crate::W<LCR_SPEC>;
5#[doc = "Field `dls` reader - Data Length Select"]
6pub type DLS_R = crate::FieldReader<DLS_A>;
7#[doc = "Data Length Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum DLS_A {
11    #[doc = "0: 5 bits"]
12    FIVE = 0,
13    #[doc = "1: 6 bits"]
14    SIX = 1,
15    #[doc = "2: 7 bits"]
16    SEVEN = 2,
17    #[doc = "3: 8 bits"]
18    EIGHT = 3,
19}
20impl From<DLS_A> for u8 {
21    #[inline(always)]
22    fn from(variant: DLS_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for DLS_A {
27    type Ux = u8;
28}
29impl DLS_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> DLS_A {
33        match self.bits {
34            0 => DLS_A::FIVE,
35            1 => DLS_A::SIX,
36            2 => DLS_A::SEVEN,
37            3 => DLS_A::EIGHT,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "5 bits"]
42    #[inline(always)]
43    pub fn is_five(&self) -> bool {
44        *self == DLS_A::FIVE
45    }
46    #[doc = "6 bits"]
47    #[inline(always)]
48    pub fn is_six(&self) -> bool {
49        *self == DLS_A::SIX
50    }
51    #[doc = "7 bits"]
52    #[inline(always)]
53    pub fn is_seven(&self) -> bool {
54        *self == DLS_A::SEVEN
55    }
56    #[doc = "8 bits"]
57    #[inline(always)]
58    pub fn is_eight(&self) -> bool {
59        *self == DLS_A::EIGHT
60    }
61}
62#[doc = "Field `dls` writer - Data Length Select"]
63pub type DLS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DLS_A>;
64impl<'a, REG> DLS_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "5 bits"]
70    #[inline(always)]
71    pub fn five(self) -> &'a mut crate::W<REG> {
72        self.variant(DLS_A::FIVE)
73    }
74    #[doc = "6 bits"]
75    #[inline(always)]
76    pub fn six(self) -> &'a mut crate::W<REG> {
77        self.variant(DLS_A::SIX)
78    }
79    #[doc = "7 bits"]
80    #[inline(always)]
81    pub fn seven(self) -> &'a mut crate::W<REG> {
82        self.variant(DLS_A::SEVEN)
83    }
84    #[doc = "8 bits"]
85    #[inline(always)]
86    pub fn eight(self) -> &'a mut crate::W<REG> {
87        self.variant(DLS_A::EIGHT)
88    }
89}
90#[doc = "Field `stop` reader - Number of stop bits"]
91pub type STOP_R = crate::BitReader<STOP_A>;
92#[doc = "Number of stop bits\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum STOP_A {
95    #[doc = "0: 1 stop bit"]
96    ONE = 0,
97    #[doc = "1: 1.5 stop bits when DLS(LCR\\[1:0\\]) is zero, else 2 stop bits"]
98    TWO = 1,
99}
100impl From<STOP_A> for bool {
101    #[inline(always)]
102    fn from(variant: STOP_A) -> Self {
103        variant as u8 != 0
104    }
105}
106impl STOP_R {
107    #[doc = "Get enumerated values variant"]
108    #[inline(always)]
109    pub const fn variant(&self) -> STOP_A {
110        match self.bits {
111            false => STOP_A::ONE,
112            true => STOP_A::TWO,
113        }
114    }
115    #[doc = "1 stop bit"]
116    #[inline(always)]
117    pub fn is_one(&self) -> bool {
118        *self == STOP_A::ONE
119    }
120    #[doc = "1.5 stop bits when DLS(LCR\\[1:0\\]) is zero, else 2 stop bits"]
121    #[inline(always)]
122    pub fn is_two(&self) -> bool {
123        *self == STOP_A::TWO
124    }
125}
126#[doc = "Field `stop` writer - Number of stop bits"]
127pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG, STOP_A>;
128impl<'a, REG> STOP_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    #[doc = "1 stop bit"]
133    #[inline(always)]
134    pub fn one(self) -> &'a mut crate::W<REG> {
135        self.variant(STOP_A::ONE)
136    }
137    #[doc = "1.5 stop bits when DLS(LCR\\[1:0\\]) is zero, else 2 stop bits"]
138    #[inline(always)]
139    pub fn two(self) -> &'a mut crate::W<REG> {
140        self.variant(STOP_A::TWO)
141    }
142}
143#[doc = "Field `pen` reader - Parity Enable"]
144pub type PEN_R = crate::BitReader<PEN_A>;
145#[doc = "Parity Enable\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum PEN_A {
148    #[doc = "0: `0`"]
149    DISABLED = 0,
150    #[doc = "1: `1`"]
151    ENABLED = 1,
152}
153impl From<PEN_A> for bool {
154    #[inline(always)]
155    fn from(variant: PEN_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl PEN_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub const fn variant(&self) -> PEN_A {
163        match self.bits {
164            false => PEN_A::DISABLED,
165            true => PEN_A::ENABLED,
166        }
167    }
168    #[doc = "`0`"]
169    #[inline(always)]
170    pub fn is_disabled(&self) -> bool {
171        *self == PEN_A::DISABLED
172    }
173    #[doc = "`1`"]
174    #[inline(always)]
175    pub fn is_enabled(&self) -> bool {
176        *self == PEN_A::ENABLED
177    }
178}
179#[doc = "Field `pen` writer - Parity Enable"]
180pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG, PEN_A>;
181impl<'a, REG> PEN_W<'a, REG>
182where
183    REG: crate::Writable + crate::RegisterSpec,
184{
185    #[doc = "`0`"]
186    #[inline(always)]
187    pub fn disabled(self) -> &'a mut crate::W<REG> {
188        self.variant(PEN_A::DISABLED)
189    }
190    #[doc = "`1`"]
191    #[inline(always)]
192    pub fn enabled(self) -> &'a mut crate::W<REG> {
193        self.variant(PEN_A::ENABLED)
194    }
195}
196#[doc = "Field `eps` reader - Even Parity Select"]
197pub type EPS_R = crate::FieldReader<EPS_A>;
198#[doc = "Even Parity Select\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200#[repr(u8)]
201pub enum EPS_A {
202    #[doc = "0: `0`"]
203    ODD = 0,
204    #[doc = "1: `1`"]
205    EVEN = 1,
206    #[doc = "2: `10`"]
207    RS485_DATA = 2,
208    #[doc = "3: `11`"]
209    RS485_ADDR = 3,
210}
211impl From<EPS_A> for u8 {
212    #[inline(always)]
213    fn from(variant: EPS_A) -> Self {
214        variant as _
215    }
216}
217impl crate::FieldSpec for EPS_A {
218    type Ux = u8;
219}
220impl EPS_R {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub const fn variant(&self) -> EPS_A {
224        match self.bits {
225            0 => EPS_A::ODD,
226            1 => EPS_A::EVEN,
227            2 => EPS_A::RS485_DATA,
228            3 => EPS_A::RS485_ADDR,
229            _ => unreachable!(),
230        }
231    }
232    #[doc = "`0`"]
233    #[inline(always)]
234    pub fn is_odd(&self) -> bool {
235        *self == EPS_A::ODD
236    }
237    #[doc = "`1`"]
238    #[inline(always)]
239    pub fn is_even(&self) -> bool {
240        *self == EPS_A::EVEN
241    }
242    #[doc = "`10`"]
243    #[inline(always)]
244    pub fn is_rs485_data(&self) -> bool {
245        *self == EPS_A::RS485_DATA
246    }
247    #[doc = "`11`"]
248    #[inline(always)]
249    pub fn is_rs485_addr(&self) -> bool {
250        *self == EPS_A::RS485_ADDR
251    }
252}
253#[doc = "Field `eps` writer - Even Parity Select"]
254pub type EPS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, EPS_A>;
255impl<'a, REG> EPS_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258    REG::Ux: From<u8>,
259{
260    #[doc = "`0`"]
261    #[inline(always)]
262    pub fn odd(self) -> &'a mut crate::W<REG> {
263        self.variant(EPS_A::ODD)
264    }
265    #[doc = "`1`"]
266    #[inline(always)]
267    pub fn even(self) -> &'a mut crate::W<REG> {
268        self.variant(EPS_A::EVEN)
269    }
270    #[doc = "`10`"]
271    #[inline(always)]
272    pub fn rs485_data(self) -> &'a mut crate::W<REG> {
273        self.variant(EPS_A::RS485_DATA)
274    }
275    #[doc = "`11`"]
276    #[inline(always)]
277    pub fn rs485_addr(self) -> &'a mut crate::W<REG> {
278        self.variant(EPS_A::RS485_ADDR)
279    }
280}
281#[doc = "Field `bc` reader - Break Control Bit"]
282pub type BC_R = crate::BitReader;
283#[doc = "Field `bc` writer - Break Control Bit"]
284pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>;
285#[doc = "Field `dlab` reader - Divisor Latch Access Bit"]
286pub type DLAB_R = crate::BitReader<DLAB_A>;
287#[doc = "Divisor Latch Access Bit\n\nValue on reset: 0"]
288#[derive(Clone, Copy, Debug, PartialEq, Eq)]
289pub enum DLAB_A {
290    #[doc = "0: `0`"]
291    RX_BUFFER = 0,
292    #[doc = "1: `1`"]
293    DIVISOR_LATCH = 1,
294}
295impl From<DLAB_A> for bool {
296    #[inline(always)]
297    fn from(variant: DLAB_A) -> Self {
298        variant as u8 != 0
299    }
300}
301impl DLAB_R {
302    #[doc = "Get enumerated values variant"]
303    #[inline(always)]
304    pub const fn variant(&self) -> DLAB_A {
305        match self.bits {
306            false => DLAB_A::RX_BUFFER,
307            true => DLAB_A::DIVISOR_LATCH,
308        }
309    }
310    #[doc = "`0`"]
311    #[inline(always)]
312    pub fn is_rx_buffer(&self) -> bool {
313        *self == DLAB_A::RX_BUFFER
314    }
315    #[doc = "`1`"]
316    #[inline(always)]
317    pub fn is_divisor_latch(&self) -> bool {
318        *self == DLAB_A::DIVISOR_LATCH
319    }
320}
321#[doc = "Field `dlab` writer - Divisor Latch Access Bit"]
322pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG, DLAB_A>;
323impl<'a, REG> DLAB_W<'a, REG>
324where
325    REG: crate::Writable + crate::RegisterSpec,
326{
327    #[doc = "`0`"]
328    #[inline(always)]
329    pub fn rx_buffer(self) -> &'a mut crate::W<REG> {
330        self.variant(DLAB_A::RX_BUFFER)
331    }
332    #[doc = "`1`"]
333    #[inline(always)]
334    pub fn divisor_latch(self) -> &'a mut crate::W<REG> {
335        self.variant(DLAB_A::DIVISOR_LATCH)
336    }
337}
338impl R {
339    #[doc = "Bits 0:1 - Data Length Select"]
340    #[inline(always)]
341    pub fn dls(&self) -> DLS_R {
342        DLS_R::new((self.bits & 3) as u8)
343    }
344    #[doc = "Bit 2 - Number of stop bits"]
345    #[inline(always)]
346    pub fn stop(&self) -> STOP_R {
347        STOP_R::new(((self.bits >> 2) & 1) != 0)
348    }
349    #[doc = "Bit 3 - Parity Enable"]
350    #[inline(always)]
351    pub fn pen(&self) -> PEN_R {
352        PEN_R::new(((self.bits >> 3) & 1) != 0)
353    }
354    #[doc = "Bits 4:5 - Even Parity Select"]
355    #[inline(always)]
356    pub fn eps(&self) -> EPS_R {
357        EPS_R::new(((self.bits >> 4) & 3) as u8)
358    }
359    #[doc = "Bit 6 - Break Control Bit"]
360    #[inline(always)]
361    pub fn bc(&self) -> BC_R {
362        BC_R::new(((self.bits >> 6) & 1) != 0)
363    }
364    #[doc = "Bit 7 - Divisor Latch Access Bit"]
365    #[inline(always)]
366    pub fn dlab(&self) -> DLAB_R {
367        DLAB_R::new(((self.bits >> 7) & 1) != 0)
368    }
369}
370impl W {
371    #[doc = "Bits 0:1 - Data Length Select"]
372    #[inline(always)]
373    #[must_use]
374    pub fn dls(&mut self) -> DLS_W<LCR_SPEC> {
375        DLS_W::new(self, 0)
376    }
377    #[doc = "Bit 2 - Number of stop bits"]
378    #[inline(always)]
379    #[must_use]
380    pub fn stop(&mut self) -> STOP_W<LCR_SPEC> {
381        STOP_W::new(self, 2)
382    }
383    #[doc = "Bit 3 - Parity Enable"]
384    #[inline(always)]
385    #[must_use]
386    pub fn pen(&mut self) -> PEN_W<LCR_SPEC> {
387        PEN_W::new(self, 3)
388    }
389    #[doc = "Bits 4:5 - Even Parity Select"]
390    #[inline(always)]
391    #[must_use]
392    pub fn eps(&mut self) -> EPS_W<LCR_SPEC> {
393        EPS_W::new(self, 4)
394    }
395    #[doc = "Bit 6 - Break Control Bit"]
396    #[inline(always)]
397    #[must_use]
398    pub fn bc(&mut self) -> BC_W<LCR_SPEC> {
399        BC_W::new(self, 6)
400    }
401    #[doc = "Bit 7 - Divisor Latch Access Bit"]
402    #[inline(always)]
403    #[must_use]
404    pub fn dlab(&mut self) -> DLAB_W<LCR_SPEC> {
405        DLAB_W::new(self, 7)
406    }
407    #[doc = r" Writes raw bits to the register."]
408    #[doc = r""]
409    #[doc = r" # Safety"]
410    #[doc = r""]
411    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
412    #[inline(always)]
413    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
414        self.bits = bits;
415        self
416    }
417}
418#[doc = "UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
419pub struct LCR_SPEC;
420impl crate::RegisterSpec for LCR_SPEC {
421    type Ux = u32;
422}
423#[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
424impl crate::Readable for LCR_SPEC {}
425#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
426impl crate::Writable for LCR_SPEC {
427    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
428    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
429}
430#[doc = "`reset()` method sets lcr to value 0"]
431impl crate::Resettable for LCR_SPEC {
432    const RESET_VALUE: Self::Ux = 0;
433}
d1_pac/uart/lcr.rs

d1_pac/uart/
lcr.rs
