cyt4dn_b 0.0.1

Peripheral access crate for cyt4dn_b T2G family
Documentation 
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#[doc = "Register `TX_RX_STATUS` reader"]
pub struct R(crate::R<TX_RX_STATUS_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<TX_RX_STATUS_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<TX_RX_STATUS_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<TX_RX_STATUS_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `TX_RX_STATUS` writer"]
pub struct W(crate::W<TX_RX_STATUS_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<TX_RX_STATUS_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<TX_RX_STATUS_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<TX_RX_STATUS_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `SYNC_COUNTER` reader - Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each). - If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased. - If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased. The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of \\[106, 152\\]. Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization."]
pub type SYNC_COUNTER_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TX_IN` reader - LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality."]
pub type TX_IN_R = crate::BitReader<bool>;
#[doc = "Field `RX_IN` reader - LIN receiver input ('rx_in', 'lin_rx_in' in functional mode)."]
pub type RX_IN_R = crate::BitReader<bool>;
#[doc = "Field `TX_OUT` reader - LIN transmitter output ('tx_out', 'lin_tx_out')."]
pub type TX_OUT_R = crate::BitReader<bool>;
#[doc = "Field `EN_OUT` reader - LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers."]
pub type EN_OUT_R = crate::BitReader<bool>;
#[doc = "Field `EN_OUT` writer - LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers."]
pub type EN_OUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TX_RX_STATUS_SPEC, bool, O>;
impl R {
    #[doc = "Bits 0:7 - Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each). - If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased. - If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased. The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of \\[106, 152\\]. Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization."]
    #[inline(always)]
    pub fn sync_counter(&self) -> SYNC_COUNTER_R {
        SYNC_COUNTER_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bit 16 - LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality."]
    #[inline(always)]
    pub fn tx_in(&self) -> TX_IN_R {
        TX_IN_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17 - LIN receiver input ('rx_in', 'lin_rx_in' in functional mode)."]
    #[inline(always)]
    pub fn rx_in(&self) -> RX_IN_R {
        RX_IN_R::new(((self.bits >> 17) & 1) != 0)
    }
    #[doc = "Bit 24 - LIN transmitter output ('tx_out', 'lin_tx_out')."]
    #[inline(always)]
    pub fn tx_out(&self) -> TX_OUT_R {
        TX_OUT_R::new(((self.bits >> 24) & 1) != 0)
    }
    #[doc = "Bit 26 - LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers."]
    #[inline(always)]
    pub fn en_out(&self) -> EN_OUT_R {
        EN_OUT_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 26 - LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers."]
    #[inline(always)]
    #[must_use]
    pub fn en_out(&mut self) -> EN_OUT_W<26> {
        EN_OUT_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "TX/RX status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_rx_status](index.html) module"]
pub struct TX_RX_STATUS_SPEC;
impl crate::RegisterSpec for TX_RX_STATUS_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [tx_rx_status::R](R) reader structure"]
impl crate::Readable for TX_RX_STATUS_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [tx_rx_status::W](W) writer structure"]
impl crate::Writable for TX_RX_STATUS_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TX_RX_STATUS to value 0x0500_0000"]
impl crate::Resettable for TX_RX_STATUS_SPEC {
    const RESET_VALUE: Self::Ux = 0x0500_0000;
}