cyt4dn_b 0.0.1

Peripheral access crate for cyt4dn_b T2G family
Documentation 
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#[doc = "Register `SPEC_ADD5_BOTTOM` reader"]
pub struct R(crate::R<SPEC_ADD5_BOTTOM_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<SPEC_ADD5_BOTTOM_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<SPEC_ADD5_BOTTOM_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<SPEC_ADD5_BOTTOM_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Field `RSVD_31_0` reader - Write ignore, read 0"]
pub type RSVD_31_0_R = crate::FieldReader<u32, u32>;
impl R {
    #[doc = "Bits 0:31 - Write ignore, read 0"]
    #[inline(always)]
    pub fn rsvd_31_0(&self) -> RSVD_31_0_R {
        RSVD_31_0_R::new(self.bits)
    }
}
#[doc = "Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spec_add5_bottom](index.html) module"]
pub struct SPEC_ADD5_BOTTOM_SPEC;
impl crate::RegisterSpec for SPEC_ADD5_BOTTOM_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [spec_add5_bottom::R](R) reader structure"]
impl crate::Readable for SPEC_ADD5_BOTTOM_SPEC {
    type Reader = R;
}
#[doc = "`reset()` method sets SPEC_ADD5_BOTTOM to value 0"]
impl crate::Resettable for SPEC_ADD5_BOTTOM_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}