cyt4dn_b 0.0.1

Peripheral access crate for cyt4dn_b T2G family
Documentation 
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#[doc = "Register `DLP_CTL` reader"]
pub struct R(crate::R<DLP_CTL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DLP_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<DLP_CTL_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<DLP_CTL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DLP_CTL` writer"]
pub struct W(crate::W<DLP_CTL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DLP_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<DLP_CTL_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<DLP_CTL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `DLP` reader - Data Learning Pattern"]
pub type DLP_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DLP` writer - Data Learning Pattern"]
pub type DLP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLP_CTL_SPEC, u16, u16, 16, O>;
#[doc = "Field `DLP_SIZE` reader - Size of data learning pattern as such: '0': 1 bit ... '15': 16 bit. If CTL2.RX_CAPTURE_MODE=1 then the DLP_SIZE+1 LSBs of the expected data learning pattern (DLP\\[DLP_SIZE:0\\]) are compared with the data learning pattern generated by the memory device and captured during the last latency / dummy cycles of a memory read transfer. Note: For DDR read data transfers the size of the DLP must be an even number, i.e. DLP_SIZE must be an odd number."]
pub type DLP_SIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DLP_SIZE` writer - Size of data learning pattern as such: '0': 1 bit ... '15': 16 bit. If CTL2.RX_CAPTURE_MODE=1 then the DLP_SIZE+1 LSBs of the expected data learning pattern (DLP\\[DLP_SIZE:0\\]) are compared with the data learning pattern generated by the memory device and captured during the last latency / dummy cycles of a memory read transfer. Note: For DDR read data transfers the size of the DLP must be an even number, i.e. DLP_SIZE must be an odd number."]
pub type DLP_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLP_CTL_SPEC, u8, u8, 4, O>;
#[doc = "Field `DLP_WARNING_LEVEL` reader - Determines when the DLP_WARNING interrupt cause field is set: - DLP_WARNING is set when the number of delay line taps resulting to a correctly captured DLP is less than DLP_WARNING_LEVEL for at least one input data line Note: To provide a margin in both directions relatively to the selected middle tap at least 3 delay line taps have to result into a correctly captured DLP, i.e. the DLP_WARNING_LEVEL has to be set to greater or equal 3."]
pub type DLP_WARNING_LEVEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DLP_WARNING_LEVEL` writer - Determines when the DLP_WARNING interrupt cause field is set: - DLP_WARNING is set when the number of delay line taps resulting to a correctly captured DLP is less than DLP_WARNING_LEVEL for at least one input data line Note: To provide a margin in both directions relatively to the selected middle tap at least 3 delay line taps have to result into a correctly captured DLP, i.e. the DLP_WARNING_LEVEL has to be set to greater or equal 3."]
pub type DLP_WARNING_LEVEL_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, DLP_CTL_SPEC, u8, u8, 4, O>;
impl R {
    #[doc = "Bits 0:15 - Data Learning Pattern"]
    #[inline(always)]
    pub fn dlp(&self) -> DLP_R {
        DLP_R::new((self.bits & 0xffff) as u16)
    }
    #[doc = "Bits 16:19 - Size of data learning pattern as such: '0': 1 bit ... '15': 16 bit. If CTL2.RX_CAPTURE_MODE=1 then the DLP_SIZE+1 LSBs of the expected data learning pattern (DLP\\[DLP_SIZE:0\\]) are compared with the data learning pattern generated by the memory device and captured during the last latency / dummy cycles of a memory read transfer. Note: For DDR read data transfers the size of the DLP must be an even number, i.e. DLP_SIZE must be an odd number."]
    #[inline(always)]
    pub fn dlp_size(&self) -> DLP_SIZE_R {
        DLP_SIZE_R::new(((self.bits >> 16) & 0x0f) as u8)
    }
    #[doc = "Bits 24:27 - Determines when the DLP_WARNING interrupt cause field is set: - DLP_WARNING is set when the number of delay line taps resulting to a correctly captured DLP is less than DLP_WARNING_LEVEL for at least one input data line Note: To provide a margin in both directions relatively to the selected middle tap at least 3 delay line taps have to result into a correctly captured DLP, i.e. the DLP_WARNING_LEVEL has to be set to greater or equal 3."]
    #[inline(always)]
    pub fn dlp_warning_level(&self) -> DLP_WARNING_LEVEL_R {
        DLP_WARNING_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8)
    }
}
impl W {
    #[doc = "Bits 0:15 - Data Learning Pattern"]
    #[inline(always)]
    #[must_use]
    pub fn dlp(&mut self) -> DLP_W<0> {
        DLP_W::new(self)
    }
    #[doc = "Bits 16:19 - Size of data learning pattern as such: '0': 1 bit ... '15': 16 bit. If CTL2.RX_CAPTURE_MODE=1 then the DLP_SIZE+1 LSBs of the expected data learning pattern (DLP\\[DLP_SIZE:0\\]) are compared with the data learning pattern generated by the memory device and captured during the last latency / dummy cycles of a memory read transfer. Note: For DDR read data transfers the size of the DLP must be an even number, i.e. DLP_SIZE must be an odd number."]
    #[inline(always)]
    #[must_use]
    pub fn dlp_size(&mut self) -> DLP_SIZE_W<16> {
        DLP_SIZE_W::new(self)
    }
    #[doc = "Bits 24:27 - Determines when the DLP_WARNING interrupt cause field is set: - DLP_WARNING is set when the number of delay line taps resulting to a correctly captured DLP is less than DLP_WARNING_LEVEL for at least one input data line Note: To provide a margin in both directions relatively to the selected middle tap at least 3 delay line taps have to result into a correctly captured DLP, i.e. the DLP_WARNING_LEVEL has to be set to greater or equal 3."]
    #[inline(always)]
    #[must_use]
    pub fn dlp_warning_level(&mut self) -> DLP_WARNING_LEVEL_W<24> {
        DLP_WARNING_LEVEL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "DLP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlp_ctl](index.html) module"]
pub struct DLP_CTL_SPEC;
impl crate::RegisterSpec for DLP_CTL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [dlp_ctl::R](R) reader structure"]
impl crate::Readable for DLP_CTL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dlp_ctl::W](W) writer structure"]
impl crate::Writable for DLP_CTL_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DLP_CTL to value 0x0307_0000"]
impl crate::Resettable for DLP_CTL_SPEC {
    const RESET_VALUE: Self::Ux = 0x0307_0000;
}