#[doc = "Register `DIV_24_5_CTL[%s]` reader"]
pub struct R(crate::R<DIV_24_5_CTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIV_24_5_CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIV_24_5_CTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIV_24_5_CTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DIV_24_5_CTL[%s]` writer"]
pub struct W(crate::W<DIV_24_5_CTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DIV_24_5_CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DIV_24_5_CTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DIV_24_5_CTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `FRAC5_DIV` reader - Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root\\[i\\]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
pub type FRAC5_DIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FRAC5_DIV` writer - Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root\\[i\\]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
pub type FRAC5_DIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DIV_24_5_CTL_SPEC, u8, u8, 5, O>;
#[doc = "Field `INT24_DIV` reader - Integer division by (1+INT24_DIV). Allows for integer divisions in the range \\[1, 16,777,216\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 16,777,216 31/32\\]
in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to \\[2, 16,777,216 31/32\\]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 16,777,216\\]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
pub type INT24_DIV_R = crate::FieldReader<u32, u32>;
#[doc = "Field `INT24_DIV` writer - Integer division by (1+INT24_DIV). Allows for integer divisions in the range \\[1, 16,777,216\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 16,777,216 31/32\\]
in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to \\[2, 16,777,216 31/32\\]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 16,777,216\\]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
pub type INT24_DIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DIV_24_5_CTL_SPEC, u32, u32, 24, O>;
impl R {
#[doc = "Bit 0 - Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 3:7 - Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root\\[i\\]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn frac5_div(&self) -> FRAC5_DIV_R {
FRAC5_DIV_R::new(((self.bits >> 3) & 0x1f) as u8)
}
#[doc = "Bits 8:31 - Integer division by (1+INT24_DIV). Allows for integer divisions in the range \\[1, 16,777,216\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 16,777,216 31/32\\]
in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to \\[2, 16,777,216 31/32\\]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 16,777,216\\]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int24_div(&self) -> INT24_DIV_R {
INT24_DIV_R::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 3:7 - Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root\\[i\\]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
#[must_use]
pub fn frac5_div(&mut self) -> FRAC5_DIV_W<3> {
FRAC5_DIV_W::new(self)
}
#[doc = "Bits 8:31 - Integer division by (1+INT24_DIV). Allows for integer divisions in the range \\[1, 16,777,216\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 16,777,216 31/32\\]
in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to \\[2, 16,777,216 31/32\\]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 16,777,216\\]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
#[must_use]
pub fn int24_div(&mut self) -> INT24_DIV_W<8> {
INT24_DIV_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Divider control (for 24.5 divider)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div_24_5_ctl](index.html) module"]
pub struct DIV_24_5_CTL_SPEC;
impl crate::RegisterSpec for DIV_24_5_CTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [div_24_5_ctl::R](R) reader structure"]
impl crate::Readable for DIV_24_5_CTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [div_24_5_ctl::W](W) writer structure"]
impl crate::Writable for DIV_24_5_CTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DIV_24_5_CTL[%s]
to value 0"]
impl crate::Resettable for DIV_24_5_CTL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}