cyt4dn_b/m0/eth0/
designcfg_debug5.rs

1#[doc = "Register `DESIGNCFG_DEBUG5` reader"]
2pub struct R(crate::R<DESIGNCFG_DEBUG5_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DESIGNCFG_DEBUG5_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DESIGNCFG_DEBUG5_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DESIGNCFG_DEBUG5_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RX_FIFO_CNT_WIDTH` reader - Takes the value of the `gem_rx_fifo_cnt_width DEFINE"]
17pub type RX_FIFO_CNT_WIDTH_R = crate::FieldReader<u8, u8>;
18#[doc = "Field `TX_FIFO_CNT_WIDTH` reader - Takes the value of the `gem_tx_fifo_cnt_width DEFINE"]
19pub type TX_FIFO_CNT_WIDTH_R = crate::FieldReader<u8, u8>;
20#[doc = "Field `TSU` reader - Takes the value of the `gem_tsu DEFINE"]
21pub type TSU_R = crate::BitReader<bool>;
22#[doc = "Field `PHY_IDENT` reader - Takes the value of the `gem_phy_ident DEFINE"]
23pub type PHY_IDENT_R = crate::BitReader<bool>;
24#[doc = "Field `DMA_BUS_WIDTH_DEF` reader - Takes the value of the `gem_dma_bus_width_def DEFINE"]
25pub type DMA_BUS_WIDTH_DEF_R = crate::FieldReader<u8, u8>;
26#[doc = "Field `MDC_CLOCK_DIV` reader - Takes the value of the `gem_mdc_clock_div DEFINE"]
27pub type MDC_CLOCK_DIV_R = crate::FieldReader<u8, u8>;
28#[doc = "Field `ENDIAN_SWAP_DEF` reader - Takes the value of the `gem_endian_swap_def DEFINE"]
29pub type ENDIAN_SWAP_DEF_R = crate::FieldReader<u8, u8>;
30#[doc = "Field `RX_PBUF_SIZE_DEF` reader - Takes the value of the `gem_rx_pbuf_size_def DEFINE"]
31pub type RX_PBUF_SIZE_DEF_R = crate::FieldReader<u8, u8>;
32#[doc = "Field `TX_PBUF_SIZE_DEF` reader - Takes the value of the `gem_tx_pbuf_size_def DEFINE"]
33pub type TX_PBUF_SIZE_DEF_R = crate::BitReader<bool>;
34#[doc = "Field `RX_BUFFER_LENGTH_DEF` reader - Takes the value of the `gem_rx_buffer_length_def DEFINE"]
35pub type RX_BUFFER_LENGTH_DEF_R = crate::FieldReader<u8, u8>;
36#[doc = "Field `TSU_CLK` reader - Takes the value of the `gem_tsu_clk DEFINE"]
37pub type TSU_CLK_R = crate::BitReader<bool>;
38#[doc = "Field `AXI_PROT_VALUE` reader - Takes the value of the `gem_axi_prot_value DEFINE"]
39pub type AXI_PROT_VALUE_R = crate::FieldReader<u8, u8>;
40impl R {
41    #[doc = "Bits 0:3 - Takes the value of the `gem_rx_fifo_cnt_width DEFINE"]
42    #[inline(always)]
43    pub fn rx_fifo_cnt_width(&self) -> RX_FIFO_CNT_WIDTH_R {
44        RX_FIFO_CNT_WIDTH_R::new((self.bits & 0x0f) as u8)
45    }
46    #[doc = "Bits 4:7 - Takes the value of the `gem_tx_fifo_cnt_width DEFINE"]
47    #[inline(always)]
48    pub fn tx_fifo_cnt_width(&self) -> TX_FIFO_CNT_WIDTH_R {
49        TX_FIFO_CNT_WIDTH_R::new(((self.bits >> 4) & 0x0f) as u8)
50    }
51    #[doc = "Bit 8 - Takes the value of the `gem_tsu DEFINE"]
52    #[inline(always)]
53    pub fn tsu(&self) -> TSU_R {
54        TSU_R::new(((self.bits >> 8) & 1) != 0)
55    }
56    #[doc = "Bit 9 - Takes the value of the `gem_phy_ident DEFINE"]
57    #[inline(always)]
58    pub fn phy_ident(&self) -> PHY_IDENT_R {
59        PHY_IDENT_R::new(((self.bits >> 9) & 1) != 0)
60    }
61    #[doc = "Bits 10:11 - Takes the value of the `gem_dma_bus_width_def DEFINE"]
62    #[inline(always)]
63    pub fn dma_bus_width_def(&self) -> DMA_BUS_WIDTH_DEF_R {
64        DMA_BUS_WIDTH_DEF_R::new(((self.bits >> 10) & 3) as u8)
65    }
66    #[doc = "Bits 12:14 - Takes the value of the `gem_mdc_clock_div DEFINE"]
67    #[inline(always)]
68    pub fn mdc_clock_div(&self) -> MDC_CLOCK_DIV_R {
69        MDC_CLOCK_DIV_R::new(((self.bits >> 12) & 7) as u8)
70    }
71    #[doc = "Bits 15:16 - Takes the value of the `gem_endian_swap_def DEFINE"]
72    #[inline(always)]
73    pub fn endian_swap_def(&self) -> ENDIAN_SWAP_DEF_R {
74        ENDIAN_SWAP_DEF_R::new(((self.bits >> 15) & 3) as u8)
75    }
76    #[doc = "Bits 17:18 - Takes the value of the `gem_rx_pbuf_size_def DEFINE"]
77    #[inline(always)]
78    pub fn rx_pbuf_size_def(&self) -> RX_PBUF_SIZE_DEF_R {
79        RX_PBUF_SIZE_DEF_R::new(((self.bits >> 17) & 3) as u8)
80    }
81    #[doc = "Bit 19 - Takes the value of the `gem_tx_pbuf_size_def DEFINE"]
82    #[inline(always)]
83    pub fn tx_pbuf_size_def(&self) -> TX_PBUF_SIZE_DEF_R {
84        TX_PBUF_SIZE_DEF_R::new(((self.bits >> 19) & 1) != 0)
85    }
86    #[doc = "Bits 20:27 - Takes the value of the `gem_rx_buffer_length_def DEFINE"]
87    #[inline(always)]
88    pub fn rx_buffer_length_def(&self) -> RX_BUFFER_LENGTH_DEF_R {
89        RX_BUFFER_LENGTH_DEF_R::new(((self.bits >> 20) & 0xff) as u8)
90    }
91    #[doc = "Bit 28 - Takes the value of the `gem_tsu_clk DEFINE"]
92    #[inline(always)]
93    pub fn tsu_clk(&self) -> TSU_CLK_R {
94        TSU_CLK_R::new(((self.bits >> 28) & 1) != 0)
95    }
96    #[doc = "Bits 29:31 - Takes the value of the `gem_axi_prot_value DEFINE"]
97    #[inline(always)]
98    pub fn axi_prot_value(&self) -> AXI_PROT_VALUE_R {
99        AXI_PROT_VALUE_R::new(((self.bits >> 29) & 7) as u8)
100    }
101}
102#[doc = "Design Configuration Register 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [designcfg_debug5](index.html) module"]
103pub struct DESIGNCFG_DEBUG5_SPEC;
104impl crate::RegisterSpec for DESIGNCFG_DEBUG5_SPEC {
105    type Ux = u32;
106}
107#[doc = "`read()` method returns [designcfg_debug5::R](R) reader structure"]
108impl crate::Readable for DESIGNCFG_DEBUG5_SPEC {
109    type Reader = R;
110}
111#[doc = "`reset()` method sets DESIGNCFG_DEBUG5 to value 0x502e_2744"]
112impl crate::Resettable for DESIGNCFG_DEBUG5_SPEC {
113    const RESET_VALUE: Self::Ux = 0x502e_2744;
114}
cyt4dn_b/m0/eth0/designcfg_debug5.rs

cyt4dn_b/m0/eth0/
designcfg_debug5.rs
