ct2rs 0.9.19

Rust bindings for OpenNMT/CTranslate2
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

#pragma once

#include <string>

namespace ctranslate2 {
  namespace cpu {

    enum class CpuIsa {
      GENERIC,
#if defined(CT2_X86_BUILD)
      AVX,
      AVX2,
      AVX512,
#elif defined(CT2_ARM64_BUILD)
      NEON,
#endif
    };

    std::string isa_to_str(CpuIsa isa);

    // Returns the CPU ISA to dispatch to.
    CpuIsa get_cpu_isa();

  }
}

#define CPU_ISA_CASE(CPU_ISA, STMTS)            \
  case CPU_ISA: {                               \
    constexpr cpu::CpuIsa ISA = CPU_ISA;        \
    STMTS;                                      \
    break;                                      \
  }

#define CPU_ISA_DEFAULT(CPU_ISA, STMTS)                 \
  default: {                                            \
    constexpr cpu::CpuIsa ISA = CPU_ISA;                \
    STMTS;                                              \
    break;                                              \
  }

#define SINGLE_ARG(...) __VA_ARGS__
#ifdef CT2_WITH_CPU_DISPATCH
#if defined(CT2_X86_BUILD)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_CASE(cpu::CpuIsa::AVX512, SINGLE_ARG(STMTS))      \
    CPU_ISA_CASE(cpu::CpuIsa::AVX2, SINGLE_ARG(STMTS))        \
    CPU_ISA_CASE(cpu::CpuIsa::AVX, SINGLE_ARG(STMTS))         \
    CPU_ISA_DEFAULT(cpu::CpuIsa::GENERIC, SINGLE_ARG(STMTS))  \
  }
#elif defined(CT2_ARM64_BUILD)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_CASE(cpu::CpuIsa::NEON, SINGLE_ARG(STMTS))        \
    CPU_ISA_DEFAULT(cpu::CpuIsa::GENERIC, SINGLE_ARG(STMTS))  \
  }
#endif
#elif defined(__AVX512F__)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_DEFAULT(cpu::CpuIsa::AVX512, SINGLE_ARG(STMTS))   \
  }
#elif defined(__AVX2__)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_DEFAULT(cpu::CpuIsa::AVX2, SINGLE_ARG(STMTS))     \
  }
#elif defined(__AVX__)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_DEFAULT(cpu::CpuIsa::AVX, SINGLE_ARG(STMTS))      \
  }
#elif defined(__ARM_NEON)
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_DEFAULT(cpu::CpuIsa::NEON, SINGLE_ARG(STMTS))     \
  }
#else
#  define CPU_ISA_DISPATCH(STMTS)                             \
  switch (cpu::get_cpu_isa()) {                               \
    CPU_ISA_DEFAULT(cpu::CpuIsa::GENERIC, SINGLE_ARG(STMTS))  \
  }
#endif