;; GENERATED BY `isaspec`. DO NOT EDIT!!!
(attr MInst.MovFromVec (tag isaspec_generated))
(spec
(MInst.MovFromVec rd rn idx size)
(provide
(match
size
((Size64) (= rd (extract 63 0 (as rn (bv 64)))))
((Size32)
(and
(=> (= idx #x00) (= rd (zero_ext 64 (extract 31 0 (as rn (bv 64))))))
(=> (= idx #x01) (= rd (zero_ext 64 (extract 63 32 (as rn (bv 64))))))
)
)
((Size16)
(and
(=> (= idx #x00) (= rd (zero_ext 64 (extract 15 0 (as rn (bv 64))))))
(=> (= idx #x01) (= rd (zero_ext 64 (extract 31 16 (as rn (bv 64))))))
(=> (= idx #x02) (= rd (zero_ext 64 (extract 47 32 (as rn (bv 64))))))
(=> (= idx #x03) (= rd (zero_ext 64 (extract 63 48 (as rn (bv 64))))))
)
)
((Size8)
(and
(=> (= idx #x00) (= rd (zero_ext 64 (extract 7 0 (as rn (bv 64))))))
(=> (= idx #x01) (= rd (zero_ext 64 (extract 15 8 (as rn (bv 64))))))
(=> (= idx #x02) (= rd (zero_ext 64 (extract 23 16 (as rn (bv 64))))))
(=> (= idx #x03) (= rd (zero_ext 64 (extract 31 24 (as rn (bv 64))))))
(=> (= idx #x04) (= rd (zero_ext 64 (extract 39 32 (as rn (bv 64))))))
(=> (= idx #x05) (= rd (zero_ext 64 (extract 47 40 (as rn (bv 64))))))
(=> (= idx #x06) (= rd (zero_ext 64 (extract 55 48 (as rn (bv 64))))))
(=> (= idx #x07) (= rd (zero_ext 64 (extract 63 56 (as rn (bv 64))))))
)
)
)
)
(require
(match
size
((Size64) (= idx #x00))
((Size32) (or (= idx #x00) (= idx #x01)))
((Size16) (or (= idx #x00) (= idx #x01) (= idx #x02) (= idx #x03)))
((Size8) (or (= idx #x00) (= idx #x01) (= idx #x02) (= idx #x03) (= idx #x04) (= idx #x05) (= idx #x06) (= idx #x07)))
)
)
)