cpudetect 0.1.0

//! CPU feature detection helpers for x86_64/AMD64 CPUs.

use pastey::paste;

macro_rules! x86_64_feature {
    ($feature:literal) => {
        x86_64_feature!($feature, $feature);
    };
    ($feature:literal, $fn_suffix:literal) => {
        paste! {
            #[doc = concat!(
                "Returns `true` if the current machine supports the ",
                $feature,
                " instruction set."
            )]
            #[cfg(all(feature = "enabled", target_feature = $feature))]
            #[must_use]
            #[inline(always)]
            pub fn [<has_ $fn_suffix>]() -> bool {
                true
            }

            #[doc = concat!(
                "Returns `true` if the current machine supports the ",
                $feature,
                " instruction set."
            )]
            #[cfg(all(feature = "enabled", not(target_feature = $feature)))]
            #[must_use]
            #[inline(always)]
            pub fn [<has_ $fn_suffix>]() -> bool {
                is_x86_feature_detected!($feature)
            }

            #[doc = concat!(
                "Returns `true` if the current machine supports the ",
                $feature,
                " instruction set."
            )]
            #[cfg(not(feature = "enabled"))]
            #[must_use]
            #[inline(always)]
            pub fn [<has_ $fn_suffix>]() -> bool {
                false
            }
        }
    };
}

// SSE instruction sets

// Enable SSE instructions.
x86_64_feature!("sse");

// Enable SSE2 instructions.
x86_64_feature!("sse2");

// Enable SSE3 instructions.
x86_64_feature!("sse3");

// Enable SSE 4.1 instructions.
x86_64_feature!("sse4.1", "sse4_1");

// Enable SSE 4.2 instructions.
x86_64_feature!("sse4.2", "sse4_2");

// Support SSE 4a instructions. Note that these are AMD-specific SSE4 extensions that are NOT assumed by future extension sets.
x86_64_feature!("sse4a");

// Enable SSSE3 instructions.
x86_64_feature!("ssse3");

// ---

// Enable AES instructions. Implies SSE2 and earlier.
x86_64_feature!("aes");

// Enable Galois Field Arithmetic Instructions. Implies SSE2 and earlier.
x86_64_feature!("gfni");

// Enable packed carry-less multiplication instructions. Implies SSE2 and earlier.
x86_64_feature!("pclmulqdq");

// Enable SHA instructions. Implies SSE2 and earlier.
x86_64_feature!("sha");

// Enable AVX instructions. Implies all SSE sets.
x86_64_feature!("avx");

// Support 16-bit floating point conversion instructions. Implies AVX and earlier sets.
x86_64_feature!("f16c");

// Enable three-operand fused multiple-add. Implies AVX and earlier sets.
x86_64_feature!("fma");

// Enable vpclmulqdq instructions. Implies AVX and earlier sets.
x86_64_feature!("vpclmulqdq");

// Enable AVX2 instructions. Implies AVX and earlier sets.
x86_64_feature!("avx2");

// ---

// AVX-512 instructions. These imply AVX2 and earlier sets.

// Support bfloat16 floating point.
x86_64_feature!("avx512bf16");

// Enable AVX-512 Bit Algorithms.
x86_64_feature!("avx512bitalg");

// Enable AVX-512 Byte and Word Instructions.
x86_64_feature!("avx512bw");

// Enable AVX-512 Conflict Detection Instructions.
x86_64_feature!("avx512cd");

// Enable AVX-512 Doubleword and Quadword Instructions.
x86_64_feature!("avx512dq");

// Enable AVX-512 instructions.
x86_64_feature!("avx512f");

// Support 16-bit floating point.
x86_64_feature!("avx512fp16");

// Enable AVX-512 Integer Fused Multiple-Add.
x86_64_feature!("avx512ifma");

// Enable AVX-512 Vector Byte Manipulation Instructions.
x86_64_feature!("avx512vbmi");

// Enable AVX-512 further Vector Byte Manipulation Instructions.
x86_64_feature!("avx512vbmi2");

// Enable AVX-512 Vector Length eXtensions.
x86_64_feature!("avx512vl");

// Enable AVX-512 Vector Neural Network Instructions.
x86_64_feature!("avx512vnni");

// Enable AVX-512 vp2intersect.
x86_64_feature!("avx512vp2intersect");

// Enable AVX-512 Population Count Instructions.
x86_64_feature!("avx512vpopcntdq");

// Enable AVX-IFMA.
x86_64_feature!("avxifma");

// Support AVX-NE-CONVERT instructions.
x86_64_feature!("avxneconvert");

// Support AVX_VNNI encoding.
x86_64_feature!("avxvnni");

// Enable AVX-VNNI-INT16.
x86_64_feature!("avxvnniint16");

// Enable AVX-VNNI-INT8.
x86_64_feature!("avxvnniint8");

// Support xsave instructions.
x86_64_feature!("xsave");

// Support xsavec instructions. Implies `xsave`.
x86_64_feature!("xsavec");

// Support xsaveopt instructions. Implies `xsave`.
x86_64_feature!("xsaveopt");

// Support xsaves instructions. Implies `xsave`.
x86_64_feature!("xsaves");

// ---

// AMX features.

// Support AMX-AVX512 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-avx512", "amx_avx512");

// Support AMX-BF16 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-bf16", "amx_bf16");

// Support AMX-COMPLEX instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-complex", "amx_complex");

// Support AMX amx-fp16 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-fp16", "amx_fp16");

// Support AMX-FP8 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-fp8", "amx_fp8");

// Support AMX-INT8 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-int8", "amx_int8");

// Support AMX-MOVRS instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-movrs", "amx_movrs");

// Support AMX-TF32 instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-tf32", "amx_tf32");

// Support AMX-TILE instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("amx-tile", "amx_tile");

// Support AVX10.1 instruction.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("avx10.1", "avx10_1");

// Support AVX10.2 instruction.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("avx10.2", "avx10_2");

// ---

// Miscellaneous instruction sets.

// Support ADX instructions.
x86_64_feature!("adx");

// Support extended general purpose register.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("apxf");

// Support BMI instructions.
x86_64_feature!("bmi1");

// Support BMI2 instructions.
x86_64_feature!("bmi2");

// 64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips).
x86_64_feature!("cmpxchg16b");

// REP MOVS/STOS are fast.
x86_64_feature!("ermsb");

// Support fxsave/fxrestore instructions.
x86_64_feature!("fxsr");

// Support Key Locker kl Instructions.
x86_64_feature!("kl");

// Support LZCNT instruction.
x86_64_feature!("lzcnt");

// Support MOVBE instruction.
x86_64_feature!("movbe");

// Enable MOVRS.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("movrs");

// Support POPCNT instruction.
x86_64_feature!("popcnt");

// Support RDRAND instruction.
x86_64_feature!("rdrand");

// Support RDSEED instruction.
x86_64_feature!("rdseed");

// Support RTM instructions.
x86_64_feature!("rtm");

// Support SHA512 instructions.
x86_64_feature!("sha512");

// Support SM3 instructions.
x86_64_feature!("sm3");

// Support SM4 instructions.
x86_64_feature!("sm4");

// Enable TBM instructions.
x86_64_feature!("tbm");

// Promote selected AES instructions to AVX512/AVX registers.
x86_64_feature!("vaes");

// Support Key Locker wide Instructions.
x86_64_feature!("widekl");

// Enable XOP instructions.
// DISABLED: Unstable library feature as of 1.96.0
// x86_64_feature!("xop");