#![feature(asm)]
#![no_std]
#![crate_type = "staticlib"]
#![deny(warnings)]
#![allow(stable_features)]
mod inline;
macro_rules! shims {
(
$( fn $name:ident( $($arg:ident: $argty:ty),* ) $(-> $ret:ty)?; )+
) => {
$(
#[no_mangle]
pub unsafe extern "C" fn $name(
$($arg: $argty),*
) $(-> $ret)? {
crate::inline::$name($($arg),*)
}
)+
};
}
shims! {
fn __bkpt();
fn __control_r() -> u32;
fn __control_w(w: u32);
fn __cpsid();
fn __cpsie();
fn __delay(cyc: u32);
fn __dmb();
fn __dsb();
fn __isb();
fn __msp_r() -> u32;
fn __msp_w(val: u32);
fn __nop();
fn __primask_r() -> u32;
fn __psp_r() -> u32;
fn __psp_w(val: u32);
fn __sev();
fn __udf() -> !;
fn __wfe();
fn __wfi();
fn __sh_syscall(nr: u32, arg: u32) -> u32;
fn __bootstrap(msp: u32, rv: u32) -> !;
}
#[cfg(any(armv7m, armv8m_main))]
shims! {
fn __basepri_max(val: u8);
fn __basepri_r() -> u8;
fn __basepri_w(val: u8);
fn __faultmask_r() -> u32;
fn __enable_icache();
fn __enable_dcache();
}
#[cfg(armv7em)]
shims! {
fn __basepri_max_cm7_r0p1(val: u8);
fn __basepri_w_cm7_r0p1(val: u8);
}
#[cfg(armv8m)]
shims! {
fn __tt(target: u32) -> u32;
fn __ttt(target: u32) -> u32;
fn __tta(target: u32) -> u32;
fn __ttat(target: u32) -> u32;
fn __msp_ns_r() -> u32;
fn __msp_ns_w(val: u32);
fn __bxns(val: u32);
}
#[cfg(armv8m_main)]
shims! {
fn __msplim_r() -> u32;
fn __msplim_w(val: u32);
fn __psplim_r() -> u32;
fn __psplim_w(val: u32);
}
#[cfg(has_fpu)]
shims! {
fn __fpscr_r() -> u32;
fn __fpscr_w(val: u32);
}
#[panic_handler]
#[link_section = ".text.asm_panic_handler"]
fn panic(_: &core::panic::PanicInfo) -> ! {
extern "C" {
#[link_name = "cortex-m internal error: panic handler not optimized out, please file an \
issue at https://github.com/rust-embedded/cortex-m"]
fn __cortex_m_should_not_panic() -> !;
}
unsafe {
__cortex_m_should_not_panic();
}
}