cortex-m 0.4.3

Low level access to Cortex-M processors
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

//! Fault Mask Register

/// All exceptions are ...
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
pub enum Faultmask {
    /// Active
    Active,
    /// Inactive, expect for NMI
    Inactive,
}

impl Faultmask {
    /// All exceptions are active
    pub fn is_active(&self) -> bool {
        *self == Faultmask::Active
    }

    /// All exceptions, except for NMI, are inactive
    pub fn is_inactive(&self) -> bool {
        *self == Faultmask::Inactive
    }
}

/// Reads the CPU register
#[inline]
pub fn read() -> Faultmask {
    match () {
        #[cfg(target_arch = "arm")]
        () => {
            let r: u32;
            unsafe { asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
            if r & (1 << 0) == (1 << 0) {
                Faultmask::Inactive
            } else {
                Faultmask::Active
            }
        }
        #[cfg(not(target_arch = "arm"))]
        () => unimplemented!(),
    }
}