cortex-ar 0.3.0

CPU support for AArch32 Arm Cortex-R and Arm Cortex-A
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

//! Code for managing IMP_CDBGDCD (*Data Cache Data Read Operation.*)

use crate::register::{SysReg, SysRegWrite};

/// IMP_CDBGDCD (*Data Cache Data Read Operation.*)
#[derive(Debug, Clone, Copy)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct ImpCdbgdcd(pub u32);
impl SysReg for ImpCdbgdcd {
    const CP: u32 = 15;
    const CRN: u32 = 15;
    const OP1: u32 = 3;
    const CRM: u32 = 4;
    const OP2: u32 = 0;
}
impl crate::register::SysRegWrite for ImpCdbgdcd {}
impl ImpCdbgdcd {
    #[inline]
    /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation.*)
    ///
    /// # Safety
    ///
    /// Ensure that this value is appropriate for this register
    pub unsafe fn write(value: Self) {
        unsafe {
            <Self as SysRegWrite>::write_raw(value.0);
        }
    }
}