cortex-ar 0.3.0

CPU support for AArch32 Arm Cortex-R and Arm Cortex-A
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

//! CPU/peripheral support for Arm Cortex-R

#![no_std]

mod critical_section;

#[cfg(any(doc, target_arch = "arm"))]
pub mod asm;

pub mod cache;
pub mod interrupt;
pub mod mmu;
pub mod register;

#[cfg(any(test, doc, arm_architecture = "v7-r"))]
pub mod pmsav7;

#[cfg(any(test, doc, arm_architecture = "v8-r"))]
pub mod generic_timer;

#[cfg(any(test, doc, arm_architecture = "v8-r"))]
pub mod pmsav8;

/// Generate an SVC call with the given argument.
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your Svc handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc {
    ($r0:expr) => {
        unsafe {
            core::arch::asm!("svc {arg}", arg = const $r0, out("lr") _);
        }
    }
}