cortex_a/registers/
midr_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Main ID Register - EL1
9//!
10//! Provides identification information for the processor, including an implementer code for the
11//! device and a device ID number.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub MIDR_EL1 [
17        /// The Implementer code. This field must hold an implementer code that has been assigned by
18        /// Arm. Assigned codes include the following:
19        ///
20        /// Hex representation Implementer
21        /// 0x00               Reserved for software use
22        /// 0xC0               Ampere Computing
23        /// 0x41               Arm Limited
24        /// 0x42               Broadcom Corporation
25        /// 0x43               Cavium Inc.
26        /// 0x44               Digital Equipment Corporation
27        /// 0x46               Fujitsu Ltd.
28        /// 0x49               Infineon Technologies AG
29        /// 0x4D               Motorola or Freescale Semiconductor Inc.
30        /// 0x4E               NVIDIA Corporation
31        /// 0x50               Applied Micro Circuits Corporation
32        /// 0x51               Qualcomm Inc.
33        /// 0x56               Marvell International Ltd.
34        /// 0x69               Intel Corporation
35        ///
36        /// Arm can assign codes that are not published in this manual. All values not assigned by
37        /// Arm are reserved and must not be used.
38        Implementer OFFSET(24) NUMBITS(8) [
39            Reserved = 0x00,
40            Ampere = 0xC0,
41            Arm = 0x41,
42            Broadcom = 0x42,
43            Cavium = 0x43,
44            DigitalEquipment = 0x44,
45            Fujitsu = 0x46,
46            Infineon = 0x49,
47            MotorolaOrFreescale = 0x4D,
48            NVIDIA = 0x4E,
49            AppliedMicroCircuits = 0x50,
50            Qualcomm = 0x51,
51            Marvell = 0x56,
52            Intel = 0x69
53        ],
54
55        /// An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish
56        /// between different product variants, or major revisions of a product.
57        Variant OFFSET(20) NUMBITS(4) [],
58
59        /// The permitted values of this field are:
60        ///
61        /// 0001 Armv4.
62        /// 0010 Armv4T.
63        /// 0011 Armv5 (obsolete).
64        /// 0100 Armv5T.
65        /// 0101 Armv5TE.
66        /// 0110 Armv5TEJ.
67        /// 0111 Armv6.
68        /// 1111 Architectural features are individually identified in the ID_* registers, see ID
69        /// registers on page K14-8060.
70        ///
71        /// All other values are reserved.
72        Architecture OFFSET(16) NUMBITS(4) [
73            Individual = 0b1111
74        ],
75
76        /// An IMPLEMENTATION DEFINED primary part number for the device.
77        ///
78        /// On processors implemented by Arm, if the top four bits of the primary part number are
79        /// 0x0 or 0x7, the variant and architecture are encoded differently.
80        PartNum OFFSET(4) NUMBITS(12) [],
81
82        /// An IMPLEMENTATION DEFINED revision number for the device.
83        Revision OFFSET(0) NUMBITS(4) []
84    ]
85}
86
87pub struct Reg;
88
89impl Readable for Reg {
90    type T = u64;
91    type R = MIDR_EL1::Register;
92
93    sys_coproc_read_raw!(u64, "MIDR_EL1", "x");
94}
95
96pub const MIDR_EL1: Reg = Reg {};
cortex_a/registers/midr_el1.rs

cortex_a/registers/
midr_el1.rs
