Module cortex_a::registers::HCR_EL2[−][src]

Modules

DC

Default Cacheability.

RW

Execution state control for lower Exception levels:

SWIO

Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way:

VM

Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime, when EL2 is enabled in the current Security state. The possible values are:

Structs

Register

Constants

DC
RW
SWIO
VM