Module cortex_a::registers::HCR_EL2::RW [−][src]
Expand description
Execution state control for lower Exception levels:
0 Lower levels are all AArch32. 1 The Execution state for EL1 is AArch64. The Execution state for EL0 is determined by the current value of PSTATE.nRW when executing at EL0.
If all lower Exception levels cannot use AArch32 then this bit is RAO/WI.
In an implementation that includes EL3, when SCR_EL3.NS==0, the PE behaves as if this bit has the same value as the SCR_EL3.RW bit for all purposes other than a direct read or write access of HCR_EL2.
The RW bit is permitted to be cached in a TLB.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 1 for all purposes other than a direct read of the value of this bit.
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Execution state control for lower Exception levels: