Module cortex_a::registers::HCR_EL2

Modules

Physical SError interrupt routing.

Controls the use of instructions related to Pointer Authentication:

Trap registers holding “key” values for Pointer Authentication. Traps accesses to the following registers from EL1 to EL2, when EL2 is enabled in the current Security state, reported using EC syndrome value 0x18:

DC

Default Cacheability.

E2H

EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System’s applications are running in EL0.

FMO

Physical FIQ Routing. If this bit is 0:

FWB

When FEAT_S2FWB is implemented Forced Write-back changes the combined cachability of stage1 and stage2 attributes

IMO

Physical IRQ Routing.

RW

Execution state control for lower Exception levels:

SWIO

Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way:

TEA

Route synchronous External abort exceptions to EL2. if 0: This control does not cause exceptions to be routed from EL0 and EL1 to EL2. if 1: Route synchronous External abort exceptions from EL0 and EL1 to EL2, when EL2 is enabled in the current Security state, if not routed to EL3.

TGE

Trap General Exceptions, from EL0.

VM

Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime, when EL2 is enabled in the current Security state. The possible values are:

Structs

Register

Constants