corstone300_pac/syscontrol/
pdcm_pd_cpu0_sense.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `PDCM_PD_CPU0_SENSE` reader"]
6pub struct R(crate::R<PDCM_PD_CPU0_SENSE_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<PDCM_PD_CPU0_SENSE_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<PDCM_PD_CPU0_SENSE_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<PDCM_PD_CPU0_SENSE_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `PDCM_PD_CPU0_SENSE` writer"]
21pub struct W(crate::W<PDCM_PD_CPU0_SENSE_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<PDCM_PD_CPU0_SENSE_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<PDCM_PD_CPU0_SENSE_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<PDCM_PD_CPU0_SENSE_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `S_PD_SYS_ON` reader - Enable PD_SYS ON Sensitivity"]
42pub type S_PD_SYS_ON_R = crate::BitReader<S_PD_SYS_ON_A>;
43#[doc = "Enable PD_SYS ON Sensitivity\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum S_PD_SYS_ON_A {
46    #[doc = "1: Keep PD_SYS awake after powered ON"]
47    ENABLE = 1,
48}
49impl From<S_PD_SYS_ON_A> for bool {
50    #[inline(always)]
51    fn from(variant: S_PD_SYS_ON_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl S_PD_SYS_ON_R {
56    #[doc = "Get enumerated values variant"]
57    #[inline(always)]
58    pub fn variant(&self) -> Option<S_PD_SYS_ON_A> {
59        match self.bits {
60            true => Some(S_PD_SYS_ON_A::ENABLE),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `ENABLE`"]
65    #[inline(always)]
66    pub fn is_enable(&self) -> bool {
67        *self == S_PD_SYS_ON_A::ENABLE
68    }
69}
70#[doc = "Field `S_PD_SYS_ON` writer - Enable PD_SYS ON Sensitivity"]
71pub type S_PD_SYS_ON_W<'a, const O: u8> =
72    crate::BitWriter<'a, u32, PDCM_PD_CPU0_SENSE_SPEC, S_PD_SYS_ON_A, O>;
73impl<'a, const O: u8> S_PD_SYS_ON_W<'a, O> {
74    #[doc = "Keep PD_SYS awake after powered ON"]
75    #[inline(always)]
76    pub fn enable(self) -> &'a mut W {
77        self.variant(S_PD_SYS_ON_A::ENABLE)
78    }
79}
80#[doc = "Field `S_PD_CPU0_ON` reader - Tied to LOW"]
81pub type S_PD_CPU0_ON_R = crate::BitReader<bool>;
82#[doc = "Field `S_PD_DEBUG_ON` reader - Tied to LOW"]
83pub type S_PD_DEBUG_ON_R = crate::BitReader<bool>;
84#[doc = "Field `S_PDCMQREQ0` reader - PDCMQREQn\\[0\\]
85Tied to LOW"]
86pub type S_PDCMQREQ0_R = crate::BitReader<bool>;
87#[doc = "Field `S_PDCMQREQ0` writer - PDCMQREQn\\[0\\]
88Tied to LOW"]
89pub type S_PDCMQREQ0_W<'a, const O: u8> =
90    crate::BitWriter<'a, u32, PDCM_PD_CPU0_SENSE_SPEC, bool, O>;
91#[doc = "Field `S_PDCMQREQ1` reader - PDCMQREQn\\[1\\]
92Tied to LOW"]
93pub type S_PDCMQREQ1_R = crate::BitReader<bool>;
94#[doc = "Field `S_PDCMQREQ1` writer - PDCMQREQn\\[1\\]
95Tied to LOW"]
96pub type S_PDCMQREQ1_W<'a, const O: u8> =
97    crate::BitWriter<'a, u32, PDCM_PD_CPU0_SENSE_SPEC, bool, O>;
98#[doc = "Field `S_PDCMQREQ2` reader - PDCMQREQn\\[2\\]
99Tied to LOW"]
100pub type S_PDCMQREQ2_R = crate::BitReader<bool>;
101#[doc = "Field `S_PDCMQREQ2` writer - PDCMQREQn\\[2\\]
102Tied to LOW"]
103pub type S_PDCMQREQ2_W<'a, const O: u8> =
104    crate::BitWriter<'a, u32, PDCM_PD_CPU0_SENSE_SPEC, bool, O>;
105#[doc = "Field `S_PDCMQREQ3` reader - PDCMQREQn\\[3\\]
106Tied to LOW"]
107pub type S_PDCMQREQ3_R = crate::BitReader<bool>;
108#[doc = "Field `S_PDCMQREQ3` writer - PDCMQREQn\\[3\\]
109Tied to LOW"]
110pub type S_PDCMQREQ3_W<'a, const O: u8> =
111    crate::BitWriter<'a, u32, PDCM_PD_CPU0_SENSE_SPEC, bool, O>;
112impl R {
113    #[doc = "Bit 0 - Enable PD_SYS ON Sensitivity"]
114    #[inline(always)]
115    pub fn s_pd_sys_on(&self) -> S_PD_SYS_ON_R {
116        S_PD_SYS_ON_R::new((self.bits & 1) != 0)
117    }
118    #[doc = "Bit 1 - Tied to LOW"]
119    #[inline(always)]
120    pub fn s_pd_cpu0_on(&self) -> S_PD_CPU0_ON_R {
121        S_PD_CPU0_ON_R::new(((self.bits >> 1) & 1) != 0)
122    }
123    #[doc = "Bit 13 - Tied to LOW"]
124    #[inline(always)]
125    pub fn s_pd_debug_on(&self) -> S_PD_DEBUG_ON_R {
126        S_PD_DEBUG_ON_R::new(((self.bits >> 13) & 1) != 0)
127    }
128    #[doc = "Bit 16 - PDCMQREQn\\[0\\]
129Tied to LOW"]
130    #[inline(always)]
131    pub fn s_pdcmqreq0(&self) -> S_PDCMQREQ0_R {
132        S_PDCMQREQ0_R::new(((self.bits >> 16) & 1) != 0)
133    }
134    #[doc = "Bit 17 - PDCMQREQn\\[1\\]
135Tied to LOW"]
136    #[inline(always)]
137    pub fn s_pdcmqreq1(&self) -> S_PDCMQREQ1_R {
138        S_PDCMQREQ1_R::new(((self.bits >> 17) & 1) != 0)
139    }
140    #[doc = "Bit 18 - PDCMQREQn\\[2\\]
141Tied to LOW"]
142    #[inline(always)]
143    pub fn s_pdcmqreq2(&self) -> S_PDCMQREQ2_R {
144        S_PDCMQREQ2_R::new(((self.bits >> 18) & 1) != 0)
145    }
146    #[doc = "Bit 19 - PDCMQREQn\\[3\\]
147Tied to LOW"]
148    #[inline(always)]
149    pub fn s_pdcmqreq3(&self) -> S_PDCMQREQ3_R {
150        S_PDCMQREQ3_R::new(((self.bits >> 19) & 1) != 0)
151    }
152}
153impl W {
154    #[doc = "Bit 0 - Enable PD_SYS ON Sensitivity"]
155    #[inline(always)]
156    pub fn s_pd_sys_on(&mut self) -> S_PD_SYS_ON_W<0> {
157        S_PD_SYS_ON_W::new(self)
158    }
159    #[doc = "Bit 16 - PDCMQREQn\\[0\\]
160Tied to LOW"]
161    #[inline(always)]
162    pub fn s_pdcmqreq0(&mut self) -> S_PDCMQREQ0_W<16> {
163        S_PDCMQREQ0_W::new(self)
164    }
165    #[doc = "Bit 17 - PDCMQREQn\\[1\\]
166Tied to LOW"]
167    #[inline(always)]
168    pub fn s_pdcmqreq1(&mut self) -> S_PDCMQREQ1_W<17> {
169        S_PDCMQREQ1_W::new(self)
170    }
171    #[doc = "Bit 18 - PDCMQREQn\\[2\\]
172Tied to LOW"]
173    #[inline(always)]
174    pub fn s_pdcmqreq2(&mut self) -> S_PDCMQREQ2_W<18> {
175        S_PDCMQREQ2_W::new(self)
176    }
177    #[doc = "Bit 19 - PDCMQREQn\\[3\\]
178Tied to LOW"]
179    #[inline(always)]
180    pub fn s_pdcmqreq3(&mut self) -> S_PDCMQREQ3_W<19> {
181        S_PDCMQREQ3_W::new(self)
182    }
183    #[doc = "Writes raw bits to the register."]
184    #[inline(always)]
185    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
186        self.0.bits(bits);
187        self
188    }
189}
190#[doc = "PDCM PD_CPU0 Sensitivity.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdcm_pd_cpu0_sense](index.html) module"]
191pub struct PDCM_PD_CPU0_SENSE_SPEC;
192impl crate::RegisterSpec for PDCM_PD_CPU0_SENSE_SPEC {
193    type Ux = u32;
194}
195#[doc = "`read()` method returns [pdcm_pd_cpu0_sense::R](R) reader structure"]
196impl crate::Readable for PDCM_PD_CPU0_SENSE_SPEC {
197    type Reader = R;
198}
199#[doc = "`write(|w| ..)` method takes [pdcm_pd_cpu0_sense::W](W) writer structure"]
200impl crate::Writable for PDCM_PD_CPU0_SENSE_SPEC {
201    type Writer = W;
202}
203#[doc = "`reset()` method sets PDCM_PD_CPU0_SENSE to value 0"]
204impl crate::Resettable for PDCM_PD_CPU0_SENSE_SPEC {
205    #[inline(always)]
206    fn reset_value() -> Self::Ux {
207        0
208    }
209}
corstone300_pac/syscontrol/pdcm_pd_cpu0_sense.rs

corstone300_pac/syscontrol/
pdcm_pd_cpu0_sense.rs
