::consortium_hal::peripherals! {
ADC1,
ADC1_COMMON,
ADC2,
ADC2_COMMON,
ADF1,
ADF1_Filter0,
BSEC,
CA35SYSCFG,
CRC,
CRYP1,
CRYP2,
CSI,
DBGMCU,
DCACHE,
DCMI,
DCMIPP,
DDRC,
DDRDBG,
DDRPERFM,
DTS,
ETH1,
ETH2,
EXTI1,
EXTI1_C1,
EXTI1_C2,
EXTI2,
EXTI2_C1,
EXTI2_C2,
EXTI2_C3,
FDCAN1,
FDCAN2,
FDCAN_CCU,
FMC_Bank1E_R,
FMC_Bank1_R,
FMC_Bank3_R,
FMC_Common_R,
GPIOA,
GPIOB,
GPIOC,
GPIOD,
GPIOE,
GPIOF,
GPIOG,
GPIOH,
GPIOI,
GPIOZ,
HASH1,
HASH1_DIGEST,
HASH2,
HASH2_DIGEST,
HDP,
HPDMA1,
HPDMA1_Channel0,
HPDMA1_Channel1,
HPDMA1_Channel10,
HPDMA1_Channel11,
HPDMA1_Channel12,
HPDMA1_Channel13,
HPDMA1_Channel14,
HPDMA1_Channel15,
HPDMA1_Channel2,
HPDMA1_Channel3,
HPDMA1_Channel4,
HPDMA1_Channel5,
HPDMA1_Channel6,
HPDMA1_Channel7,
HPDMA1_Channel8,
HPDMA1_Channel9,
HPDMA2,
HPDMA2_Channel0,
HPDMA2_Channel1,
HPDMA2_Channel10,
HPDMA2_Channel11,
HPDMA2_Channel12,
HPDMA2_Channel13,
HPDMA2_Channel14,
HPDMA2_Channel15,
HPDMA2_Channel2,
HPDMA2_Channel3,
HPDMA2_Channel4,
HPDMA2_Channel5,
HPDMA2_Channel6,
HPDMA2_Channel7,
HPDMA2_Channel8,
HPDMA2_Channel9,
HPDMA3,
HPDMA3_Channel0,
HPDMA3_Channel1,
HPDMA3_Channel10,
HPDMA3_Channel11,
HPDMA3_Channel12,
HPDMA3_Channel13,
HPDMA3_Channel14,
HPDMA3_Channel15,
HPDMA3_Channel2,
HPDMA3_Channel3,
HPDMA3_Channel4,
HPDMA3_Channel5,
HPDMA3_Channel6,
HPDMA3_Channel7,
HPDMA3_Channel8,
HPDMA3_Channel9,
I2C1,
I2C2,
I2C3,
I3C1,
I3C2,
I3C3,
IAC,
ICACHE,
IPCC1,
IWDG1,
IWDG2,
IWDG3,
IWDG4,
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5,
LPUART1,
LTDC,
MDF1,
MDF1_Filter0,
MDF1_Filter1,
MDF1_Filter2,
MDF1_Filter3,
MDF1_Filter4,
MDF1_Filter5,
MDF1_Filter6,
MDF1_Filter7,
OCTOSPI1,
OTFDEC1,
OTFDEC1_REGION1,
OTFDEC1_REGION2,
OTFDEC1_REGION3,
OTFDEC1_REGION4,
OTFDEC2,
OTFDEC2_REGION1,
OTFDEC2_REGION2,
OTFDEC2_REGION3,
OTFDEC2_REGION4,
PKA,
PSSI,
PWR,
RAMCFG_BKPSRAM,
RAMCFG_RETRAM,
RAMCFG_SRAM1,
RAMCFG_SYSRAM,
RCC,
RIFSC_ID,
RIMC,
RISAB1,
RISAB2,
RISAB3,
RISAB5,
RISAF1,
RISAF2,
RISAF4,
RISC,
RNG1,
RNG2,
RTC,
SAES,
SAI1,
SAI1_Block_A,
SAI1_Block_B,
SAI2,
SAI2_Block_A,
SAI2_Block_B,
SAI3,
SAI3_Block_A,
SAI3_Block_B,
SAI4,
SAI4_Block_A,
SAI4_Block_B,
SDMMC1,
SDMMC2,
SDMMC3,
SERC,
SPDIFRX,
SPI1,
SPI2,
SPI3,
SPI4,
SPI5,
SPI6,
STGENC,
STGENR,
SYSCFG,
TAMP,
TIM1,
TIM10,
TIM11,
TIM12,
TIM13,
TIM14,
TIM15,
TIM16,
TIM17,
TIM2,
TIM3,
TIM4,
TIM5,
TIM6,
TIM7,
TIM8,
UART4,
UART5,
UART7,
USART1,
USART2,
USART3,
USART6,
USBH_EHCI,
USBH_OHCI,
VREFBUF,
WWDG1,
}
#[cfg(feature = "adc")]
mod adc_bindings {
crate::adc::impl_adc!(ADC1, 0x404e_0000, Some(81));
crate::adc::impl_adc!(ADC2, 0x404f_0000, Some(82));
}
#[cfg(feature = "can")]
mod can_bindings {
crate::can::impl_can!(FDCAN1, 0x402d_0000, Some(84));
crate::can::impl_can!(FDCAN2, 0x402e_0000, Some(85));
}
#[cfg(feature = "dma")]
mod dma_bindings {
crate::dma::impl_dma_channel!(HPDMA1_Channel0, 0x4040_0050, Some(31));
crate::dma::impl_dma_channel!(HPDMA1_Channel1, 0x4040_00d0, Some(32));
crate::dma::impl_dma_channel!(HPDMA1_Channel10, 0x4040_0550, Some(41));
crate::dma::impl_dma_channel!(HPDMA1_Channel11, 0x4040_05d0, Some(42));
crate::dma::impl_dma_channel!(HPDMA1_Channel12, 0x4040_0650, Some(43));
crate::dma::impl_dma_channel!(HPDMA1_Channel13, 0x4040_06d0, Some(44));
crate::dma::impl_dma_channel!(HPDMA1_Channel14, 0x4040_0750, Some(45));
crate::dma::impl_dma_channel!(HPDMA1_Channel15, 0x4040_07d0, Some(46));
crate::dma::impl_dma_channel!(HPDMA1_Channel2, 0x4040_0150, Some(33));
crate::dma::impl_dma_channel!(HPDMA1_Channel3, 0x4040_01d0, Some(34));
crate::dma::impl_dma_channel!(HPDMA1_Channel4, 0x4040_0250, Some(35));
crate::dma::impl_dma_channel!(HPDMA1_Channel5, 0x4040_02d0, Some(36));
crate::dma::impl_dma_channel!(HPDMA1_Channel6, 0x4040_0350, Some(37));
crate::dma::impl_dma_channel!(HPDMA1_Channel7, 0x4040_03d0, Some(38));
crate::dma::impl_dma_channel!(HPDMA1_Channel8, 0x4040_0450, Some(39));
crate::dma::impl_dma_channel!(HPDMA1_Channel9, 0x4040_04d0, Some(40));
crate::dma::impl_dma_channel!(HPDMA2_Channel0, 0x4041_0050, Some(47));
crate::dma::impl_dma_channel!(HPDMA2_Channel1, 0x4041_00d0, Some(48));
crate::dma::impl_dma_channel!(HPDMA2_Channel10, 0x4041_0550, Some(57));
crate::dma::impl_dma_channel!(HPDMA2_Channel11, 0x4041_05d0, Some(58));
crate::dma::impl_dma_channel!(HPDMA2_Channel12, 0x4041_0650, Some(59));
crate::dma::impl_dma_channel!(HPDMA2_Channel13, 0x4041_06d0, Some(60));
crate::dma::impl_dma_channel!(HPDMA2_Channel14, 0x4041_0750, Some(61));
crate::dma::impl_dma_channel!(HPDMA2_Channel15, 0x4041_07d0, Some(62));
crate::dma::impl_dma_channel!(HPDMA2_Channel2, 0x4041_0150, Some(49));
crate::dma::impl_dma_channel!(HPDMA2_Channel3, 0x4041_01d0, Some(50));
crate::dma::impl_dma_channel!(HPDMA2_Channel4, 0x4041_0250, Some(51));
crate::dma::impl_dma_channel!(HPDMA2_Channel5, 0x4041_02d0, Some(52));
crate::dma::impl_dma_channel!(HPDMA2_Channel6, 0x4041_0350, Some(53));
crate::dma::impl_dma_channel!(HPDMA2_Channel7, 0x4041_03d0, Some(54));
crate::dma::impl_dma_channel!(HPDMA2_Channel8, 0x4041_0450, Some(55));
crate::dma::impl_dma_channel!(HPDMA2_Channel9, 0x4041_04d0, Some(56));
crate::dma::impl_dma_channel!(HPDMA3_Channel0, 0x4042_0050, Some(63));
crate::dma::impl_dma_channel!(HPDMA3_Channel1, 0x4042_00d0, Some(64));
crate::dma::impl_dma_channel!(HPDMA3_Channel10, 0x4042_0550, Some(73));
crate::dma::impl_dma_channel!(HPDMA3_Channel11, 0x4042_05d0, Some(74));
crate::dma::impl_dma_channel!(HPDMA3_Channel12, 0x4042_0650, Some(75));
crate::dma::impl_dma_channel!(HPDMA3_Channel13, 0x4042_06d0, Some(76));
crate::dma::impl_dma_channel!(HPDMA3_Channel14, 0x4042_0750, Some(77));
crate::dma::impl_dma_channel!(HPDMA3_Channel15, 0x4042_07d0, Some(78));
crate::dma::impl_dma_channel!(HPDMA3_Channel2, 0x4042_0150, Some(65));
crate::dma::impl_dma_channel!(HPDMA3_Channel3, 0x4042_01d0, Some(66));
crate::dma::impl_dma_channel!(HPDMA3_Channel4, 0x4042_0250, Some(67));
crate::dma::impl_dma_channel!(HPDMA3_Channel5, 0x4042_02d0, Some(68));
crate::dma::impl_dma_channel!(HPDMA3_Channel6, 0x4042_0350, Some(69));
crate::dma::impl_dma_channel!(HPDMA3_Channel7, 0x4042_03d0, Some(70));
crate::dma::impl_dma_channel!(HPDMA3_Channel8, 0x4042_0450, Some(71));
crate::dma::impl_dma_channel!(HPDMA3_Channel9, 0x4042_04d0, Some(72));
}
#[cfg(feature = "gpio")]
mod gpio_bindings {
crate::gpio::impl_gpio!(GPIOA, 0x4424_0000, None);
crate::gpio::impl_gpio!(GPIOB, 0x4425_0000, None);
crate::gpio::impl_gpio!(GPIOC, 0x4426_0000, None);
crate::gpio::impl_gpio!(GPIOD, 0x4427_0000, None);
crate::gpio::impl_gpio!(GPIOE, 0x4428_0000, None);
crate::gpio::impl_gpio!(GPIOF, 0x4429_0000, None);
crate::gpio::impl_gpio!(GPIOG, 0x442a_0000, None);
crate::gpio::impl_gpio!(GPIOH, 0x442b_0000, None);
crate::gpio::impl_gpio!(GPIOI, 0x442c_0000, None);
crate::gpio::impl_gpio!(GPIOZ, 0x4620_0000, None);
}
#[cfg(feature = "i2c")]
mod i2c_bindings {
crate::i2c::impl_i2c!(I2C1, 0x4017_0000, Some(95));
crate::i2c::impl_i2c!(I2C2, 0x4018_0000, Some(97));
crate::i2c::impl_i2c!(I2C3, 0x4604_0000, Some(124));
}
#[cfg(feature = "i3c")]
mod i3c_bindings {
crate::i3c::impl_i3c!(I3C1, 0x4019_0000, Some(96));
crate::i3c::impl_i3c!(I3C2, 0x401a_0000, Some(98));
crate::i3c::impl_i3c!(I3C3, 0x4608_0000, Some(125));
}
#[cfg(feature = "lptim")]
mod lptim_bindings {
crate::lptim::impl_lptim!(LPTIM1, 0x4009_0000, Lptim1, Some(149));
crate::lptim::impl_lptim!(LPTIM2, 0x400a_0000, Lptim2, Some(180));
crate::lptim::impl_lptim!(LPTIM3, 0x4605_0000, Lptim3, Some(181));
crate::lptim::impl_lptim!(LPTIM4, 0x4606_0000, Lptim4, Some(182));
crate::lptim::impl_lptim!(LPTIM5, 0x4607_0000, Lptim5, Some(183));
}
#[cfg(feature = "spi")]
mod spi_bindings {
crate::spi::impl_spi!(SPI1, 0x4023_0000, Some(99));
crate::spi::impl_spi!(SPI2, 0x400b_0000, Some(100));
crate::spi::impl_spi!(SPI3, 0x400c_0000, Some(112));
crate::spi::impl_spi!(SPI4, 0x4024_0000, Some(137));
crate::spi::impl_spi!(SPI5, 0x4028_0000, Some(138));
crate::spi::impl_spi!(SPI6, 0x4602_0000, Some(139));
}
#[cfg(feature = "timer")]
mod timer_bindings {
crate::timer::impl_tim!(TIM1, 0x4020_0000, Bits16, Some(89));
crate::timer::impl_tim!(TIM10, 0x401c_0000, Bits16, Some(175));
crate::timer::impl_tim!(TIM11, 0x401d_0000, Bits16, Some(189));
crate::timer::impl_tim!(TIM12, 0x4006_0000, Bits16, Some(168));
crate::timer::impl_tim!(TIM13, 0x4007_0000, Bits16, Some(173));
crate::timer::impl_tim!(TIM14, 0x4008_0000, Bits16, Some(174));
crate::timer::impl_tim!(TIM15, 0x4025_0000, Bits16, Some(165));
crate::timer::impl_tim!(TIM16, 0x4026_0000, Bits16, Some(166));
crate::timer::impl_tim!(TIM17, 0x4027_0000, Bits16, Some(167));
crate::timer::impl_tim!(TIM2, 0x4000_0000, Bits32, Some(92));
crate::timer::impl_tim!(TIM3, 0x4001_0000, Bits16, Some(93));
crate::timer::impl_tim!(TIM4, 0x4002_0000, Bits16, Some(94));
crate::timer::impl_tim!(TIM5, 0x4003_0000, Bits32, Some(111));
crate::timer::impl_tim!(TIM6, 0x4004_0000, Bits16, Some(115));
crate::timer::impl_tim!(TIM7, 0x4005_0000, Bits16, Some(116));
crate::timer::impl_tim!(TIM8, 0x4021_0000, Bits16, Some(106));
}
#[cfg(feature = "time-driver-gp-tim")]
mod timer_driver_bindings {
crate::timer_driver::impl_tim_driver!(TIM12, 0x4006_0000, Bits16, Some(168));
crate::timer_driver::impl_tim_driver!(TIM15, 0x4025_0000, Bits16, Some(165));
crate::timer_driver::impl_tim_driver!(TIM2, 0x4000_0000, Bits32, Some(92));
crate::timer_driver::impl_tim_driver!(TIM3, 0x4001_0000, Bits16, Some(93));
crate::timer_driver::impl_tim_driver!(TIM4, 0x4002_0000, Bits16, Some(94));
crate::timer_driver::impl_tim_driver!(TIM5, 0x4003_0000, Bits32, Some(111));
}
#[cfg(feature = "uart")]
mod uart_bindings {
crate::uart::impl_uart!(LPUART1, 0x4603_0000, Some(136));
crate::uart::impl_uart!(UART4, 0x4010_0000, Some(113));
crate::uart::impl_uart!(UART5, 0x4011_0000, Some(114));
crate::uart::impl_uart!(UART7, 0x4037_0000, Some(135));
crate::uart::impl_uart!(USART1, 0x4033_0000, Some(101));
crate::uart::impl_uart!(USART2, 0x400e_0000, Some(102));
crate::uart::impl_uart!(USART3, 0x400f_0000, Some(103));
crate::uart::impl_uart!(USART6, 0x4022_0000, Some(123));
}
#[cfg(feature = "watchdog")]
mod watchdog_bindings {
crate::watchdog::impl_watchdog!(IWDG1, 0x4401_0000, None);
crate::watchdog::impl_watchdog!(IWDG2, 0x4402_0000, None);
crate::watchdog::impl_watchdog!(IWDG3, 0x4403_0000, Some(2));
crate::watchdog::impl_watchdog!(IWDG4, 0x4404_0000, Some(3));
}