#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum ClockNodes {
None,
HSIRC,
HSI48RC,
CRSOutput,
HSEOSC,
LSIRC,
LSEOSC,
MSIRC,
LSCOMult,
LSCOOutput,
SysClkSource,
SysCLKOutput,
PLLSource,
PLLM,
HSERTCDevisor,
RTCClkSource,
RTCOutput,
LCDOutput,
IWDGOutput,
USART1Mult,
USART1output,
USART2Mult,
USART2output,
LPUART1Mult,
LPUART1output,
LPTIM1Mult,
LPTIM1output,
LPTIM2Mult,
LPTIM2output,
ADCoutput,
CK48Mult,
CK48output,
RNGoutput,
I2C1Mult,
I2C1output,
I2C3Mult,
I2C3output,
MCOMult,
MCODiv,
MCOPin,
AHBPrescaler,
PWRCLKoutput,
AHBOutput,
HCLKOutput,
CortexPrescaler,
CortexSysOutput,
FCLKCortexOutput,
APB1Prescaler,
APB1Output,
TimPrescalerAPB1,
TimPrescOut1,
APB2Prescaler,
APB2Output,
TimPrescalerAPB2,
TimPrescOut2,
PLLN,
PLLQ,
PLLQoutput,
PLLR,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum ClockErrorType {
Underflow(u32, u32),
Overflow(u32, u32),
}
#[derive(Debug)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub struct ClockError {
err_type: ClockErrorType,
from: ClockNodes,
to: ClockNodes,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum HSEOSCConf {
Value(u32),
}
impl HSEOSCConf {
pub const fn min() -> u32 {
4000000
}
pub const fn max() -> u32 {
48000000
}
pub const fn get(&self) -> Result<f32, ClockError> {
match self {
HSEOSCConf::Value(val) => {
if *val < Self::min() {
return Err(ClockError {
err_type: ClockErrorType::Underflow(*val, Self::min()),
from: ClockNodes::None,
to: ClockNodes::HSEOSC,
});
} else if *val > Self::max() {
return Err(ClockError {
err_type: ClockErrorType::Overflow(*val, Self::max()),
from: ClockNodes::None,
to: ClockNodes::HSEOSC,
});
}
Ok(*val as f32)
}
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum LSEOSCConf {
Value(u32),
}
impl LSEOSCConf {
pub const fn min() -> u32 {
1000
}
pub const fn max() -> u32 {
1000000
}
pub const fn get(&self) -> Result<f32, ClockError> {
match self {
LSEOSCConf::Value(val) => {
if *val < Self::min() {
return Err(ClockError {
err_type: ClockErrorType::Underflow(*val, Self::min()),
from: ClockNodes::None,
to: ClockNodes::LSEOSC,
});
} else if *val > Self::max() {
return Err(ClockError {
err_type: ClockErrorType::Overflow(*val, Self::max()),
from: ClockNodes::None,
to: ClockNodes::LSEOSC,
});
}
Ok(*val as f32)
}
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum MSIRCConf {
CLOCK_100,
CLOCK_200,
CLOCK_400,
CLOCK_800,
CLOCK_1000,
CLOCK_2000,
CLOCK_4000,
CLOCK_8000,
CLOCK_16000,
CLOCK_24000,
CLOCK_32000,
CLOCK_48000,
}
impl MSIRCConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
MSIRCConf::CLOCK_100 => return Ok(100.0),
MSIRCConf::CLOCK_200 => return Ok(200.0),
MSIRCConf::CLOCK_400 => return Ok(400.0),
MSIRCConf::CLOCK_800 => return Ok(800.0),
MSIRCConf::CLOCK_1000 => return Ok(1000.0),
MSIRCConf::CLOCK_2000 => return Ok(2000.0),
MSIRCConf::CLOCK_4000 => return Ok(4000.0),
MSIRCConf::CLOCK_8000 => return Ok(8000.0),
MSIRCConf::CLOCK_16000 => return Ok(16000.0),
MSIRCConf::CLOCK_24000 => return Ok(24000.0),
MSIRCConf::CLOCK_32000 => return Ok(32000.0),
MSIRCConf::CLOCK_48000 => return Ok(48000.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum LSCOMultConf {
LSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum SysClkSourceConf {
MSIRC,
HSIRC,
HSEOSC,
PLLR,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum PLLSourceConf {
MSIRC,
HSIRC,
HSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum PLLMConf {
Value(u32),
}
impl PLLMConf {
pub const fn min() -> u32 {
1
}
pub const fn max() -> u32 {
8
}
pub const fn get(&self) -> Result<f32, ClockError> {
match self {
PLLMConf::Value(val) => {
if *val < Self::min() {
return Err(ClockError {
err_type: ClockErrorType::Underflow(*val, Self::min()),
from: ClockNodes::None,
to: ClockNodes::PLLM,
});
} else if *val > Self::max() {
return Err(ClockError {
err_type: ClockErrorType::Overflow(*val, Self::max()),
from: ClockNodes::None,
to: ClockNodes::PLLM,
});
}
Ok(*val as f32)
}
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum RTCClkSourceConf {
HSERTCDevisor,
LSEOSC,
LSIRC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum USART1MultConf {
APB2Prescaler,
SysCLKOutput,
HSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum USART2MultConf {
APB1Prescaler,
SysCLKOutput,
HSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum LPUART1MultConf {
APB1Prescaler,
SysCLKOutput,
HSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum LPTIM1MultConf {
APB1Prescaler,
LSIRC,
HSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum LPTIM2MultConf {
APB1Prescaler,
LSIRC,
HSIRC,
LSEOSC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum CK48MultConf {
PLLQ,
MSIRC,
HSI48RC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum I2C1MultConf {
APB1Prescaler,
SysCLKOutput,
HSIRC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum I2C3MultConf {
APB1Prescaler,
SysCLKOutput,
HSIRC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum MCOMultConf {
LSEOSC,
LSIRC,
HSEOSC,
SysCLKOutput,
HSIRC,
HSI48RC,
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum MCODivConf {
DIV1,
DIV2,
DIV4,
DIV8,
DIV16,
}
impl MCODivConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
MCODivConf::DIV1 => return Ok(1.0),
MCODivConf::DIV2 => return Ok(2.0),
MCODivConf::DIV4 => return Ok(4.0),
MCODivConf::DIV8 => return Ok(8.0),
MCODivConf::DIV16 => return Ok(16.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum AHBPrescalerConf {
DIV1,
DIV2,
DIV4,
DIV8,
DIV16,
DIV64,
DIV128,
DIV256,
DIV512,
}
impl AHBPrescalerConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
AHBPrescalerConf::DIV1 => return Ok(1.0),
AHBPrescalerConf::DIV2 => return Ok(2.0),
AHBPrescalerConf::DIV4 => return Ok(4.0),
AHBPrescalerConf::DIV8 => return Ok(8.0),
AHBPrescalerConf::DIV16 => return Ok(16.0),
AHBPrescalerConf::DIV64 => return Ok(64.0),
AHBPrescalerConf::DIV128 => return Ok(128.0),
AHBPrescalerConf::DIV256 => return Ok(256.0),
AHBPrescalerConf::DIV512 => return Ok(512.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum CortexPrescalerConf {
DIV1,
DIV8,
}
impl CortexPrescalerConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
CortexPrescalerConf::DIV1 => return Ok(1.0),
CortexPrescalerConf::DIV8 => return Ok(8.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum APB1PrescalerConf {
DIV1,
DIV2,
DIV4,
DIV8,
DIV16,
}
impl APB1PrescalerConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
APB1PrescalerConf::DIV1 => return Ok(1.0),
APB1PrescalerConf::DIV2 => return Ok(2.0),
APB1PrescalerConf::DIV4 => return Ok(4.0),
APB1PrescalerConf::DIV8 => return Ok(8.0),
APB1PrescalerConf::DIV16 => return Ok(16.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum APB2PrescalerConf {
DIV1,
DIV2,
DIV4,
DIV8,
DIV16,
}
impl APB2PrescalerConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
APB2PrescalerConf::DIV1 => return Ok(1.0),
APB2PrescalerConf::DIV2 => return Ok(2.0),
APB2PrescalerConf::DIV4 => return Ok(4.0),
APB2PrescalerConf::DIV8 => return Ok(8.0),
APB2PrescalerConf::DIV16 => return Ok(16.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum PLLNConf {
Value(u32),
}
impl PLLNConf {
pub const fn min() -> u32 {
8
}
pub const fn max() -> u32 {
86
}
pub const fn get(&self) -> Result<f32, ClockError> {
match self {
PLLNConf::Value(val) => {
if *val < Self::min() {
return Err(ClockError {
err_type: ClockErrorType::Underflow(*val, Self::min()),
from: ClockNodes::None,
to: ClockNodes::PLLN,
});
} else if *val > Self::max() {
return Err(ClockError {
err_type: ClockErrorType::Overflow(*val, Self::max()),
from: ClockNodes::None,
to: ClockNodes::PLLN,
});
}
Ok(*val as f32)
}
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum PLLQConf {
DIV2,
DIV4,
DIV6,
DIV8,
}
impl PLLQConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
PLLQConf::DIV2 => return Ok(2.0),
PLLQConf::DIV4 => return Ok(4.0),
PLLQConf::DIV6 => return Ok(6.0),
PLLQConf::DIV8 => return Ok(8.0),
}
}
}
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize))]
pub enum PLLRConf {
DIV2,
DIV4,
DIV6,
DIV8,
}
impl PLLRConf {
pub fn get(&self) -> Result<f32, ClockError> {
match self {
PLLRConf::DIV2 => return Ok(2.0),
PLLRConf::DIV4 => return Ok(4.0),
PLLRConf::DIV6 => return Ok(6.0),
PLLRConf::DIV8 => return Ok(8.0),
}
}
}
#[derive(Debug, Clone)]
#[cfg_attr(feature = "serialize", derive(serde::Serialize, serde::Deserialize))]
pub struct ClockTree {
pub HSEOSC: HSEOSCConf,
pub LSEOSC: LSEOSCConf,
pub MSIRC: MSIRCConf,
pub LSCOMult: LSCOMultConf,
pub SysClkSource: SysClkSourceConf,
pub PLLSource: PLLSourceConf,
pub PLLM: PLLMConf,
pub RTCClkSource: RTCClkSourceConf,
pub USART1Mult: USART1MultConf,
pub USART2Mult: USART2MultConf,
pub LPUART1Mult: LPUART1MultConf,
pub LPTIM1Mult: LPTIM1MultConf,
pub LPTIM2Mult: LPTIM2MultConf,
pub CK48Mult: CK48MultConf,
pub I2C1Mult: I2C1MultConf,
pub I2C3Mult: I2C3MultConf,
pub MCOMult: MCOMultConf,
pub MCODiv: MCODivConf,
pub AHBPrescaler: AHBPrescalerConf,
pub CortexPrescaler: CortexPrescalerConf,
pub APB1Prescaler: APB1PrescalerConf,
pub APB2Prescaler: APB2PrescalerConf,
pub PLLN: PLLNConf,
pub PLLQ: PLLQConf,
pub PLLR: PLLRConf,
}
impl Default for ClockTree {
fn default() -> Self {
Self {
HSEOSC: HSEOSCConf::Value(8000000),
LSEOSC: LSEOSCConf::Value(32768),
MSIRC: MSIRCConf::CLOCK_4000,
LSCOMult: LSCOMultConf::LSIRC,
SysClkSource: SysClkSourceConf::MSIRC,
PLLSource: PLLSourceConf::MSIRC,
PLLM: PLLMConf::Value(1),
RTCClkSource: RTCClkSourceConf::LSIRC,
USART1Mult: USART1MultConf::APB2Prescaler,
USART2Mult: USART2MultConf::APB1Prescaler,
LPUART1Mult: LPUART1MultConf::APB1Prescaler,
LPTIM1Mult: LPTIM1MultConf::APB1Prescaler,
LPTIM2Mult: LPTIM2MultConf::APB1Prescaler,
CK48Mult: CK48MultConf::MSIRC,
I2C1Mult: I2C1MultConf::APB1Prescaler,
I2C3Mult: I2C3MultConf::APB1Prescaler,
MCOMult: MCOMultConf::SysCLKOutput,
MCODiv: MCODivConf::DIV1,
AHBPrescaler: AHBPrescalerConf::DIV1,
CortexPrescaler: CortexPrescalerConf::DIV1,
APB1Prescaler: APB1PrescalerConf::DIV1,
APB2Prescaler: APB2PrescalerConf::DIV1,
PLLN: PLLNConf::Value(8),
PLLQ: PLLQConf::DIV2,
PLLR: PLLRConf::DIV2,
}
}
}
impl ClockTree {
pub fn HSIRC_get(&self) -> Result<f32, ClockError> {
Ok(16000000 as f32)
}
pub fn HSI48RC_get(&self) -> Result<f32, ClockError> {
Ok(48000000 as f32)
}
pub fn CRSOutput_get(&self) -> Result<f32, ClockError> {
self.HSI48RC_get()
}
pub fn HSEOSC_get(&self) -> Result<f32, ClockError> {
self.HSEOSC.get()
}
pub fn LSIRC_get(&self) -> Result<f32, ClockError> {
Ok(32000 as f32)
}
pub fn LSEOSC_get(&self) -> Result<f32, ClockError> {
self.LSEOSC.get()
}
pub fn MSIRC_get(&self) -> Result<f32, ClockError> {
self.MSIRC.get()
}
fn LSCOMult_get(&self) -> Result<f32, ClockError> {
match self.LSCOMult {
LSCOMultConf::LSIRC => return self.LSIRC_get(),
LSCOMultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn LSCOOutput_get(&self) -> Result<f32, ClockError> {
self.LSCOMult_get()
}
fn SysClkSource_get(&self) -> Result<f32, ClockError> {
match self.SysClkSource {
SysClkSourceConf::MSIRC => return self.MSIRC_get(),
SysClkSourceConf::HSIRC => return self.HSIRC_get(),
SysClkSourceConf::HSEOSC => return self.HSEOSC_get(),
SysClkSourceConf::PLLR => return self.PLLR_get(),
};
}
pub fn SysCLKOutput_get(&self) -> Result<f32, ClockError> {
self.SysClkSource_get()
}
fn PLLSource_get(&self) -> Result<f32, ClockError> {
match self.PLLSource {
PLLSourceConf::MSIRC => return self.MSIRC_get(),
PLLSourceConf::HSIRC => return self.HSIRC_get(),
PLLSourceConf::HSEOSC => return self.HSEOSC_get(),
};
}
fn PLLM_get(&self) -> Result<f32, ClockError> {
let input = self.PLLSource_get()? as f32;
let value = self.PLLM.get()? as f32;
Ok((input / value) as f32)
}
fn HSERTCDevisor_get(&self) -> Result<f32, ClockError> {
let input = self.HSEOSC_get()? as f32;
let value = 32 as f32;
Ok((input / value) as f32)
}
fn RTCClkSource_get(&self) -> Result<f32, ClockError> {
match self.RTCClkSource {
RTCClkSourceConf::HSERTCDevisor => return self.HSERTCDevisor_get(),
RTCClkSourceConf::LSEOSC => return self.LSEOSC_get(),
RTCClkSourceConf::LSIRC => return self.LSIRC_get(),
};
}
pub fn RTCOutput_get(&self) -> Result<f32, ClockError> {
self.RTCClkSource_get()
}
pub fn LCDOutput_get(&self) -> Result<f32, ClockError> {
self.RTCClkSource_get()
}
pub fn IWDGOutput_get(&self) -> Result<f32, ClockError> {
self.LSIRC_get()
}
fn USART1Mult_get(&self) -> Result<f32, ClockError> {
match self.USART1Mult {
USART1MultConf::APB2Prescaler => return self.APB2Prescaler_get(),
USART1MultConf::SysCLKOutput => return self.SysCLKOutput_get(),
USART1MultConf::HSIRC => return self.HSIRC_get(),
USART1MultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn USART1output_get(&self) -> Result<f32, ClockError> {
self.USART1Mult_get()
}
fn USART2Mult_get(&self) -> Result<f32, ClockError> {
match self.USART2Mult {
USART2MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
USART2MultConf::SysCLKOutput => return self.SysCLKOutput_get(),
USART2MultConf::HSIRC => return self.HSIRC_get(),
USART2MultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn USART2output_get(&self) -> Result<f32, ClockError> {
self.USART2Mult_get()
}
fn LPUART1Mult_get(&self) -> Result<f32, ClockError> {
match self.LPUART1Mult {
LPUART1MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
LPUART1MultConf::SysCLKOutput => return self.SysCLKOutput_get(),
LPUART1MultConf::HSIRC => return self.HSIRC_get(),
LPUART1MultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn LPUART1output_get(&self) -> Result<f32, ClockError> {
self.LPUART1Mult_get()
}
fn LPTIM1Mult_get(&self) -> Result<f32, ClockError> {
match self.LPTIM1Mult {
LPTIM1MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
LPTIM1MultConf::LSIRC => return self.LSIRC_get(),
LPTIM1MultConf::HSIRC => return self.HSIRC_get(),
LPTIM1MultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn LPTIM1output_get(&self) -> Result<f32, ClockError> {
self.LPTIM1Mult_get()
}
fn LPTIM2Mult_get(&self) -> Result<f32, ClockError> {
match self.LPTIM2Mult {
LPTIM2MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
LPTIM2MultConf::LSIRC => return self.LSIRC_get(),
LPTIM2MultConf::HSIRC => return self.HSIRC_get(),
LPTIM2MultConf::LSEOSC => return self.LSEOSC_get(),
};
}
pub fn LPTIM2output_get(&self) -> Result<f32, ClockError> {
self.LPTIM2Mult_get()
}
pub fn ADCoutput_get(&self) -> Result<f32, ClockError> {
let input = self.SysCLKOutput_get()?;
if input > (80000000 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Overflow(input as u32, 80000000),
from: ClockNodes::SysCLKOutput,
to: ClockNodes::ADCoutput,
});
} else if input < (140000 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Underflow(input as u32, 140000),
from: ClockNodes::SysCLKOutput,
to: ClockNodes::ADCoutput,
});
}
Ok(input)
}
fn CK48Mult_get(&self) -> Result<f32, ClockError> {
match self.CK48Mult {
CK48MultConf::PLLQ => return self.PLLQ_get(),
CK48MultConf::MSIRC => return self.MSIRC_get(),
CK48MultConf::HSI48RC => return self.HSI48RC_get(),
};
}
pub fn CK48output_get(&self) -> Result<f32, ClockError> {
self.CK48Mult_get()
}
pub fn RNGoutput_get(&self) -> Result<f32, ClockError> {
let input = self.CK48Mult_get()?;
if input > (48000000 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Overflow(input as u32, 48000000),
from: ClockNodes::CK48Mult,
to: ClockNodes::RNGoutput,
});
} else if input < (0 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Underflow(input as u32, 0),
from: ClockNodes::CK48Mult,
to: ClockNodes::RNGoutput,
});
}
Ok(input)
}
fn I2C1Mult_get(&self) -> Result<f32, ClockError> {
match self.I2C1Mult {
I2C1MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
I2C1MultConf::SysCLKOutput => return self.SysCLKOutput_get(),
I2C1MultConf::HSIRC => return self.HSIRC_get(),
};
}
pub fn I2C1output_get(&self) -> Result<f32, ClockError> {
self.I2C1Mult_get()
}
fn I2C3Mult_get(&self) -> Result<f32, ClockError> {
match self.I2C3Mult {
I2C3MultConf::APB1Prescaler => return self.APB1Prescaler_get(),
I2C3MultConf::SysCLKOutput => return self.SysCLKOutput_get(),
I2C3MultConf::HSIRC => return self.HSIRC_get(),
};
}
pub fn I2C3output_get(&self) -> Result<f32, ClockError> {
self.I2C3Mult_get()
}
fn MCOMult_get(&self) -> Result<f32, ClockError> {
match self.MCOMult {
MCOMultConf::LSEOSC => return self.LSEOSC_get(),
MCOMultConf::LSIRC => return self.LSIRC_get(),
MCOMultConf::HSEOSC => return self.HSEOSC_get(),
MCOMultConf::SysCLKOutput => return self.SysCLKOutput_get(),
MCOMultConf::HSIRC => return self.HSIRC_get(),
MCOMultConf::HSI48RC => return self.HSI48RC_get(),
};
}
fn MCODiv_get(&self) -> Result<f32, ClockError> {
let input = self.MCOMult_get()? as f32;
let value = self.MCODiv.get()? as f32;
Ok((input / value) as f32)
}
pub fn MCOPin_get(&self) -> Result<f32, ClockError> {
self.MCODiv_get()
}
fn AHBPrescaler_get(&self) -> Result<f32, ClockError> {
let input = self.SysCLKOutput_get()? as f32;
let value = self.AHBPrescaler.get()? as f32;
Ok((input / value) as f32)
}
pub fn PWRCLKoutput_get(&self) -> Result<f32, ClockError> {
self.SysCLKOutput_get()
}
pub fn AHBOutput_get(&self) -> Result<f32, ClockError> {
self.AHBPrescaler_get()
}
pub fn HCLKOutput_get(&self) -> Result<f32, ClockError> {
self.AHBOutput_get()
}
fn CortexPrescaler_get(&self) -> Result<f32, ClockError> {
let input = self.AHBOutput_get()? as f32;
let value = self.CortexPrescaler.get()? as f32;
Ok((input / value) as f32)
}
pub fn CortexSysOutput_get(&self) -> Result<f32, ClockError> {
self.CortexPrescaler_get()
}
pub fn FCLKCortexOutput_get(&self) -> Result<f32, ClockError> {
self.AHBOutput_get()
}
fn APB1Prescaler_get(&self) -> Result<f32, ClockError> {
let input = self.AHBOutput_get()? as f32;
let value = self.APB1Prescaler.get()? as f32;
Ok((input / value) as f32)
}
pub fn APB1Output_get(&self) -> Result<f32, ClockError> {
let input = self.APB1Prescaler_get()?;
if input > (80000000 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Overflow(input as u32, 80000000),
from: ClockNodes::APB1Prescaler,
to: ClockNodes::APB1Output,
});
} else if input < (0 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Underflow(input as u32, 0),
from: ClockNodes::APB1Prescaler,
to: ClockNodes::APB1Output,
});
}
Ok(input)
}
fn TimPrescalerAPB1_get(&self) -> Result<f32, ClockError> {
let input = self.APB1Prescaler_get()? as f32;
let value = 2 as f32;
Ok((input * value) as f32)
}
pub fn TimPrescOut1_get(&self) -> Result<f32, ClockError> {
self.TimPrescalerAPB1_get()
}
fn APB2Prescaler_get(&self) -> Result<f32, ClockError> {
let input = self.AHBOutput_get()? as f32;
let value = self.APB2Prescaler.get()? as f32;
Ok((input / value) as f32)
}
pub fn APB2Output_get(&self) -> Result<f32, ClockError> {
let input = self.APB2Prescaler_get()?;
if input > (80000000 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Overflow(input as u32, 80000000),
from: ClockNodes::APB2Prescaler,
to: ClockNodes::APB2Output,
});
} else if input < (0 as f32) {
return Err(ClockError {
err_type: ClockErrorType::Underflow(input as u32, 0),
from: ClockNodes::APB2Prescaler,
to: ClockNodes::APB2Output,
});
}
Ok(input)
}
fn TimPrescalerAPB2_get(&self) -> Result<f32, ClockError> {
let input = self.APB2Prescaler_get()? as f32;
let value = 2 as f32;
Ok((input * value) as f32)
}
pub fn TimPrescOut2_get(&self) -> Result<f32, ClockError> {
self.TimPrescalerAPB2_get()
}
fn PLLN_get(&self) -> Result<f32, ClockError> {
let input = self.PLLM_get()? as f32;
let value = self.PLLN.get()? as f32;
Ok((input * value) as f32)
}
fn PLLQ_get(&self) -> Result<f32, ClockError> {
let input = self.PLLN_get()? as f32;
let value = self.PLLQ.get()? as f32;
Ok((input / value) as f32)
}
pub fn PLLQoutput_get(&self) -> Result<f32, ClockError> {
self.PLLQ_get()
}
fn PLLR_get(&self) -> Result<f32, ClockError> {
let input = self.PLLN_get()? as f32;
let value = self.PLLR.get()? as f32;
Ok((input / value) as f32)
}
}