cinrs-core 0.2.0

The C front end behind the cinrs crate: lexer, preprocessor, parser, semantic analysis, code generation
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

/* <vaesintrin.h> — the vaes intrinsics, as GCC arranges them.
 *
 * Written by crates/cinrs-core/tests/x86_intrinsics.rs; the regions below
 * are regenerated from `core::arch`'s source, and an empty one is an
 * instruction set whose intrinsics are all still unstable there. Needs the
 * instruction set in `__attribute__((target("…")))` on the function that
 * calls them, and a function that passes or returns a 512-bit vector by
 * value needs `target("avx512f")`; see <immintrin.h>.
 */
#ifndef _CINRS_VAESINTRIN_H
#if !defined(__i386__) && !defined(__x86_64__)
#error "the Intel intrinsics headers are x86 only; this unit is being translated for another architecture. Guard the #include with #ifdef __x86_64__, or see doc/features.md, 'SIMD intrinsics'."
#elif !defined(_CINRS_IMMINTRIN_H)
/* On its own: <immintrin.h> includes this file back, in its place. */
#include <immintrin.h>
#else
#define _CINRS_VAESINTRIN_H

/* @generated vaes — see crates/cinrs-core/tests/x86_intrinsics.rs */
__m256i _mm256_aesdec_epi128(__m256i, __m256i);
__m256i _mm256_aesdeclast_epi128(__m256i, __m256i);
__m256i _mm256_aesenc_epi128(__m256i, __m256i);
__m256i _mm256_aesenclast_epi128(__m256i, __m256i);
__m512i _mm512_aesdec_epi128(__m512i, __m512i);
__m512i _mm512_aesdeclast_epi128(__m512i, __m512i);
__m512i _mm512_aesenc_epi128(__m512i, __m512i);
__m512i _mm512_aesenclast_epi128(__m512i, __m512i);
/* @generated end */

#endif
#endif /* _CINRS_VAESINTRIN_H */