#![doc = "Peripheral access API for CH572SFR microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_auto_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 2;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic {
use core::marker;
#[doc = " Generic peripheral accessor"]
pub struct Periph<RB, const A: usize> {
_marker: marker::PhantomData<RB>,
}
unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
impl<RB, const A: usize> Periph<RB, A> {
#[doc = "Pointer to the register block"]
pub const PTR: *const RB = A as *const _;
#[doc = "Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const RB {
Self::PTR
}
#[doc = " Steal an instance of this peripheral"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = " that may race with any existing instances, for example by only"]
#[doc = " accessing read-only or write-only registers, or by consuming the"]
#[doc = " original peripheral and using critical sections to coordinate"]
#[doc = " access between multiple new instances."]
#[doc = ""]
#[doc = " Additionally, other software such as HALs may rely on only one"]
#[doc = " peripheral instance existing to ensure memory safety; ensure"]
#[doc = " no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: marker::PhantomData,
}
}
}
impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
type Target = RB;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg:
Copy
+ From<bool>
+ core::ops::BitOr<Output = Self>
+ core::ops::BitAnd<Output = Self>
+ core::ops::BitOrAssign
+ core::ops::BitAndAssign
+ core::ops::Not<Output = Self>
+ core::ops::Shl<u8, Output = Self>
{
#[doc = " Mask for bits of width `WI`"]
fn mask<const WI: u8>() -> Self;
#[doc = " `0`"]
const ZERO: Self;
#[doc = " `1`"]
const ONE: Self;
}
macro_rules! raw_reg {
($ U : ty , $ size : literal , $ mask : ident) => {
impl RawReg for $U {
#[inline(always)]
fn mask<const WI: u8>() -> Self {
$mask::<WI>()
}
const ZERO: Self = 0;
const ONE: Self = 1;
}
const fn $mask<const WI: u8>() -> $U {
<$U>::MAX >> ($size - WI)
}
impl FieldSpec for $U {
type Ux = $U;
}
};
}
raw_reg!(u8, 8, mask_u8);
raw_reg!(u16, 16, mask_u16);
raw_reg!(u32, 32, mask_u32);
raw_reg!(u64, 64, mask_u64);
#[doc = " Raw register type"]
pub trait RegisterSpec {
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux: RawReg;
}
#[doc = " Raw field type"]
pub trait FieldSpec: Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
}
#[doc = " Marker for fields with fixed values"]
pub trait IsEnum: FieldSpec {}
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable: RegisterSpec {}
#[doc = " Trait implemented by writeable registers."]
#[doc = ""]
#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
#[doc = ""]
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable: RegisterSpec {
#[doc = " Is it safe to write any bits to register"]
type Safety;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
}
#[doc = " Reset value of the register."]
#[doc = ""]
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
#[doc = " register by using the `reset` method."]
pub trait Resettable: RegisterSpec {
#[doc = " Reset value of the register."]
const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
#[doc = " Reset value of the register."]
#[inline(always)]
fn reset_value() -> Self::Ux {
Self::RESET_VALUE
}
}
#[doc(hidden)]
pub mod raw {
use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
pub struct R<REG: RegisterSpec> {
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct W<REG: RegisterSpec> {
#[doc = "Writable bits"]
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct FieldReader<FI = u8>
where
FI: FieldSpec,
{
pub(crate) bits: FI::Ux,
_reg: marker::PhantomData<FI>,
}
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: FI::Ux) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
pub struct BitReader<FI = bool> {
pub(crate) bits: bool,
_reg: marker::PhantomData<FI>,
}
impl<FI> BitReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: bool) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, Safety)>,
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
#[must_use = "after creating `BitWriter` you need to call bit setting method"]
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, M)>,
}
impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
}
#[doc = " Register reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
#[doc = " method."]
pub type R<REG> = raw::R<REG>;
impl<REG: RegisterSpec> R<REG> {
#[doc = " Reads raw bits from register."]
#[inline(always)]
pub const fn bits(&self) -> REG::Ux {
self.bits
}
}
impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
where
REG::Ux: PartialEq,
FI: Copy,
REG::Ux: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(®::Ux::from(*other))
}
}
#[doc = " Register writer."]
#[doc = ""]
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W<REG> = raw::W<REG>;
impl<REG: Writable> W<REG> {
#[doc = " Writes raw bits to the register."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
impl<REG> W<REG>
where
REG: Writable<Safety = Safe>,
{
#[doc = " Writes raw bits to the register."]
#[inline(always)]
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = " Field reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of fields."]
pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
#[doc = " Bit-wise field reader"]
pub type BitReader<FI = bool> = raw::BitReader<FI>;
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Reads raw bits from field."]
#[inline(always)]
pub const fn bits(&self) -> FI::Ux {
self.bits
}
}
impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
impl<FI> PartialEq<FI> for FieldReader<FI>
where
FI: FieldSpec + Copy,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&FI::Ux::from(*other))
}
}
impl<FI> PartialEq<FI> for BitReader<FI>
where
FI: Copy,
bool: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&bool::from(*other))
}
}
impl<FI> BitReader<FI> {
#[doc = " Value of the field as raw bits."]
#[inline(always)]
pub const fn bit(&self) -> bool {
self.bits
}
#[doc = " Returns `true` if the bit is clear (0)."]
#[inline(always)]
pub const fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = " Returns `true` if the bit is set (1)."]
#[inline(always)]
pub const fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl<FI> core::fmt::Debug for BitReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
#[doc = " Marker for register/field writers which can take any value of specified width"]
pub struct Safe;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct Range<const MIN: u64, const MAX: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeFrom<const MIN: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeTo<const MAX: u64>;
#[doc = " Write field Proxy"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
raw::FieldWriter<'a, REG, WI, FI, Safety>;
impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
WI
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
}
impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN && value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: IsEnum,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
unsafe { self.bits(FI::Ux::from(variant)) }
}
}
macro_rules! bit_proxy {
($ writer : ident , $ mwv : ident) => {
#[doc(hidden)]
pub struct $mwv;
#[doc = " Bit-wise write field proxy"]
pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
impl<'a, REG, FI> $writer<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = 1;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
Self::WIDTH
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes bit to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
self.bit(bool::from(variant))
}
}
};
}
bit_proxy!(BitWriter, BitM);
bit_proxy!(BitWriter1S, Bit1S);
bit_proxy!(BitWriter0C, Bit0C);
bit_proxy!(BitWriter1C, Bit1C);
bit_proxy!(BitWriter0S, Bit0S);
bit_proxy!(BitWriter1T, Bit1T);
bit_proxy!(BitWriter0T, Bit0T);
impl<'a, REG, FI> BitWriter<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Clears the field bit by passing one"]
#[inline(always)]
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Sets the field bit by passing zero"]
#[inline(always)]
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing one"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing zero"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes bits to a `Writable` register and produce a value."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[doc = ""]
#[doc = " Values can be returned from the closure:"]
#[doc = " ```ignore"]
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
#[doc = " ```"]
#[inline(always)]
pub fn from_write<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes 0 to a `Writable` register and produces a value."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F) -> REG::Ux
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
let value = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits;
self.register.set(value);
value
}
#[doc = " Modifies the contents of the register by reading and then writing it"]
#[doc = " and produces a value."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.modify(|r, w| {"]
#[doc = " let new_bits = r.bits() | 3;"]
#[doc = " unsafe {"]
#[doc = " w.bits(new_bits);"]
#[doc = " }"]
#[doc = ""]
#[doc = " new_bits"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn from_modify<F, T>(&self, f: F) -> T
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
{
let bits = self.register.get();
let mut writer = W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut writer,
);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
where
R<REG>: core::fmt::Debug,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
}
#[cfg(feature = "rt")]
extern "C" {
fn GPIOA();
fn SPI();
fn BLEB();
fn BLEL();
fn USBFS();
fn TMR();
fn UART0();
fn UART();
fn RTC();
fn CMP();
fn I2C();
fn PWMx();
fn KEYSCAN();
fn ENCODER();
fn WDOG_BAT();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
pub _handler: unsafe extern "C" fn(),
pub _reserved: usize,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[no_mangle]
pub static __EXTERNAL_INTERRUPTS: [Vector; 36] = [
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: GPIOA },
Vector { _reserved: 0 },
Vector { _handler: SPI },
Vector { _handler: BLEB },
Vector { _handler: BLEL },
Vector { _handler: USBFS },
Vector { _reserved: 0 },
Vector { _handler: TMR },
Vector { _reserved: 0 },
Vector { _handler: UART0 },
Vector { _handler: UART },
Vector { _handler: RTC },
Vector { _handler: CMP },
Vector { _handler: I2C },
Vector { _handler: PWMx },
Vector { _reserved: 0 },
Vector { _handler: KEYSCAN },
Vector { _handler: ENCODER },
Vector { _handler: WDOG_BAT },
];
#[doc(hidden)]
pub mod interrupt {
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "17 - GPIOA_IRQHandler"]
GPIOA = 17,
#[doc = "19 - SPI_IRQHandler"]
SPI = 19,
#[doc = "20 - BB_IRQHandler"]
BLEB = 20,
#[doc = "21 - LLE_IRQHandler"]
BLEL = 21,
#[doc = "22 - USB_IRQHandler"]
USBFS = 22,
#[doc = "24 - TMR_IRQHandler"]
TMR = 24,
#[doc = "26 - UART0_IRQHandler"]
UART0 = 26,
#[doc = "27 - UART_IRQHandler"]
UART = 27,
#[doc = "28 - RTC_IRQHandler"]
RTC = 28,
#[doc = "29 - CMP_IRQHandler"]
CMP = 29,
#[doc = "30 - I2C_IRQHandler"]
I2C = 30,
#[doc = "31 - PWMX_IRQHandler"]
PWMx = 31,
#[doc = "33 - KEYSCAN_IRQHandler"]
KEYSCAN = 33,
#[doc = "34 - ENCODER_IRQHandler"]
ENCODER = 34,
#[doc = "35 - WDOG_BAT_IRQHandler"]
WDOG_BAT = 35,
}
#[doc = r" TryFromInterruptError"]
#[derive(Debug, Copy, Clone)]
pub struct TryFromInterruptError(());
impl Interrupt {
#[doc = r" Attempt to convert a given value into an `Interrupt`"]
#[inline]
pub fn try_from(value: u8) -> Result<Self, TryFromInterruptError> {
match value {
17 => Ok(Interrupt::GPIOA),
19 => Ok(Interrupt::SPI),
20 => Ok(Interrupt::BLEB),
21 => Ok(Interrupt::BLEL),
22 => Ok(Interrupt::USBFS),
24 => Ok(Interrupt::TMR),
26 => Ok(Interrupt::UART0),
27 => Ok(Interrupt::UART),
28 => Ok(Interrupt::RTC),
29 => Ok(Interrupt::CMP),
30 => Ok(Interrupt::I2C),
31 => Ok(Interrupt::PWMx),
33 => Ok(Interrupt::KEYSCAN),
34 => Ok(Interrupt::ENCODER),
35 => Ok(Interrupt::WDOG_BAT),
_ => Err(TryFromInterruptError(())),
}
}
}
#[cfg(feature = "rt")]
#[macro_export]
#[doc = r" Assigns a handler to an interrupt"]
#[doc = r""]
#[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"]
#[doc = r" function that will be used as the handler of that interrupt. That function"]
#[doc = r" must have signature `fn()`."]
#[doc = r""]
#[doc = r" Optionally, a third argument may be used to declare interrupt local data."]
#[doc = r" The handler will have exclusive access to these *local* variables on each"]
#[doc = r" invocation. If the third argument is used then the signature of the handler"]
#[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"]
#[doc = r" passed to the macro."]
#[doc = r""]
#[doc = r" # Example"]
#[doc = r""]
#[doc = r" ``` ignore"]
#[doc = r" interrupt!(TIM2, periodic);"]
#[doc = r""]
#[doc = r" fn periodic() {"]
#[doc = r#" print!(".");"#]
#[doc = r" }"]
#[doc = r""]
#[doc = r" interrupt!(TIM3, tick, locals: {"]
#[doc = r" tick: bool = false;"]
#[doc = r" });"]
#[doc = r""]
#[doc = r" fn tick(locals: &mut TIM3::Locals) {"]
#[doc = r" locals.tick = !locals.tick;"]
#[doc = r""]
#[doc = r" if locals.tick {"]
#[doc = r#" println!("Tick");"#]
#[doc = r" } else {"]
#[doc = r#" println!("Tock");"#]
#[doc = r" }"]
#[doc = r" }"]
#[doc = r" ```"]
macro_rules ! interrupt { ($ NAME : ident , $ path : path , locals : { $ ($ lvar : ident : $ lty : ty = $ lval : expr ;) * }) => {
#[allow (non_snake_case)] mod $ NAME { pub struct Locals { $ (pub $ lvar : $ lty ,) * } }
#[allow (non_snake_case)]
#[no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ($ lvar : $ lval ,) * } ; let f : fn (& mut self :: $ NAME :: Locals) = $ path ; f (unsafe { & mut LOCALS }) ; } } ; ($ NAME : ident , $ path : path) => {
#[allow (non_snake_case)]
#[no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn () = $ path ; f () ; } } }
}
pub use self::interrupt::Interrupt;
#[doc = "System Control Register"]
pub type Sys = crate::Periph<sys::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Sys {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sys").finish()
}
}
#[doc = "System Control Register"]
pub mod sys {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r32_iwdg_kr: R32IwdgKr,
r32_iwdg_cfg: R32IwdgCfg,
r8_clk_sys_cfg: R8ClkSysCfg,
_reserved3: [u8; 0x01],
r8_hfck_pwr_ctrl: R8HfckPwrCtrl,
_reserved4: [u8; 0x01],
r8_slp_clk_off0: R8SlpClkOff0,
r8_slp_clk_off1: R8SlpClkOff1,
r8_slp_wake_ctrl: R8SlpWakeCtrl,
r8_slp_power_ctrl: R8SlpPowerCtrl,
_reserved8: [u8; 0x08],
r16_pin_alternate: R16PinAlternate,
r16_pin_alternate_h: R16PinAlternateH,
r8_long_rst_cfg: R8LongRstCfg,
r8_slp_clk_off2: R8SlpClkOff2,
r16_slp_wake_cfg: R16SlpWakeCfg,
r16_power_plan: R16PowerPlan,
r16_aux_power_adj: R16AuxPowerAdj,
r8_bat_det_ctrl: R8BatDetCtrl,
r8_bat_det_cfg: R8BatDetCfg,
r8_bat_status: R8BatStatus,
_reserved18: [u8; 0x08],
r8_lsi_config: R8LsiConfig,
}
impl RegisterBlock {
#[doc = "0x00 - WO, Watchdog key register, SAM"]
#[inline(always)]
pub const fn r32_iwdg_kr(&self) -> &R32IwdgKr {
&self.r32_iwdg_kr
}
#[doc = "0x04 - RW, Watchdog configuration register, SAM"]
#[inline(always)]
pub const fn r32_iwdg_cfg(&self) -> &R32IwdgCfg {
&self.r32_iwdg_cfg
}
#[doc = "0x08 - RWA, system clock configuration, SAM"]
#[inline(always)]
pub const fn r8_clk_sys_cfg(&self) -> &R8ClkSysCfg {
&self.r8_clk_sys_cfg
}
#[doc = "0x0a - RWA, High frequency clock module power control register, SAM"]
#[inline(always)]
pub const fn r8_hfck_pwr_ctrl(&self) -> &R8HfckPwrCtrl {
&self.r8_hfck_pwr_ctrl
}
#[doc = "0x0c - RWA, sleep clock off control byte 0, SAM"]
#[inline(always)]
pub const fn r8_slp_clk_off0(&self) -> &R8SlpClkOff0 {
&self.r8_slp_clk_off0
}
#[doc = "0x0d - RWA, sleep clock off control byte 1, SAM"]
#[inline(always)]
pub const fn r8_slp_clk_off1(&self) -> &R8SlpClkOff1 {
&self.r8_slp_clk_off1
}
#[doc = "0x0e - RWA, wake control, SAM"]
#[inline(always)]
pub const fn r8_slp_wake_ctrl(&self) -> &R8SlpWakeCtrl {
&self.r8_slp_wake_ctrl
}
#[doc = "0x0f - RWA, peripherals power down control, SAM"]
#[inline(always)]
pub const fn r8_slp_power_ctrl(&self) -> &R8SlpPowerCtrl {
&self.r8_slp_power_ctrl
}
#[doc = "0x18 - RW, function pin alternate configuration"]
#[inline(always)]
pub const fn r16_pin_alternate(&self) -> &R16PinAlternate {
&self.r16_pin_alternate
}
#[doc = "0x1a - RW, function pin high alternate configuration"]
#[inline(always)]
pub const fn r16_pin_alternate_h(&self) -> &R16PinAlternateH {
&self.r16_pin_alternate_h
}
#[doc = "0x1c - RWA, Long reset configuration register"]
#[inline(always)]
pub const fn r8_long_rst_cfg(&self) -> &R8LongRstCfg {
&self.r8_long_rst_cfg
}
#[doc = "0x1d - RWA, Sleep clock control register 2"]
#[inline(always)]
pub const fn r8_slp_clk_off2(&self) -> &R8SlpClkOff2 {
&self.r8_slp_clk_off2
}
#[doc = "0x1e - RWA, Sleep clock control register"]
#[inline(always)]
pub const fn r16_slp_wake_cfg(&self) -> &R16SlpWakeCfg {
&self.r16_slp_wake_cfg
}
#[doc = "0x20 - RWA, power plan before sleep instruction, SAM"]
#[inline(always)]
pub const fn r16_power_plan(&self) -> &R16PowerPlan {
&self.r16_power_plan
}
#[doc = "0x22 - RWA, aux power adjust control, SAM"]
#[inline(always)]
pub const fn r16_aux_power_adj(&self) -> &R16AuxPowerAdj {
&self.r16_aux_power_adj
}
#[doc = "0x24 - RWA, battery voltage detector control, SAM"]
#[inline(always)]
pub const fn r8_bat_det_ctrl(&self) -> &R8BatDetCtrl {
&self.r8_bat_det_ctrl
}
#[doc = "0x25 - RWA, battery voltage detector configuration, SAM"]
#[inline(always)]
pub const fn r8_bat_det_cfg(&self) -> &R8BatDetCfg {
&self.r8_bat_det_cfg
}
#[doc = "0x26 - RO, battery status"]
#[inline(always)]
pub const fn r8_bat_status(&self) -> &R8BatStatus {
&self.r8_bat_status
}
#[doc = "0x2f - RWA, LSI configure register"]
#[inline(always)]
pub const fn r8_lsi_config(&self) -> &R8LsiConfig {
&self.r8_lsi_config
}
}
#[doc = "R32_IWDG_KR (w) register accessor: WO, Watchdog key register, SAM\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_iwdg_kr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_iwdg_kr`] module"]
#[doc(alias = "R32_IWDG_KR")]
pub type R32IwdgKr = crate::Reg<r32_iwdg_kr::R32IwdgKrSpec>;
#[doc = "WO, Watchdog key register, SAM"]
pub mod r32_iwdg_kr {
#[doc = "Register `R32_IWDG_KR` writer"]
pub type W = crate::W<R32IwdgKrSpec>;
#[doc = "Field `IWDG_KR` writer - RO,KEY \\[15:0\\]: Key value"]
pub type IwdgKrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl W {
#[doc = "Bits 0:15 - RO,KEY \\[15:0\\]: Key value"]
#[inline(always)]
pub fn iwdg_kr(&mut self) -> IwdgKrW<R32IwdgKrSpec> {
IwdgKrW::new(self, 0)
}
}
#[doc = "WO, Watchdog key register, SAM\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_iwdg_kr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32IwdgKrSpec;
impl crate::RegisterSpec for R32IwdgKrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_iwdg_kr::W`](W) writer structure"]
impl crate::Writable for R32IwdgKrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_IWDG_KR to value 0"]
impl crate::Resettable for R32IwdgKrSpec {}
}
#[doc = "R32_IWDG_CFG (rw) register accessor: RW, Watchdog configuration register, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_iwdg_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_iwdg_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_iwdg_cfg`] module"]
#[doc(alias = "R32_IWDG_CFG")]
pub type R32IwdgCfg = crate::Reg<r32_iwdg_cfg::R32IwdgCfgSpec>;
#[doc = "RW, Watchdog configuration register, SAM"]
pub mod r32_iwdg_cfg {
#[doc = "Register `R32_IWDG_CFG` reader"]
pub type R = crate::R<R32IwdgCfgSpec>;
#[doc = "Register `R32_IWDG_CFG` writer"]
pub type W = crate::W<R32IwdgCfgSpec>;
#[doc = "Field `RLR` reader - RW, RL \\[11:0\\]: Watchdog counter reload"]
pub type RlrR = crate::FieldReader<u16>;
#[doc = "Field `RLR` writer - RW, RL \\[11:0\\]: Watchdog counter reload"]
pub type RlrW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `PR` reader - RO, Pre division factor (with write protection)"]
pub type PrR = crate::FieldReader;
#[doc = "Field `PR` writer - RO, Pre division factor (with write protection)"]
pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PVU` reader - RO, Configure register update flag bit (with write protection)"]
pub type PvuR = crate::BitReader;
#[doc = "Field `COUNT` reader - RO, Watchdog countdown counter"]
pub type CountR = crate::FieldReader<u16>;
#[doc = "Field `STOP_EN` reader - RW, Watchdog stop enabled (with write protection)"]
pub type StopEnR = crate::BitReader;
#[doc = "Field `WR_PROTECT` reader - RW, Write protection"]
pub type WrProtectR = crate::BitReader;
#[doc = "Field `IWDG_EN` reader - RW, Watch dog start switch: 1: ON; 0: Close"]
pub type IwdgEnR = crate::BitReader;
impl R {
#[doc = "Bits 0:11 - RW, RL \\[11:0\\]: Watchdog counter reload"]
#[inline(always)]
pub fn rlr(&self) -> RlrR {
RlrR::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:14 - RO, Pre division factor (with write protection)"]
#[inline(always)]
pub fn pr(&self) -> PrR {
PrR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15 - RO, Configure register update flag bit (with write protection)"]
#[inline(always)]
pub fn pvu(&self) -> PvuR {
PvuR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:27 - RO, Watchdog countdown counter"]
#[inline(always)]
pub fn count(&self) -> CountR {
CountR::new(((self.bits >> 16) & 0x0fff) as u16)
}
#[doc = "Bit 29 - RW, Watchdog stop enabled (with write protection)"]
#[inline(always)]
pub fn stop_en(&self) -> StopEnR {
StopEnR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - RW, Write protection"]
#[inline(always)]
pub fn wr_protect(&self) -> WrProtectR {
WrProtectR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - RW, Watch dog start switch: 1: ON; 0: Close"]
#[inline(always)]
pub fn iwdg_en(&self) -> IwdgEnR {
IwdgEnR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:11 - RW, RL \\[11:0\\]: Watchdog counter reload"]
#[inline(always)]
pub fn rlr(&mut self) -> RlrW<R32IwdgCfgSpec> {
RlrW::new(self, 0)
}
#[doc = "Bits 12:14 - RO, Pre division factor (with write protection)"]
#[inline(always)]
pub fn pr(&mut self) -> PrW<R32IwdgCfgSpec> {
PrW::new(self, 12)
}
}
#[doc = "RW, Watchdog configuration register, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_iwdg_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_iwdg_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32IwdgCfgSpec;
impl crate::RegisterSpec for R32IwdgCfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_iwdg_cfg::R`](R) reader structure"]
impl crate::Readable for R32IwdgCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_iwdg_cfg::W`](W) writer structure"]
impl crate::Writable for R32IwdgCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_IWDG_CFG to value 0"]
impl crate::Resettable for R32IwdgCfgSpec {}
}
#[doc = "R8_CLK_SYS_CFG (rw) register accessor: RWA, system clock configuration, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_clk_sys_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_clk_sys_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_clk_sys_cfg`] module"]
#[doc(alias = "R8_CLK_SYS_CFG")]
pub type R8ClkSysCfg = crate::Reg<r8_clk_sys_cfg::R8ClkSysCfgSpec>;
#[doc = "RWA, system clock configuration, SAM"]
pub mod r8_clk_sys_cfg {
#[doc = "Register `R8_CLK_SYS_CFG` reader"]
pub type R = crate::R<R8ClkSysCfgSpec>;
#[doc = "Register `R8_CLK_SYS_CFG` writer"]
pub type W = crate::W<R8ClkSysCfgSpec>;
#[doc = "Field `RB_CLK_PLL_DIV` reader - RWA, output clock divider from PLL or CK32M"]
pub type RbClkPllDivR = crate::FieldReader;
#[doc = "Field `RB_CLK_PLL_DIV` writer - RWA, output clock divider from PLL or CK32M"]
pub type RbClkPllDivW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RB_CLK_SYS_MOD` reader - RWA, system clock source mode: 00=divided from 32MHz"]
pub type RbClkSysModR = crate::FieldReader;
#[doc = "Field `RB_CLK_SYS_MOD` writer - RWA, system clock source mode: 00=divided from 32MHz"]
pub type RbClkSysModW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:4 - RWA, output clock divider from PLL or CK32M"]
#[inline(always)]
pub fn rb_clk_pll_div(&self) -> RbClkPllDivR {
RbClkPllDivR::new(self.bits & 0x1f)
}
#[doc = "Bits 6:7 - RWA, system clock source mode: 00=divided from 32MHz"]
#[inline(always)]
pub fn rb_clk_sys_mod(&self) -> RbClkSysModR {
RbClkSysModR::new((self.bits >> 6) & 3)
}
}
impl W {
#[doc = "Bits 0:4 - RWA, output clock divider from PLL or CK32M"]
#[inline(always)]
pub fn rb_clk_pll_div(&mut self) -> RbClkPllDivW<R8ClkSysCfgSpec> {
RbClkPllDivW::new(self, 0)
}
#[doc = "Bits 6:7 - RWA, system clock source mode: 00=divided from 32MHz"]
#[inline(always)]
pub fn rb_clk_sys_mod(&mut self) -> RbClkSysModW<R8ClkSysCfgSpec> {
RbClkSysModW::new(self, 6)
}
}
#[doc = "RWA, system clock configuration, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_clk_sys_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_clk_sys_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8ClkSysCfgSpec;
impl crate::RegisterSpec for R8ClkSysCfgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_clk_sys_cfg::R`](R) reader structure"]
impl crate::Readable for R8ClkSysCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_clk_sys_cfg::W`](W) writer structure"]
impl crate::Writable for R8ClkSysCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_CLK_SYS_CFG to value 0x05"]
impl crate::Resettable for R8ClkSysCfgSpec {
const RESET_VALUE: u8 = 0x05;
}
}
#[doc = "R8_HFCK_PWR_CTRL (rw) register accessor: RWA, High frequency clock module power control register, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_hfck_pwr_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_hfck_pwr_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_hfck_pwr_ctrl`] module"]
#[doc(alias = "R8_HFCK_PWR_CTRL")]
pub type R8HfckPwrCtrl = crate::Reg<r8_hfck_pwr_ctrl::R8HfckPwrCtrlSpec>;
#[doc = "RWA, High frequency clock module power control register, SAM"]
pub mod r8_hfck_pwr_ctrl {
#[doc = "Register `R8_HFCK_PWR_CTRL` reader"]
pub type R = crate::R<R8HfckPwrCtrlSpec>;
#[doc = "Register `R8_HFCK_PWR_CTRL` writer"]
pub type W = crate::W<R8HfckPwrCtrlSpec>;
#[doc = "Field `RB_CLK_XT32M_PON` reader - RWA, External 32MHz oscillator HSE power control bit"]
pub type RbClkXt32mPonR = crate::BitReader;
#[doc = "Field `RB_CLK_XT32M_PON` writer - RWA, External 32MHz oscillator HSE power control bit"]
pub type RbClkXt32mPonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLK_XT32M_KEEP` reader - RWA, Used to control the stopping of the clock system in pause mode"]
pub type RbClkXt32mKeepR = crate::BitReader;
#[doc = "Field `RB_CLK_XT32M_KEEP` writer - RWA, Used to control the stopping of the clock system in pause mode"]
pub type RbClkXt32mKeepW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLK_PLL_PON` reader - RWA, PLL power control bit"]
pub type RbClkPllPonR = crate::BitReader;
#[doc = "Field `RB_CLK_PLL_PON` writer - RWA, PLL power control bit"]
pub type RbClkPllPonW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - RWA, External 32MHz oscillator HSE power control bit"]
#[inline(always)]
pub fn rb_clk_xt32m_pon(&self) -> RbClkXt32mPonR {
RbClkXt32mPonR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RWA, Used to control the stopping of the clock system in pause mode"]
#[inline(always)]
pub fn rb_clk_xt32m_keep(&self) -> RbClkXt32mKeepR {
RbClkXt32mKeepR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RWA, PLL power control bit"]
#[inline(always)]
pub fn rb_clk_pll_pon(&self) -> RbClkPllPonR {
RbClkPllPonR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - RWA, External 32MHz oscillator HSE power control bit"]
#[inline(always)]
pub fn rb_clk_xt32m_pon(&mut self) -> RbClkXt32mPonW<R8HfckPwrCtrlSpec> {
RbClkXt32mPonW::new(self, 2)
}
#[doc = "Bit 3 - RWA, Used to control the stopping of the clock system in pause mode"]
#[inline(always)]
pub fn rb_clk_xt32m_keep(&mut self) -> RbClkXt32mKeepW<R8HfckPwrCtrlSpec> {
RbClkXt32mKeepW::new(self, 3)
}
#[doc = "Bit 4 - RWA, PLL power control bit"]
#[inline(always)]
pub fn rb_clk_pll_pon(&mut self) -> RbClkPllPonW<R8HfckPwrCtrlSpec> {
RbClkPllPonW::new(self, 4)
}
}
#[doc = "RWA, High frequency clock module power control register, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_hfck_pwr_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_hfck_pwr_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8HfckPwrCtrlSpec;
impl crate::RegisterSpec for R8HfckPwrCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_hfck_pwr_ctrl::R`](R) reader structure"]
impl crate::Readable for R8HfckPwrCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_hfck_pwr_ctrl::W`](W) writer structure"]
impl crate::Writable for R8HfckPwrCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_HFCK_PWR_CTRL to value 0x14"]
impl crate::Resettable for R8HfckPwrCtrlSpec {
const RESET_VALUE: u8 = 0x14;
}
}
#[doc = "R8_SLP_CLK_OFF0 (rw) register accessor: RWA, sleep clock off control byte 0, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_slp_clk_off0`] module"]
#[doc(alias = "R8_SLP_CLK_OFF0")]
pub type R8SlpClkOff0 = crate::Reg<r8_slp_clk_off0::R8SlpClkOff0Spec>;
#[doc = "RWA, sleep clock off control byte 0, SAM"]
pub mod r8_slp_clk_off0 {
#[doc = "Register `R8_SLP_CLK_OFF0` reader"]
pub type R = crate::R<R8SlpClkOff0Spec>;
#[doc = "Register `R8_SLP_CLK_OFF0` writer"]
pub type W = crate::W<R8SlpClkOff0Spec>;
#[doc = "Field `RB_SLP_CLK_TMR` reader - RWA, Timer clock source"]
pub type RbSlpClkTmrR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_TMR` writer - RWA, Timer clock source"]
pub type RbSlpClkTmrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_CMP` reader - RWA, CMP clock source"]
pub type RbSlpClkCmpR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_CMP` writer - RWA, CMP clock source"]
pub type RbSlpClkCmpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_UART` reader - RWA, UART clock source"]
pub type RbSlpClkUartR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_UART` writer - RWA, UART clock source"]
pub type RbSlpClkUartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_KEYSCAN_WAKE` reader - RWA, KEYSCAN wakeup enable"]
pub type RbSlpKeyscanWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_KEYSCAN_WAKE` writer - RWA, KEYSCAN wakeup enable"]
pub type RbSlpKeyscanWakeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, Timer clock source"]
#[inline(always)]
pub fn rb_slp_clk_tmr(&self) -> RbSlpClkTmrR {
RbSlpClkTmrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, CMP clock source"]
#[inline(always)]
pub fn rb_slp_clk_cmp(&self) -> RbSlpClkCmpR {
RbSlpClkCmpR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - RWA, UART clock source"]
#[inline(always)]
pub fn rb_slp_clk_uart(&self) -> RbSlpClkUartR {
RbSlpClkUartR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7 - RWA, KEYSCAN wakeup enable"]
#[inline(always)]
pub fn rb_slp_keyscan_wake(&self) -> RbSlpKeyscanWakeR {
RbSlpKeyscanWakeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, Timer clock source"]
#[inline(always)]
pub fn rb_slp_clk_tmr(&mut self) -> RbSlpClkTmrW<R8SlpClkOff0Spec> {
RbSlpClkTmrW::new(self, 0)
}
#[doc = "Bit 1 - RWA, CMP clock source"]
#[inline(always)]
pub fn rb_slp_clk_cmp(&mut self) -> RbSlpClkCmpW<R8SlpClkOff0Spec> {
RbSlpClkCmpW::new(self, 1)
}
#[doc = "Bit 4 - RWA, UART clock source"]
#[inline(always)]
pub fn rb_slp_clk_uart(&mut self) -> RbSlpClkUartW<R8SlpClkOff0Spec> {
RbSlpClkUartW::new(self, 4)
}
#[doc = "Bit 7 - RWA, KEYSCAN wakeup enable"]
#[inline(always)]
pub fn rb_slp_keyscan_wake(&mut self) -> RbSlpKeyscanWakeW<R8SlpClkOff0Spec> {
RbSlpKeyscanWakeW::new(self, 7)
}
}
#[doc = "RWA, sleep clock off control byte 0, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SlpClkOff0Spec;
impl crate::RegisterSpec for R8SlpClkOff0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_slp_clk_off0::R`](R) reader structure"]
impl crate::Readable for R8SlpClkOff0Spec {}
#[doc = "`write(|w| ..)` method takes [`r8_slp_clk_off0::W`](W) writer structure"]
impl crate::Writable for R8SlpClkOff0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SLP_CLK_OFF0 to value 0"]
impl crate::Resettable for R8SlpClkOff0Spec {}
}
#[doc = "R8_SLP_CLK_OFF1 (rw) register accessor: RWA, sleep clock off control byte 1, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_slp_clk_off1`] module"]
#[doc(alias = "R8_SLP_CLK_OFF1")]
pub type R8SlpClkOff1 = crate::Reg<r8_slp_clk_off1::R8SlpClkOff1Spec>;
#[doc = "RWA, sleep clock off control byte 1, SAM"]
pub mod r8_slp_clk_off1 {
#[doc = "Register `R8_SLP_CLK_OFF1` reader"]
pub type R = crate::R<R8SlpClkOff1Spec>;
#[doc = "Register `R8_SLP_CLK_OFF1` writer"]
pub type W = crate::W<R8SlpClkOff1Spec>;
#[doc = "Field `RB_SLP_CLK_SPI` reader - RWA, close SPI clock"]
pub type RbSlpClkSpiR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_SPI` writer - RWA, close SPI clock"]
pub type RbSlpClkSpiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLK_OFF_AESCCM` reader - RWA, close AES_CCM clock"]
pub type RbClkOffAesccmR = crate::BitReader;
#[doc = "Field `RB_CLK_OFF_AESCCM` writer - RWA, close AES_CCM clock"]
pub type RbClkOffAesccmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_PWMX` reader - RWA, close PWMx clock"]
pub type RbSlpClkPwmxR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_PWMX` writer - RWA, close PWMx clock"]
pub type RbSlpClkPwmxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_I2C` reader - RWA, close I2C clock"]
pub type RbSlpClkI2cR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_I2C` writer - RWA, close I2C clock"]
pub type RbSlpClkI2cW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_USB` reader - RWA, close USB clock"]
pub type RbSlpClkUsbR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_USB` writer - RWA, close USB clock"]
pub type RbSlpClkUsbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_CLK_BLE` reader - RWA, close BLE clock"]
pub type RbSlpClkBleR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_BLE` writer - RWA, close BLE clock"]
pub type RbSlpClkBleW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, close SPI clock"]
#[inline(always)]
pub fn rb_slp_clk_spi(&self) -> RbSlpClkSpiR {
RbSlpClkSpiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, close AES_CCM clock"]
#[inline(always)]
pub fn rb_clk_off_aesccm(&self) -> RbClkOffAesccmR {
RbClkOffAesccmR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RWA, close PWMx clock"]
#[inline(always)]
pub fn rb_slp_clk_pwmx(&self) -> RbSlpClkPwmxR {
RbSlpClkPwmxR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RWA, close I2C clock"]
#[inline(always)]
pub fn rb_slp_clk_i2c(&self) -> RbSlpClkI2cR {
RbSlpClkI2cR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RWA, close USB clock"]
#[inline(always)]
pub fn rb_slp_clk_usb(&self) -> RbSlpClkUsbR {
RbSlpClkUsbR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7 - RWA, close BLE clock"]
#[inline(always)]
pub fn rb_slp_clk_ble(&self) -> RbSlpClkBleR {
RbSlpClkBleR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, close SPI clock"]
#[inline(always)]
pub fn rb_slp_clk_spi(&mut self) -> RbSlpClkSpiW<R8SlpClkOff1Spec> {
RbSlpClkSpiW::new(self, 0)
}
#[doc = "Bit 1 - RWA, close AES_CCM clock"]
#[inline(always)]
pub fn rb_clk_off_aesccm(&mut self) -> RbClkOffAesccmW<R8SlpClkOff1Spec> {
RbClkOffAesccmW::new(self, 1)
}
#[doc = "Bit 2 - RWA, close PWMx clock"]
#[inline(always)]
pub fn rb_slp_clk_pwmx(&mut self) -> RbSlpClkPwmxW<R8SlpClkOff1Spec> {
RbSlpClkPwmxW::new(self, 2)
}
#[doc = "Bit 3 - RWA, close I2C clock"]
#[inline(always)]
pub fn rb_slp_clk_i2c(&mut self) -> RbSlpClkI2cW<R8SlpClkOff1Spec> {
RbSlpClkI2cW::new(self, 3)
}
#[doc = "Bit 4 - RWA, close USB clock"]
#[inline(always)]
pub fn rb_slp_clk_usb(&mut self) -> RbSlpClkUsbW<R8SlpClkOff1Spec> {
RbSlpClkUsbW::new(self, 4)
}
#[doc = "Bit 7 - RWA, close BLE clock"]
#[inline(always)]
pub fn rb_slp_clk_ble(&mut self) -> RbSlpClkBleW<R8SlpClkOff1Spec> {
RbSlpClkBleW::new(self, 7)
}
}
#[doc = "RWA, sleep clock off control byte 1, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SlpClkOff1Spec;
impl crate::RegisterSpec for R8SlpClkOff1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_slp_clk_off1::R`](R) reader structure"]
impl crate::Readable for R8SlpClkOff1Spec {}
#[doc = "`write(|w| ..)` method takes [`r8_slp_clk_off1::W`](W) writer structure"]
impl crate::Writable for R8SlpClkOff1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SLP_CLK_OFF1 to value 0"]
impl crate::Resettable for R8SlpClkOff1Spec {}
}
#[doc = "R8_SLP_WAKE_CTRL (rw) register accessor: RWA, wake control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_wake_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_wake_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_slp_wake_ctrl`] module"]
#[doc(alias = "R8_SLP_WAKE_CTRL")]
pub type R8SlpWakeCtrl = crate::Reg<r8_slp_wake_ctrl::R8SlpWakeCtrlSpec>;
#[doc = "RWA, wake control, SAM"]
pub mod r8_slp_wake_ctrl {
#[doc = "Register `R8_SLP_WAKE_CTRL` reader"]
pub type R = crate::R<R8SlpWakeCtrlSpec>;
#[doc = "Register `R8_SLP_WAKE_CTRL` writer"]
pub type W = crate::W<R8SlpWakeCtrlSpec>;
#[doc = "Field `RB_SLP_USB_WAKE` reader - RWA, enable USB waking"]
pub type RbSlpUsbWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_USB_WAKE` writer - RWA, enable USB waking"]
pub type RbSlpUsbWakeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_ENC_WAKE` reader - RWA, enable ENC waking"]
pub type RbSlpEncWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_ENC_WAKE` writer - RWA, enable ENC waking"]
pub type RbSlpEncWakeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_GPIO_EDGE_MODE` reader - RWA, GPIO wake-up mode selection"]
pub type RbSlpGpioEdgeModeR = crate::BitReader;
#[doc = "Field `RB_SLP_GPIO_EDGE_MODE` writer - RWA, GPIO wake-up mode selection"]
pub type RbSlpGpioEdgeModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_RTC_WAKE` reader - RWA, enable RTC waking"]
pub type RbSlpRtcWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_RTC_WAKE` writer - RWA, enable RTC waking"]
pub type RbSlpRtcWakeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_GPIO_WAKE` reader - RWA, enable GPIO waking"]
pub type RbSlpGpioWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_GPIO_WAKE` writer - RWA, enable GPIO waking"]
pub type RbSlpGpioWakeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SLP_BAT_WAKE` reader - RWA, enable BAT waking"]
pub type RbSlpBatWakeR = crate::BitReader;
#[doc = "Field `RB_SLP_BAT_WAKE` writer - RWA, enable BAT waking"]
pub type RbSlpBatWakeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_WAKE_EV_MODE` reader - RWA, event wakeup mode"]
pub type RbWakeEvModeR = crate::BitReader;
#[doc = "Field `RB_WAKE_EV_MODE` writer - RWA, event wakeup mode"]
pub type RbWakeEvModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_GPIO_WAKE_MODE` reader - RWA, enable edge GPIO wake-up mode"]
pub type RbGpioWakeModeR = crate::BitReader;
#[doc = "Field `RB_GPIO_WAKE_MODE` writer - RWA, enable edge GPIO wake-up mode"]
pub type RbGpioWakeModeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, enable USB waking"]
#[inline(always)]
pub fn rb_slp_usb_wake(&self) -> RbSlpUsbWakeR {
RbSlpUsbWakeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, enable ENC waking"]
#[inline(always)]
pub fn rb_slp_enc_wake(&self) -> RbSlpEncWakeR {
RbSlpEncWakeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RWA, GPIO wake-up mode selection"]
#[inline(always)]
pub fn rb_slp_gpio_edge_mode(&self) -> RbSlpGpioEdgeModeR {
RbSlpGpioEdgeModeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RWA, enable RTC waking"]
#[inline(always)]
pub fn rb_slp_rtc_wake(&self) -> RbSlpRtcWakeR {
RbSlpRtcWakeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RWA, enable GPIO waking"]
#[inline(always)]
pub fn rb_slp_gpio_wake(&self) -> RbSlpGpioWakeR {
RbSlpGpioWakeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RWA, enable BAT waking"]
#[inline(always)]
pub fn rb_slp_bat_wake(&self) -> RbSlpBatWakeR {
RbSlpBatWakeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RWA, event wakeup mode"]
#[inline(always)]
pub fn rb_wake_ev_mode(&self) -> RbWakeEvModeR {
RbWakeEvModeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RWA, enable edge GPIO wake-up mode"]
#[inline(always)]
pub fn rb_gpio_wake_mode(&self) -> RbGpioWakeModeR {
RbGpioWakeModeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, enable USB waking"]
#[inline(always)]
pub fn rb_slp_usb_wake(&mut self) -> RbSlpUsbWakeW<R8SlpWakeCtrlSpec> {
RbSlpUsbWakeW::new(self, 0)
}
#[doc = "Bit 1 - RWA, enable ENC waking"]
#[inline(always)]
pub fn rb_slp_enc_wake(&mut self) -> RbSlpEncWakeW<R8SlpWakeCtrlSpec> {
RbSlpEncWakeW::new(self, 1)
}
#[doc = "Bit 2 - RWA, GPIO wake-up mode selection"]
#[inline(always)]
pub fn rb_slp_gpio_edge_mode(&mut self) -> RbSlpGpioEdgeModeW<R8SlpWakeCtrlSpec> {
RbSlpGpioEdgeModeW::new(self, 2)
}
#[doc = "Bit 3 - RWA, enable RTC waking"]
#[inline(always)]
pub fn rb_slp_rtc_wake(&mut self) -> RbSlpRtcWakeW<R8SlpWakeCtrlSpec> {
RbSlpRtcWakeW::new(self, 3)
}
#[doc = "Bit 4 - RWA, enable GPIO waking"]
#[inline(always)]
pub fn rb_slp_gpio_wake(&mut self) -> RbSlpGpioWakeW<R8SlpWakeCtrlSpec> {
RbSlpGpioWakeW::new(self, 4)
}
#[doc = "Bit 5 - RWA, enable BAT waking"]
#[inline(always)]
pub fn rb_slp_bat_wake(&mut self) -> RbSlpBatWakeW<R8SlpWakeCtrlSpec> {
RbSlpBatWakeW::new(self, 5)
}
#[doc = "Bit 6 - RWA, event wakeup mode"]
#[inline(always)]
pub fn rb_wake_ev_mode(&mut self) -> RbWakeEvModeW<R8SlpWakeCtrlSpec> {
RbWakeEvModeW::new(self, 6)
}
#[doc = "Bit 7 - RWA, enable edge GPIO wake-up mode"]
#[inline(always)]
pub fn rb_gpio_wake_mode(&mut self) -> RbGpioWakeModeW<R8SlpWakeCtrlSpec> {
RbGpioWakeModeW::new(self, 7)
}
}
#[doc = "RWA, wake control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_wake_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_wake_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SlpWakeCtrlSpec;
impl crate::RegisterSpec for R8SlpWakeCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_slp_wake_ctrl::R`](R) reader structure"]
impl crate::Readable for R8SlpWakeCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_slp_wake_ctrl::W`](W) writer structure"]
impl crate::Writable for R8SlpWakeCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SLP_WAKE_CTRL to value 0x20"]
impl crate::Resettable for R8SlpWakeCtrlSpec {
const RESET_VALUE: u8 = 0x20;
}
}
#[doc = "R8_SLP_POWER_CTRL (rw) register accessor: RWA, peripherals power down control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_slp_power_ctrl`] module"]
#[doc(alias = "R8_SLP_POWER_CTRL")]
pub type R8SlpPowerCtrl = crate::Reg<r8_slp_power_ctrl::R8SlpPowerCtrlSpec>;
#[doc = "RWA, peripherals power down control, SAM"]
pub mod r8_slp_power_ctrl {
#[doc = "Register `R8_SLP_POWER_CTRL` reader"]
pub type R = crate::R<R8SlpPowerCtrlSpec>;
#[doc = "Register `R8_SLP_POWER_CTRL` writer"]
pub type W = crate::W<R8SlpPowerCtrlSpec>;
#[doc = "Field `RB_WAKE_DLY_MOD` reader - RWA, wakeup delay time selection"]
pub type RbWakeDlyModR = crate::FieldReader;
#[doc = "Field `RB_WAKE_DLY_MOD` writer - RWA, wakeup delay time selection"]
pub type RbWakeDlyModW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_SLP_CLK_RAMX` reader - RWA, close main SRAM clock"]
pub type RbSlpClkRamxR = crate::BitReader;
#[doc = "Field `RB_SLP_CLK_RAMX` writer - RWA, close main SRAM clock"]
pub type RbSlpClkRamxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RAM_RET_LV` reader - RWA, SRAM retention voltage selection"]
pub type RbRamRetLvR = crate::FieldReader;
#[doc = "Field `RB_RAM_RET_LV` writer - RWA, SRAM retention voltage selection"]
pub type RbRamRetLvW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:2 - RWA, wakeup delay time selection"]
#[inline(always)]
pub fn rb_wake_dly_mod(&self) -> RbWakeDlyModR {
RbWakeDlyModR::new(self.bits & 7)
}
#[doc = "Bit 4 - RWA, close main SRAM clock"]
#[inline(always)]
pub fn rb_slp_clk_ramx(&self) -> RbSlpClkRamxR {
RbSlpClkRamxR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 6:7 - RWA, SRAM retention voltage selection"]
#[inline(always)]
pub fn rb_ram_ret_lv(&self) -> RbRamRetLvR {
RbRamRetLvR::new((self.bits >> 6) & 3)
}
}
impl W {
#[doc = "Bits 0:2 - RWA, wakeup delay time selection"]
#[inline(always)]
pub fn rb_wake_dly_mod(&mut self) -> RbWakeDlyModW<R8SlpPowerCtrlSpec> {
RbWakeDlyModW::new(self, 0)
}
#[doc = "Bit 4 - RWA, close main SRAM clock"]
#[inline(always)]
pub fn rb_slp_clk_ramx(&mut self) -> RbSlpClkRamxW<R8SlpPowerCtrlSpec> {
RbSlpClkRamxW::new(self, 4)
}
#[doc = "Bits 6:7 - RWA, SRAM retention voltage selection"]
#[inline(always)]
pub fn rb_ram_ret_lv(&mut self) -> RbRamRetLvW<R8SlpPowerCtrlSpec> {
RbRamRetLvW::new(self, 6)
}
}
#[doc = "RWA, peripherals power down control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_power_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_power_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SlpPowerCtrlSpec;
impl crate::RegisterSpec for R8SlpPowerCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_slp_power_ctrl::R`](R) reader structure"]
impl crate::Readable for R8SlpPowerCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_slp_power_ctrl::W`](W) writer structure"]
impl crate::Writable for R8SlpPowerCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SLP_POWER_CTRL to value 0"]
impl crate::Resettable for R8SlpPowerCtrlSpec {}
}
#[doc = "R16_PIN_ALTERNATE (rw) register accessor: RW, function pin alternate configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pin_alternate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pin_alternate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pin_alternate`] module"]
#[doc(alias = "R16_PIN_ALTERNATE")]
pub type R16PinAlternate = crate::Reg<r16_pin_alternate::R16PinAlternateSpec>;
#[doc = "RW, function pin alternate configuration"]
pub mod r16_pin_alternate {
#[doc = "Register `R16_PIN_ALTERNATE` reader"]
pub type R = crate::R<R16PinAlternateSpec>;
#[doc = "Register `R16_PIN_ALTERNATE` writer"]
pub type W = crate::W<R16PinAlternateSpec>;
#[doc = "Field `RB_PA_DI_DIS` reader - RW, PA0-PA11 channel pin digital input enable"]
pub type RbPaDiDisR = crate::FieldReader<u16>;
#[doc = "Field `RB_PA_DI_DIS` writer - RW, PA0-PA11 channel pin digital input enable"]
pub type RbPaDiDisW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RB_UDP_PU_EN` reader - RW, Enable internal pull-up resistor for UDP pin of full speed USB"]
pub type RbUdpPuEnR = crate::BitReader;
#[doc = "Field `RB_UDP_PU_EN` writer - RW, Enable internal pull-up resistor for UDP pin of full speed USB"]
pub type RbUdpPuEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PIN_USB_EN` reader - RW, Full speed USB pin enable"]
pub type RbPinUsbEnR = crate::BitReader;
#[doc = "Field `RB_PIN_USB_EN` writer - RW, Full speed USB pin enable"]
pub type RbPinUsbEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PIN_DEBUG_EN` reader - RW, Debugging interface control bit"]
pub type RbPinDebugEnR = crate::BitReader;
#[doc = "Field `RB_PIN_DEBUG_EN` writer - RW, Debugging interface control bit"]
pub type RbPinDebugEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:11 - RW, PA0-PA11 channel pin digital input enable"]
#[inline(always)]
pub fn rb_pa_di_dis(&self) -> RbPaDiDisR {
RbPaDiDisR::new(self.bits & 0x0fff)
}
#[doc = "Bit 12 - RW, Enable internal pull-up resistor for UDP pin of full speed USB"]
#[inline(always)]
pub fn rb_udp_pu_en(&self) -> RbUdpPuEnR {
RbUdpPuEnR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - RW, Full speed USB pin enable"]
#[inline(always)]
pub fn rb_pin_usb_en(&self) -> RbPinUsbEnR {
RbPinUsbEnR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - RW, Debugging interface control bit"]
#[inline(always)]
pub fn rb_pin_debug_en(&self) -> RbPinDebugEnR {
RbPinDebugEnR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:11 - RW, PA0-PA11 channel pin digital input enable"]
#[inline(always)]
pub fn rb_pa_di_dis(&mut self) -> RbPaDiDisW<R16PinAlternateSpec> {
RbPaDiDisW::new(self, 0)
}
#[doc = "Bit 12 - RW, Enable internal pull-up resistor for UDP pin of full speed USB"]
#[inline(always)]
pub fn rb_udp_pu_en(&mut self) -> RbUdpPuEnW<R16PinAlternateSpec> {
RbUdpPuEnW::new(self, 12)
}
#[doc = "Bit 13 - RW, Full speed USB pin enable"]
#[inline(always)]
pub fn rb_pin_usb_en(&mut self) -> RbPinUsbEnW<R16PinAlternateSpec> {
RbPinUsbEnW::new(self, 13)
}
#[doc = "Bit 14 - RW, Debugging interface control bit"]
#[inline(always)]
pub fn rb_pin_debug_en(&mut self) -> RbPinDebugEnW<R16PinAlternateSpec> {
RbPinDebugEnW::new(self, 14)
}
}
#[doc = "RW, function pin alternate configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pin_alternate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pin_alternate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PinAlternateSpec;
impl crate::RegisterSpec for R16PinAlternateSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pin_alternate::R`](R) reader structure"]
impl crate::Readable for R16PinAlternateSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pin_alternate::W`](W) writer structure"]
impl crate::Writable for R16PinAlternateSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PIN_ALTERNATE to value 0x4000"]
impl crate::Resettable for R16PinAlternateSpec {
const RESET_VALUE: u16 = 0x4000;
}
}
#[doc = "R16_PIN_ALTERNATE_H (rw) register accessor: RW, function pin high alternate configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pin_alternate_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pin_alternate_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pin_alternate_h`] module"]
#[doc(alias = "R16_PIN_ALTERNATE_H")]
pub type R16PinAlternateH = crate::Reg<r16_pin_alternate_h::R16PinAlternateHSpec>;
#[doc = "RW, function pin high alternate configuration"]
pub mod r16_pin_alternate_h {
#[doc = "Register `R16_PIN_ALTERNATE_H` reader"]
pub type R = crate::R<R16PinAlternateHSpec>;
#[doc = "Register `R16_PIN_ALTERNATE_H` writer"]
pub type W = crate::W<R16PinAlternateHSpec>;
#[doc = "Field `RB_UART_RXD` reader - RW, RXD alternate pin enable"]
pub type RbUartRxdR = crate::FieldReader;
#[doc = "Field `RB_UART_RXD` writer - RW, RXD alternate pin enable"]
pub type RbUartRxdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_UART_TXD` reader - RW, TXD alternate pin enable"]
pub type RbUartTxdR = crate::FieldReader;
#[doc = "Field `RB_UART_TXD` writer - RW, TXD alternate pin enable"]
pub type RbUartTxdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_TMR_PIN` reader - RW, Timer function pin mapping selection bit"]
pub type RbTmrPinR = crate::FieldReader;
#[doc = "Field `RB_TMR_PIN` writer - RW, Timer function pin mapping selection bit"]
pub type RbTmrPinW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_SPI_CS` reader - RW, SPI CS function pin mapping selection bit"]
pub type RbSpiCsR = crate::BitReader;
#[doc = "Field `RB_SPI_CS` writer - RW, SPI CS function pin mapping selection bit"]
pub type RbSpiCsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_PIN` reader - RW, I2C function pin mapping selection bit"]
pub type RbI2cPinR = crate::FieldReader;
#[doc = "Field `RB_I2C_PIN` writer - RW, I2C function pin mapping selection bit"]
pub type RbI2cPinW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_SPI_CLK` reader - RW, SPI CLK function pin mapping selection bit"]
pub type RbSpiClkR = crate::BitReader;
#[doc = "Field `RB_SPI_CLK` writer - RW, SPI CLK function pin mapping selection bit"]
pub type RbSpiClkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_25M_EN` reader - RW, Enable 25MHz clock output"]
pub type Rb25mEnR = crate::BitReader;
#[doc = "Field `RB_25M_EN` writer - RW, Enable 25MHz clock output"]
pub type Rb25mEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - RW, RXD alternate pin enable"]
#[inline(always)]
pub fn rb_uart_rxd(&self) -> RbUartRxdR {
RbUartRxdR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - RW, TXD alternate pin enable"]
#[inline(always)]
pub fn rb_uart_txd(&self) -> RbUartTxdR {
RbUartTxdR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7 - RW, Timer function pin mapping selection bit"]
#[inline(always)]
pub fn rb_tmr_pin(&self) -> RbTmrPinR {
RbTmrPinR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - RW, SPI CS function pin mapping selection bit"]
#[inline(always)]
pub fn rb_spi_cs(&self) -> RbSpiCsR {
RbSpiCsR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - RW, I2C function pin mapping selection bit"]
#[inline(always)]
pub fn rb_i2c_pin(&self) -> RbI2cPinR {
RbI2cPinR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - RW, SPI CLK function pin mapping selection bit"]
#[inline(always)]
pub fn rb_spi_clk(&self) -> RbSpiClkR {
RbSpiClkR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - RW, Enable 25MHz clock output"]
#[inline(always)]
pub fn rb_25m_en(&self) -> Rb25mEnR {
Rb25mEnR::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - RW, RXD alternate pin enable"]
#[inline(always)]
pub fn rb_uart_rxd(&mut self) -> RbUartRxdW<R16PinAlternateHSpec> {
RbUartRxdW::new(self, 0)
}
#[doc = "Bits 3:5 - RW, TXD alternate pin enable"]
#[inline(always)]
pub fn rb_uart_txd(&mut self) -> RbUartTxdW<R16PinAlternateHSpec> {
RbUartTxdW::new(self, 3)
}
#[doc = "Bits 6:7 - RW, Timer function pin mapping selection bit"]
#[inline(always)]
pub fn rb_tmr_pin(&mut self) -> RbTmrPinW<R16PinAlternateHSpec> {
RbTmrPinW::new(self, 6)
}
#[doc = "Bit 8 - RW, SPI CS function pin mapping selection bit"]
#[inline(always)]
pub fn rb_spi_cs(&mut self) -> RbSpiCsW<R16PinAlternateHSpec> {
RbSpiCsW::new(self, 8)
}
#[doc = "Bits 9:10 - RW, I2C function pin mapping selection bit"]
#[inline(always)]
pub fn rb_i2c_pin(&mut self) -> RbI2cPinW<R16PinAlternateHSpec> {
RbI2cPinW::new(self, 9)
}
#[doc = "Bit 11 - RW, SPI CLK function pin mapping selection bit"]
#[inline(always)]
pub fn rb_spi_clk(&mut self) -> RbSpiClkW<R16PinAlternateHSpec> {
RbSpiClkW::new(self, 11)
}
#[doc = "Bit 12 - RW, Enable 25MHz clock output"]
#[inline(always)]
pub fn rb_25m_en(&mut self) -> Rb25mEnW<R16PinAlternateHSpec> {
Rb25mEnW::new(self, 12)
}
}
#[doc = "RW, function pin high alternate configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pin_alternate_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pin_alternate_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PinAlternateHSpec;
impl crate::RegisterSpec for R16PinAlternateHSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pin_alternate_h::R`](R) reader structure"]
impl crate::Readable for R16PinAlternateHSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pin_alternate_h::W`](W) writer structure"]
impl crate::Writable for R16PinAlternateHSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PIN_ALTERNATE_H to value 0"]
impl crate::Resettable for R16PinAlternateHSpec {}
}
#[doc = "R8_LONG_RST_CFG (rw) register accessor: RWA, Long reset configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_long_rst_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_long_rst_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_long_rst_cfg`] module"]
#[doc(alias = "R8_LONG_RST_CFG")]
pub type R8LongRstCfg = crate::Reg<r8_long_rst_cfg::R8LongRstCfgSpec>;
#[doc = "RWA, Long reset configuration register"]
pub mod r8_long_rst_cfg {
#[doc = "Register `R8_LONG_RST_CFG` reader"]
pub type R = crate::R<R8LongRstCfgSpec>;
#[doc = "Register `R8_LONG_RST_CFG` writer"]
pub type W = crate::W<R8LongRstCfgSpec>;
#[doc = "Field `RB_LONG_RST_EN` reader - RWA, Long reset enable"]
pub type RbLongRstEnR = crate::BitReader;
#[doc = "Field `RB_LONG_RST_EN` writer - RWA, Long reset enable"]
pub type RbLongRstEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_LONG_TIM_SEL` reader - RWA, Long reset duration selection"]
pub type RbLongTimSelR = crate::FieldReader;
#[doc = "Field `RB_LONG_TIM_SEL` writer - RWA, Long reset duration selection"]
pub type RbLongTimSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bit 0 - RWA, Long reset enable"]
#[inline(always)]
pub fn rb_long_rst_en(&self) -> RbLongRstEnR {
RbLongRstEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - RWA, Long reset duration selection"]
#[inline(always)]
pub fn rb_long_tim_sel(&self) -> RbLongTimSelR {
RbLongTimSelR::new((self.bits >> 1) & 3)
}
}
impl W {
#[doc = "Bit 0 - RWA, Long reset enable"]
#[inline(always)]
pub fn rb_long_rst_en(&mut self) -> RbLongRstEnW<R8LongRstCfgSpec> {
RbLongRstEnW::new(self, 0)
}
#[doc = "Bits 1:2 - RWA, Long reset duration selection"]
#[inline(always)]
pub fn rb_long_tim_sel(&mut self) -> RbLongTimSelW<R8LongRstCfgSpec> {
RbLongTimSelW::new(self, 1)
}
}
#[doc = "RWA, Long reset configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_long_rst_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_long_rst_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8LongRstCfgSpec;
impl crate::RegisterSpec for R8LongRstCfgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_long_rst_cfg::R`](R) reader structure"]
impl crate::Readable for R8LongRstCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_long_rst_cfg::W`](W) writer structure"]
impl crate::Writable for R8LongRstCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_LONG_RST_CFG to value 0"]
impl crate::Resettable for R8LongRstCfgSpec {}
}
#[doc = "R8_SLP_CLK_OFF2 (rw) register accessor: RWA, Sleep clock control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_slp_clk_off2`] module"]
#[doc(alias = "R8_SLP_CLK_OFF2")]
pub type R8SlpClkOff2 = crate::Reg<r8_slp_clk_off2::R8SlpClkOff2Spec>;
#[doc = "RWA, Sleep clock control register 2"]
pub mod r8_slp_clk_off2 {
#[doc = "Register `R8_SLP_CLK_OFF2` reader"]
pub type R = crate::R<R8SlpClkOff2Spec>;
#[doc = "Register `R8_SLP_CLK_OFF2` writer"]
pub type W = crate::W<R8SlpClkOff2Spec>;
#[doc = "Field `RB_CLK_OFF_XROM` reader - RWA, Turn off the 64M or 600M clock of the FLASH controller"]
pub type RbClkOffXromR = crate::BitReader;
#[doc = "Field `RB_CLK_OFF_XROM` writer - RWA, Turn off the 64M or 600M clock of the FLASH controller"]
pub type RbClkOffXromW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLK_OFF_DEBUG` reader - RWA, Close the two-wire debugging 32M clock"]
pub type RbClkOffDebugR = crate::BitReader;
#[doc = "Field `RB_CLK_OFF_DEBUG` writer - RWA, Close the two-wire debugging 32M clock"]
pub type RbClkOffDebugW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLK_OFF_HCLK` reader - RWA, Turn off the HCLK clock of the FLASH controller"]
pub type RbClkOffHclkR = crate::BitReader;
#[doc = "Field `RB_CLK_OFF_HCLK` writer - RWA, Turn off the HCLK clock of the FLASH controller"]
pub type RbClkOffHclkW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, Turn off the 64M or 600M clock of the FLASH controller"]
#[inline(always)]
pub fn rb_clk_off_xrom(&self) -> RbClkOffXromR {
RbClkOffXromR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, Close the two-wire debugging 32M clock"]
#[inline(always)]
pub fn rb_clk_off_debug(&self) -> RbClkOffDebugR {
RbClkOffDebugR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - RWA, Turn off the HCLK clock of the FLASH controller"]
#[inline(always)]
pub fn rb_clk_off_hclk(&self) -> RbClkOffHclkR {
RbClkOffHclkR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, Turn off the 64M or 600M clock of the FLASH controller"]
#[inline(always)]
pub fn rb_clk_off_xrom(&mut self) -> RbClkOffXromW<R8SlpClkOff2Spec> {
RbClkOffXromW::new(self, 0)
}
#[doc = "Bit 1 - RWA, Close the two-wire debugging 32M clock"]
#[inline(always)]
pub fn rb_clk_off_debug(&mut self) -> RbClkOffDebugW<R8SlpClkOff2Spec> {
RbClkOffDebugW::new(self, 1)
}
#[doc = "Bit 4 - RWA, Turn off the HCLK clock of the FLASH controller"]
#[inline(always)]
pub fn rb_clk_off_hclk(&mut self) -> RbClkOffHclkW<R8SlpClkOff2Spec> {
RbClkOffHclkW::new(self, 4)
}
}
#[doc = "RWA, Sleep clock control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_slp_clk_off2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_slp_clk_off2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SlpClkOff2Spec;
impl crate::RegisterSpec for R8SlpClkOff2Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_slp_clk_off2::R`](R) reader structure"]
impl crate::Readable for R8SlpClkOff2Spec {}
#[doc = "`write(|w| ..)` method takes [`r8_slp_clk_off2::W`](W) writer structure"]
impl crate::Writable for R8SlpClkOff2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SLP_CLK_OFF2 to value 0"]
impl crate::Resettable for R8SlpClkOff2Spec {}
}
#[doc = "R16_SLP_WAKE_CFG (rw) register accessor: RWA, Sleep clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_slp_wake_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_slp_wake_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_slp_wake_cfg`] module"]
#[doc(alias = "R16_SLP_WAKE_CFG")]
pub type R16SlpWakeCfg = crate::Reg<r16_slp_wake_cfg::R16SlpWakeCfgSpec>;
#[doc = "RWA, Sleep clock control register"]
pub mod r16_slp_wake_cfg {
#[doc = "Register `R16_SLP_WAKE_CFG` reader"]
pub type R = crate::R<R16SlpWakeCfgSpec>;
#[doc = "Register `R16_SLP_WAKE_CFG` writer"]
pub type W = crate::W<R16SlpWakeCfgSpec>;
#[doc = "Field `RB_OSCCLK_RDY_KEEP` reader - RWA, During Halt sleep, the peripheral clock remains on"]
pub type RbOscclkRdyKeepR = crate::BitReader;
#[doc = "Field `RB_OSCCLK_RDY_KEEP` writer - RWA, During Halt sleep, the peripheral clock remains on"]
pub type RbOscclkRdyKeepW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PRECLK_CNT_EN` reader - RWA, When waking up from sleep, it takes a certain amount of time to release HCLK"]
pub type RbPreclkCntEnR = crate::BitReader;
#[doc = "Field `RB_PRECLK_CNT_EN` writer - RWA, When waking up from sleep, it takes a certain amount of time to release HCLK"]
pub type RbPreclkCntEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PRECLK_CNT_SEL` reader - RWA, Sleep time configuration, sleep duration=number of cycles * Fsys"]
pub type RbPreclkCntSelR = crate::FieldReader;
#[doc = "Field `RB_PRECLK_CNT_SEL` writer - RWA, Sleep time configuration, sleep duration=number of cycles * Fsys"]
pub type RbPreclkCntSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_ACAUTO_ENABLE` reader - RWA, The secure register channel automatically closes"]
pub type RbAcautoEnableR = crate::BitReader;
#[doc = "Field `RB_ACAUTO_ENABLE` writer - RWA, The secure register channel automatically closes"]
pub type RbAcautoEnableW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, During Halt sleep, the peripheral clock remains on"]
#[inline(always)]
pub fn rb_oscclk_rdy_keep(&self) -> RbOscclkRdyKeepR {
RbOscclkRdyKeepR::new((self.bits & 1) != 0)
}
#[doc = "Bit 4 - RWA, When waking up from sleep, it takes a certain amount of time to release HCLK"]
#[inline(always)]
pub fn rb_preclk_cnt_en(&self) -> RbPreclkCntEnR {
RbPreclkCntEnR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - RWA, Sleep time configuration, sleep duration=number of cycles * Fsys"]
#[inline(always)]
pub fn rb_preclk_cnt_sel(&self) -> RbPreclkCntSelR {
RbPreclkCntSelR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 8 - RWA, The secure register channel automatically closes"]
#[inline(always)]
pub fn rb_acauto_enable(&self) -> RbAcautoEnableR {
RbAcautoEnableR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, During Halt sleep, the peripheral clock remains on"]
#[inline(always)]
pub fn rb_oscclk_rdy_keep(&mut self) -> RbOscclkRdyKeepW<R16SlpWakeCfgSpec> {
RbOscclkRdyKeepW::new(self, 0)
}
#[doc = "Bit 4 - RWA, When waking up from sleep, it takes a certain amount of time to release HCLK"]
#[inline(always)]
pub fn rb_preclk_cnt_en(&mut self) -> RbPreclkCntEnW<R16SlpWakeCfgSpec> {
RbPreclkCntEnW::new(self, 4)
}
#[doc = "Bits 5:6 - RWA, Sleep time configuration, sleep duration=number of cycles * Fsys"]
#[inline(always)]
pub fn rb_preclk_cnt_sel(&mut self) -> RbPreclkCntSelW<R16SlpWakeCfgSpec> {
RbPreclkCntSelW::new(self, 5)
}
#[doc = "Bit 8 - RWA, The secure register channel automatically closes"]
#[inline(always)]
pub fn rb_acauto_enable(&mut self) -> RbAcautoEnableW<R16SlpWakeCfgSpec> {
RbAcautoEnableW::new(self, 8)
}
}
#[doc = "RWA, Sleep clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_slp_wake_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_slp_wake_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16SlpWakeCfgSpec;
impl crate::RegisterSpec for R16SlpWakeCfgSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_slp_wake_cfg::R`](R) reader structure"]
impl crate::Readable for R16SlpWakeCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_slp_wake_cfg::W`](W) writer structure"]
impl crate::Writable for R16SlpWakeCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_SLP_WAKE_CFG to value 0x0100"]
impl crate::Resettable for R16SlpWakeCfgSpec {
const RESET_VALUE: u16 = 0x0100;
}
}
#[doc = "R16_POWER_PLAN (rw) register accessor: RWA, power plan before sleep instruction, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_power_plan::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_power_plan::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_power_plan`] module"]
#[doc(alias = "R16_POWER_PLAN")]
pub type R16PowerPlan = crate::Reg<r16_power_plan::R16PowerPlanSpec>;
#[doc = "RWA, power plan before sleep instruction, SAM"]
pub mod r16_power_plan {
#[doc = "Register `R16_POWER_PLAN` reader"]
pub type R = crate::R<R16PowerPlanSpec>;
#[doc = "Register `R16_POWER_PLAN` writer"]
pub type W = crate::W<R16PowerPlanSpec>;
#[doc = "Field `RB_PWR_XROM` reader - RWA, power for FlashROM"]
pub type RbPwrXromR = crate::BitReader;
#[doc = "Field `RB_PWR_XROM` writer - RWA, power for FlashROM"]
pub type RbPwrXromW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_RAM12K` reader - RWA, SRAM power supply for RAM12K"]
pub type RbPwrRam12kR = crate::BitReader;
#[doc = "Field `RB_PWR_RAM12K` writer - RWA, SRAM power supply for RAM12K"]
pub type RbPwrRam12kW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_CORE` reader - RWA, power retention for core and base peripherals"]
pub type RbPwrCoreR = crate::BitReader;
#[doc = "Field `RB_PWR_CORE` writer - RWA, power retention for core and base peripherals"]
pub type RbPwrCoreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_EXTEND` reader - RWA, power retention for USB and BLE"]
pub type RbPwrExtendR = crate::BitReader;
#[doc = "Field `RB_PWR_EXTEND` writer - RWA, power retention for USB and BLE"]
pub type RbPwrExtendW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_MAIN_ACT` reader - RWA, Main power selection"]
pub type RbMainActR = crate::BitReader;
#[doc = "Field `RB_MAIN_ACT` writer - RWA, Main power selection"]
pub type RbMainActW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_SYS_EN` reader - RWA, power for system"]
pub type RbPwrSysEnR = crate::BitReader;
#[doc = "Field `RB_PWR_SYS_EN` writer - RWA, power for system"]
pub type RbPwrSysEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_LDO5V_EN` reader - RWA, Internal LDO5V control"]
pub type RbPwrLdo5vEnR = crate::BitReader;
#[doc = "Field `RB_PWR_LDO5V_EN` writer - RWA, Internal LDO5V control"]
pub type RbPwrLdo5vEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWR_PLAN_EN` reader - RWA, Enable sleep power planning and control"]
pub type RbPwrPlanEnR = crate::BitReader;
#[doc = "Field `RB_PWR_PLAN_EN` writer - RWA, Enable sleep power planning and control"]
pub type RbPwrPlanEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, power for FlashROM"]
#[inline(always)]
pub fn rb_pwr_xrom(&self) -> RbPwrXromR {
RbPwrXromR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, SRAM power supply for RAM12K"]
#[inline(always)]
pub fn rb_pwr_ram12k(&self) -> RbPwrRam12kR {
RbPwrRam12kR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RWA, power retention for core and base peripherals"]
#[inline(always)]
pub fn rb_pwr_core(&self) -> RbPwrCoreR {
RbPwrCoreR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RWA, power retention for USB and BLE"]
#[inline(always)]
pub fn rb_pwr_extend(&self) -> RbPwrExtendR {
RbPwrExtendR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 6 - RWA, Main power selection"]
#[inline(always)]
pub fn rb_main_act(&self) -> RbMainActR {
RbMainActR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RWA, power for system"]
#[inline(always)]
pub fn rb_pwr_sys_en(&self) -> RbPwrSysEnR {
RbPwrSysEnR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - RWA, Internal LDO5V control"]
#[inline(always)]
pub fn rb_pwr_ldo5v_en(&self) -> RbPwrLdo5vEnR {
RbPwrLdo5vEnR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 15 - RWA, Enable sleep power planning and control"]
#[inline(always)]
pub fn rb_pwr_plan_en(&self) -> RbPwrPlanEnR {
RbPwrPlanEnR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, power for FlashROM"]
#[inline(always)]
pub fn rb_pwr_xrom(&mut self) -> RbPwrXromW<R16PowerPlanSpec> {
RbPwrXromW::new(self, 0)
}
#[doc = "Bit 1 - RWA, SRAM power supply for RAM12K"]
#[inline(always)]
pub fn rb_pwr_ram12k(&mut self) -> RbPwrRam12kW<R16PowerPlanSpec> {
RbPwrRam12kW::new(self, 1)
}
#[doc = "Bit 2 - RWA, power retention for core and base peripherals"]
#[inline(always)]
pub fn rb_pwr_core(&mut self) -> RbPwrCoreW<R16PowerPlanSpec> {
RbPwrCoreW::new(self, 2)
}
#[doc = "Bit 3 - RWA, power retention for USB and BLE"]
#[inline(always)]
pub fn rb_pwr_extend(&mut self) -> RbPwrExtendW<R16PowerPlanSpec> {
RbPwrExtendW::new(self, 3)
}
#[doc = "Bit 6 - RWA, Main power selection"]
#[inline(always)]
pub fn rb_main_act(&mut self) -> RbMainActW<R16PowerPlanSpec> {
RbMainActW::new(self, 6)
}
#[doc = "Bit 7 - RWA, power for system"]
#[inline(always)]
pub fn rb_pwr_sys_en(&mut self) -> RbPwrSysEnW<R16PowerPlanSpec> {
RbPwrSysEnW::new(self, 7)
}
#[doc = "Bit 8 - RWA, Internal LDO5V control"]
#[inline(always)]
pub fn rb_pwr_ldo5v_en(&mut self) -> RbPwrLdo5vEnW<R16PowerPlanSpec> {
RbPwrLdo5vEnW::new(self, 8)
}
#[doc = "Bit 15 - RWA, Enable sleep power planning and control"]
#[inline(always)]
pub fn rb_pwr_plan_en(&mut self) -> RbPwrPlanEnW<R16PowerPlanSpec> {
RbPwrPlanEnW::new(self, 15)
}
}
#[doc = "RWA, power plan before sleep instruction, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_power_plan::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_power_plan::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PowerPlanSpec;
impl crate::RegisterSpec for R16PowerPlanSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_power_plan::R`](R) reader structure"]
impl crate::Readable for R16PowerPlanSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_power_plan::W`](W) writer structure"]
impl crate::Writable for R16PowerPlanSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_POWER_PLAN to value 0x11cf"]
impl crate::Resettable for R16PowerPlanSpec {
const RESET_VALUE: u16 = 0x11cf;
}
}
#[doc = "R16_AUX_POWER_ADJ (rw) register accessor: RWA, aux power adjust control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_aux_power_adj::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_aux_power_adj::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_aux_power_adj`] module"]
#[doc(alias = "R16_AUX_POWER_ADJ")]
pub type R16AuxPowerAdj = crate::Reg<r16_aux_power_adj::R16AuxPowerAdjSpec>;
#[doc = "RWA, aux power adjust control, SAM"]
pub mod r16_aux_power_adj {
#[doc = "Register `R16_AUX_POWER_ADJ` reader"]
pub type R = crate::R<R16AuxPowerAdjSpec>;
#[doc = "Register `R16_AUX_POWER_ADJ` writer"]
pub type W = crate::W<R16AuxPowerAdjSpec>;
#[doc = "Field `RB_ULPLDO_ADJ` reader - RWA, Output voltage regulation value of auxiliary power supply for ultra-low power consumption LDO"]
pub type RbUlpldoAdjR = crate::FieldReader;
#[doc = "Field `RB_ULPLDO_ADJ` writer - RWA, Output voltage regulation value of auxiliary power supply for ultra-low power consumption LDO"]
pub type RbUlpldoAdjW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_CFG_IVREF` reader - RO, retain. The original value must be kept unchanged when writing"]
pub type RbCfgIvrefR = crate::FieldReader;
#[doc = "Field `RB_CFG_IVREF` writer - RO, retain. The original value must be kept unchanged when writing"]
pub type RbCfgIvrefW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:2 - RWA, Output voltage regulation value of auxiliary power supply for ultra-low power consumption LDO"]
#[inline(always)]
pub fn rb_ulpldo_adj(&self) -> RbUlpldoAdjR {
RbUlpldoAdjR::new((self.bits & 7) as u8)
}
#[doc = "Bits 8:11 - RO, retain. The original value must be kept unchanged when writing"]
#[inline(always)]
pub fn rb_cfg_ivref(&self) -> RbCfgIvrefR {
RbCfgIvrefR::new(((self.bits >> 8) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - RWA, Output voltage regulation value of auxiliary power supply for ultra-low power consumption LDO"]
#[inline(always)]
pub fn rb_ulpldo_adj(&mut self) -> RbUlpldoAdjW<R16AuxPowerAdjSpec> {
RbUlpldoAdjW::new(self, 0)
}
#[doc = "Bits 8:11 - RO, retain. The original value must be kept unchanged when writing"]
#[inline(always)]
pub fn rb_cfg_ivref(&mut self) -> RbCfgIvrefW<R16AuxPowerAdjSpec> {
RbCfgIvrefW::new(self, 8)
}
}
#[doc = "RWA, aux power adjust control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_aux_power_adj::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_aux_power_adj::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16AuxPowerAdjSpec;
impl crate::RegisterSpec for R16AuxPowerAdjSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_aux_power_adj::R`](R) reader structure"]
impl crate::Readable for R16AuxPowerAdjSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_aux_power_adj::W`](W) writer structure"]
impl crate::Writable for R16AuxPowerAdjSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_AUX_POWER_ADJ to value 0"]
impl crate::Resettable for R16AuxPowerAdjSpec {}
}
#[doc = "R8_BAT_DET_CTRL (rw) register accessor: RWA, battery voltage detector control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_det_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_bat_det_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_bat_det_ctrl`] module"]
#[doc(alias = "R8_BAT_DET_CTRL")]
pub type R8BatDetCtrl = crate::Reg<r8_bat_det_ctrl::R8BatDetCtrlSpec>;
#[doc = "RWA, battery voltage detector control, SAM"]
pub mod r8_bat_det_ctrl {
#[doc = "Register `R8_BAT_DET_CTRL` reader"]
pub type R = crate::R<R8BatDetCtrlSpec>;
#[doc = "Register `R8_BAT_DET_CTRL` writer"]
pub type W = crate::W<R8BatDetCtrlSpec>;
#[doc = "Field `RB_PWR_LDO_EN` reader - RWA, -"]
pub type RbPwrLdoEnR = crate::BitReader;
#[doc = "Field `RB_PWR_LDO_EN` writer - RWA, -"]
pub type RbPwrLdoEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_BAT_MON_EN` reader - RWA, Enable low-power battery voltage monitoring function"]
pub type RbBatMonEnR = crate::BitReader;
#[doc = "Field `RB_BAT_MON_EN` writer - RWA, Enable low-power battery voltage monitoring function"]
pub type RbBatMonEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_BAT_LOW_IE` reader - RWA, Battery low voltage interrupt enable"]
pub type RbBatLowIeR = crate::BitReader;
#[doc = "Field `RB_BAT_LOW_IE` writer - RWA, Battery low voltage interrupt enable"]
pub type RbBatLowIeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RWA, -"]
#[inline(always)]
pub fn rb_pwr_ldo_en(&self) -> RbPwrLdoEnR {
RbPwrLdoEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, Enable low-power battery voltage monitoring function"]
#[inline(always)]
pub fn rb_bat_mon_en(&self) -> RbBatMonEnR {
RbBatMonEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - RWA, Battery low voltage interrupt enable"]
#[inline(always)]
pub fn rb_bat_low_ie(&self) -> RbBatLowIeR {
RbBatLowIeR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RWA, -"]
#[inline(always)]
pub fn rb_pwr_ldo_en(&mut self) -> RbPwrLdoEnW<R8BatDetCtrlSpec> {
RbPwrLdoEnW::new(self, 0)
}
#[doc = "Bit 1 - RWA, Enable low-power battery voltage monitoring function"]
#[inline(always)]
pub fn rb_bat_mon_en(&mut self) -> RbBatMonEnW<R8BatDetCtrlSpec> {
RbBatMonEnW::new(self, 1)
}
#[doc = "Bit 3 - RWA, Battery low voltage interrupt enable"]
#[inline(always)]
pub fn rb_bat_low_ie(&mut self) -> RbBatLowIeW<R8BatDetCtrlSpec> {
RbBatLowIeW::new(self, 3)
}
}
#[doc = "RWA, battery voltage detector control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_det_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_bat_det_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8BatDetCtrlSpec;
impl crate::RegisterSpec for R8BatDetCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_bat_det_ctrl::R`](R) reader structure"]
impl crate::Readable for R8BatDetCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_bat_det_ctrl::W`](W) writer structure"]
impl crate::Writable for R8BatDetCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_BAT_DET_CTRL to value 0"]
impl crate::Resettable for R8BatDetCtrlSpec {}
}
#[doc = "R8_BAT_DET_CFG (rw) register accessor: RWA, battery voltage detector configuration, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_det_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_bat_det_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_bat_det_cfg`] module"]
#[doc(alias = "R8_BAT_DET_CFG")]
pub type R8BatDetCfg = crate::Reg<r8_bat_det_cfg::R8BatDetCfgSpec>;
#[doc = "RWA, battery voltage detector configuration, SAM"]
pub mod r8_bat_det_cfg {
#[doc = "Register `R8_BAT_DET_CFG` reader"]
pub type R = crate::R<R8BatDetCfgSpec>;
#[doc = "Register `R8_BAT_DET_CFG` writer"]
pub type W = crate::W<R8BatDetCfgSpec>;
#[doc = "Field `RB_BAT_LOW_VTH` reader - RWA, select threshold voltage of battery voltage low"]
pub type RbBatLowVthR = crate::FieldReader;
#[doc = "Field `RB_BAT_LOW_VTH` writer - RWA, select threshold voltage of battery voltage low"]
pub type RbBatLowVthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:1 - RWA, select threshold voltage of battery voltage low"]
#[inline(always)]
pub fn rb_bat_low_vth(&self) -> RbBatLowVthR {
RbBatLowVthR::new(self.bits & 3)
}
}
impl W {
#[doc = "Bits 0:1 - RWA, select threshold voltage of battery voltage low"]
#[inline(always)]
pub fn rb_bat_low_vth(&mut self) -> RbBatLowVthW<R8BatDetCfgSpec> {
RbBatLowVthW::new(self, 0)
}
}
#[doc = "RWA, battery voltage detector configuration, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_det_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_bat_det_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8BatDetCfgSpec;
impl crate::RegisterSpec for R8BatDetCfgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_bat_det_cfg::R`](R) reader structure"]
impl crate::Readable for R8BatDetCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_bat_det_cfg::W`](W) writer structure"]
impl crate::Writable for R8BatDetCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_BAT_DET_CFG to value 0x02"]
impl crate::Resettable for R8BatDetCfgSpec {
const RESET_VALUE: u8 = 0x02;
}
}
#[doc = "R8_BAT_STATUS (r) register accessor: RO, battery status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_bat_status`] module"]
#[doc(alias = "R8_BAT_STATUS")]
pub type R8BatStatus = crate::Reg<r8_bat_status::R8BatStatusSpec>;
#[doc = "RO, battery status"]
pub mod r8_bat_status {
#[doc = "Register `R8_BAT_STATUS` reader"]
pub type R = crate::R<R8BatStatusSpec>;
#[doc = "Field `RB_BAT_STAT_LOW` reader - RO, battery low voltage status, high action"]
pub type RbBatStatLowR = crate::BitReader;
impl R {
#[doc = "Bit 1 - RO, battery low voltage status, high action"]
#[inline(always)]
pub fn rb_bat_stat_low(&self) -> RbBatStatLowR {
RbBatStatLowR::new(((self.bits >> 1) & 1) != 0)
}
}
#[doc = "RO, battery status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_bat_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8BatStatusSpec;
impl crate::RegisterSpec for R8BatStatusSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_bat_status::R`](R) reader structure"]
impl crate::Readable for R8BatStatusSpec {}
#[doc = "`reset()` method sets R8_BAT_STATUS to value 0"]
impl crate::Resettable for R8BatStatusSpec {}
}
#[doc = "R8_LSI_CONFIG (rw) register accessor: RWA, LSI configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_lsi_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_lsi_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_lsi_config`] module"]
#[doc(alias = "R8_LSI_CONFIG")]
pub type R8LsiConfig = crate::Reg<r8_lsi_config::R8LsiConfigSpec>;
#[doc = "RWA, LSI configure register"]
pub mod r8_lsi_config {
#[doc = "Register `R8_LSI_CONFIG` reader"]
pub type R = crate::R<R8LsiConfigSpec>;
#[doc = "Register `R8_LSI_CONFIG` writer"]
pub type W = crate::W<R8LsiConfigSpec>;
#[doc = "Field `RB_CLK_LSI_PON` reader - RWA, Internal low-frequency RC oscillator LSI power control bit"]
pub type RbClkLsiPonR = crate::BitReader;
#[doc = "Field `RB_CLK_LSI_PON` writer - RWA, Internal low-frequency RC oscillator LSI power control bit"]
pub type RbClkLsiPonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_LSI_CLK_PIN` reader - RO, LSI clock pin status (asynchronous signal)"]
pub type RbLsiClkPinR = crate::BitReader;
#[doc = "Field `RB_LSI_CLK_PIN` writer - RO, LSI clock pin status (asynchronous signal)"]
pub type RbLsiClkPinW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - RWA, Internal low-frequency RC oscillator LSI power control bit"]
#[inline(always)]
pub fn rb_clk_lsi_pon(&self) -> RbClkLsiPonR {
RbClkLsiPonR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 7 - RO, LSI clock pin status (asynchronous signal)"]
#[inline(always)]
pub fn rb_lsi_clk_pin(&self) -> RbLsiClkPinR {
RbLsiClkPinR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - RWA, Internal low-frequency RC oscillator LSI power control bit"]
#[inline(always)]
pub fn rb_clk_lsi_pon(&mut self) -> RbClkLsiPonW<R8LsiConfigSpec> {
RbClkLsiPonW::new(self, 1)
}
#[doc = "Bit 7 - RO, LSI clock pin status (asynchronous signal)"]
#[inline(always)]
pub fn rb_lsi_clk_pin(&mut self) -> RbLsiClkPinW<R8LsiConfigSpec> {
RbLsiClkPinW::new(self, 7)
}
}
#[doc = "RWA, LSI configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_lsi_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_lsi_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8LsiConfigSpec;
impl crate::RegisterSpec for R8LsiConfigSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_lsi_config::R`](R) reader structure"]
impl crate::Readable for R8LsiConfigSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_lsi_config::W`](W) writer structure"]
impl crate::Writable for R8LsiConfigSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_LSI_CONFIG to value 0"]
impl crate::Resettable for R8LsiConfigSpec {}
}
}
#[doc = "Real time clock"]
pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Rtc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rtc").finish()
}
}
#[doc = "Real time clock"]
pub mod rtc {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x30],
r8_rtc_flag_ctrl: R8RtcFlagCtrl,
r8_rtc_mode_ctrl: R8RtcModeCtrl,
_reserved2: [u8; 0x02],
r32_rtc_trig: R32RtcTrig,
r16_rtc_cnt_lsi: R16RtcCntLsi,
r16_rtc_cnt_div1: R16RtcCntDiv1,
r32_rtc_cnt_div2: R32RtcCntDiv2,
}
impl RegisterBlock {
#[doc = "0x30 - RWA, Real time clock"]
#[inline(always)]
pub const fn r8_rtc_flag_ctrl(&self) -> &R8RtcFlagCtrl {
&self.r8_rtc_flag_ctrl
}
#[doc = "0x31 - RWA, RTC mode control, SAM"]
#[inline(always)]
pub const fn r8_rtc_mode_ctrl(&self) -> &R8RtcModeCtrl {
&self.r8_rtc_mode_ctrl
}
#[doc = "0x34 - RWA, RTC trigger value, SAM"]
#[inline(always)]
pub const fn r32_rtc_trig(&self) -> &R32RtcTrig {
&self.r32_rtc_trig
}
#[doc = "0x38 - RO, RTC count based lsi"]
#[inline(always)]
pub const fn r16_rtc_cnt_lsi(&self) -> &R16RtcCntLsi {
&self.r16_rtc_cnt_lsi
}
#[doc = "0x3a - RO, RTC count based 65536 LSI clock cycles"]
#[inline(always)]
pub const fn r16_rtc_cnt_div1(&self) -> &R16RtcCntDiv1 {
&self.r16_rtc_cnt_div1
}
#[doc = "0x3c - RO, RTC count based 2831155200 LSI clock cycles, only low 14 bit"]
#[inline(always)]
pub const fn r32_rtc_cnt_div2(&self) -> &R32RtcCntDiv2 {
&self.r32_rtc_cnt_div2
}
}
#[doc = "R8_RTC_FLAG_CTRL (rw) register accessor: RWA, Real time clock\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rtc_flag_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rtc_flag_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_rtc_flag_ctrl`] module"]
#[doc(alias = "R8_RTC_FLAG_CTRL")]
pub type R8RtcFlagCtrl = crate::Reg<r8_rtc_flag_ctrl::R8RtcFlagCtrlSpec>;
#[doc = "RWA, Real time clock"]
pub mod r8_rtc_flag_ctrl {
#[doc = "Register `R8_RTC_FLAG_CTRL` reader"]
pub type R = crate::R<R8RtcFlagCtrlSpec>;
#[doc = "Register `R8_RTC_FLAG_CTRL` writer"]
pub type W = crate::W<R8RtcFlagCtrlSpec>;
#[doc = "Field `RB_RTC_TMR_CLR` reader - RW, set 1 to clear RTC timer action flag, auto clear"]
pub type RbRtcTmrClrR = crate::BitReader;
#[doc = "Field `RB_RTC_TMR_CLR` writer - RW, set 1 to clear RTC timer action flag, auto clear"]
pub type RbRtcTmrClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_TRIG_CLR` reader - RW, set 1 to clear RTC trigger action flag, auto clear"]
pub type RbRtcTrigClrR = crate::BitReader;
#[doc = "Field `RB_RTC_TRIG_CLR` writer - RW, set 1 to clear RTC trigger action flag, auto clear"]
pub type RbRtcTrigClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_TMR_FLAG` reader - RO, RTC timer action flag"]
pub type RbRtcTmrFlagR = crate::BitReader;
#[doc = "Field `RB_RTC_TRIG_FLAG` reader - RO, RTC trigger action flag"]
pub type RbRtcTrigFlagR = crate::BitReader;
impl R {
#[doc = "Bit 4 - RW, set 1 to clear RTC timer action flag, auto clear"]
#[inline(always)]
pub fn rb_rtc_tmr_clr(&self) -> RbRtcTmrClrR {
RbRtcTmrClrR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RW, set 1 to clear RTC trigger action flag, auto clear"]
#[inline(always)]
pub fn rb_rtc_trig_clr(&self) -> RbRtcTrigClrR {
RbRtcTrigClrR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, RTC timer action flag"]
#[inline(always)]
pub fn rb_rtc_tmr_flag(&self) -> RbRtcTmrFlagR {
RbRtcTmrFlagR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, RTC trigger action flag"]
#[inline(always)]
pub fn rb_rtc_trig_flag(&self) -> RbRtcTrigFlagR {
RbRtcTrigFlagR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 4 - RW, set 1 to clear RTC timer action flag, auto clear"]
#[inline(always)]
pub fn rb_rtc_tmr_clr(&mut self) -> RbRtcTmrClrW<R8RtcFlagCtrlSpec> {
RbRtcTmrClrW::new(self, 4)
}
#[doc = "Bit 5 - RW, set 1 to clear RTC trigger action flag, auto clear"]
#[inline(always)]
pub fn rb_rtc_trig_clr(&mut self) -> RbRtcTrigClrW<R8RtcFlagCtrlSpec> {
RbRtcTrigClrW::new(self, 5)
}
}
#[doc = "RWA, Real time clock\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rtc_flag_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rtc_flag_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8RtcFlagCtrlSpec;
impl crate::RegisterSpec for R8RtcFlagCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_rtc_flag_ctrl::R`](R) reader structure"]
impl crate::Readable for R8RtcFlagCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_rtc_flag_ctrl::W`](W) writer structure"]
impl crate::Writable for R8RtcFlagCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_RTC_FLAG_CTRL to value 0x30"]
impl crate::Resettable for R8RtcFlagCtrlSpec {
const RESET_VALUE: u8 = 0x30;
}
}
#[doc = "R8_RTC_MODE_CTRL (rw) register accessor: RWA, RTC mode control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rtc_mode_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rtc_mode_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_rtc_mode_ctrl`] module"]
#[doc(alias = "R8_RTC_MODE_CTRL")]
pub type R8RtcModeCtrl = crate::Reg<r8_rtc_mode_ctrl::R8RtcModeCtrlSpec>;
#[doc = "RWA, RTC mode control, SAM"]
pub mod r8_rtc_mode_ctrl {
#[doc = "Register `R8_RTC_MODE_CTRL` reader"]
pub type R = crate::R<R8RtcModeCtrlSpec>;
#[doc = "Register `R8_RTC_MODE_CTRL` writer"]
pub type W = crate::W<R8RtcModeCtrlSpec>;
#[doc = "Field `RB_RTC_TMR_MODE` reader - RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S"]
pub type RbRtcTmrModeR = crate::FieldReader;
#[doc = "Field `RB_RTC_TMR_MODE` writer - RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S"]
pub type RbRtcTmrModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_RTC_IGNORE_B0` reader - RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0"]
pub type RbRtcIgnoreB0R = crate::BitReader;
#[doc = "Field `RB_RTC_IGNORE_B0` writer - RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0"]
pub type RbRtcIgnoreB0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_TMR_EN` reader - RWA, RTC timer mode enable"]
pub type RbRtcTmrEnR = crate::BitReader;
#[doc = "Field `RB_RTC_TMR_EN` writer - RWA, RTC timer mode enable"]
pub type RbRtcTmrEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_TRIG_EN` reader - RWA, RTC trigger mode enable"]
pub type RbRtcTrigEnR = crate::BitReader;
#[doc = "Field `RB_RTC_TRIG_EN` writer - RWA, RTC trigger mode enable"]
pub type RbRtcTrigEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_LOAD_LO` reader - RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded"]
pub type RbRtcLoadLoR = crate::BitReader;
#[doc = "Field `RB_RTC_LOAD_LO` writer - RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded"]
pub type RbRtcLoadLoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_RTC_LOAD_HI` reader - RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded"]
pub type RbRtcLoadHiR = crate::BitReader;
#[doc = "Field `RB_RTC_LOAD_HI` writer - RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded"]
pub type RbRtcLoadHiW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S"]
#[inline(always)]
pub fn rb_rtc_tmr_mode(&self) -> RbRtcTmrModeR {
RbRtcTmrModeR::new(self.bits & 7)
}
#[doc = "Bit 3 - RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0"]
#[inline(always)]
pub fn rb_rtc_ignore_b0(&self) -> RbRtcIgnoreB0R {
RbRtcIgnoreB0R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RWA, RTC timer mode enable"]
#[inline(always)]
pub fn rb_rtc_tmr_en(&self) -> RbRtcTmrEnR {
RbRtcTmrEnR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RWA, RTC trigger mode enable"]
#[inline(always)]
pub fn rb_rtc_trig_en(&self) -> RbRtcTrigEnR {
RbRtcTrigEnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded"]
#[inline(always)]
pub fn rb_rtc_load_lo(&self) -> RbRtcLoadLoR {
RbRtcLoadLoR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded"]
#[inline(always)]
pub fn rb_rtc_load_hi(&self) -> RbRtcLoadHiR {
RbRtcLoadHiR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S"]
#[inline(always)]
pub fn rb_rtc_tmr_mode(&mut self) -> RbRtcTmrModeW<R8RtcModeCtrlSpec> {
RbRtcTmrModeW::new(self, 0)
}
#[doc = "Bit 3 - RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0"]
#[inline(always)]
pub fn rb_rtc_ignore_b0(&mut self) -> RbRtcIgnoreB0W<R8RtcModeCtrlSpec> {
RbRtcIgnoreB0W::new(self, 3)
}
#[doc = "Bit 4 - RWA, RTC timer mode enable"]
#[inline(always)]
pub fn rb_rtc_tmr_en(&mut self) -> RbRtcTmrEnW<R8RtcModeCtrlSpec> {
RbRtcTmrEnW::new(self, 4)
}
#[doc = "Bit 5 - RWA, RTC trigger mode enable"]
#[inline(always)]
pub fn rb_rtc_trig_en(&mut self) -> RbRtcTrigEnW<R8RtcModeCtrlSpec> {
RbRtcTrigEnW::new(self, 5)
}
#[doc = "Bit 6 - RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded"]
#[inline(always)]
pub fn rb_rtc_load_lo(&mut self) -> RbRtcLoadLoW<R8RtcModeCtrlSpec> {
RbRtcLoadLoW::new(self, 6)
}
#[doc = "Bit 7 - RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded"]
#[inline(always)]
pub fn rb_rtc_load_hi(&mut self) -> RbRtcLoadHiW<R8RtcModeCtrlSpec> {
RbRtcLoadHiW::new(self, 7)
}
}
#[doc = "RWA, RTC mode control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rtc_mode_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rtc_mode_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8RtcModeCtrlSpec;
impl crate::RegisterSpec for R8RtcModeCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_rtc_mode_ctrl::R`](R) reader structure"]
impl crate::Readable for R8RtcModeCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_rtc_mode_ctrl::W`](W) writer structure"]
impl crate::Writable for R8RtcModeCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_RTC_MODE_CTRL to value 0xc2"]
impl crate::Resettable for R8RtcModeCtrlSpec {
const RESET_VALUE: u8 = 0xc2;
}
}
#[doc = "R32_RTC_TRIG (rw) register accessor: RWA, RTC trigger value, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_rtc_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_rtc_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_rtc_trig`] module"]
#[doc(alias = "R32_RTC_TRIG")]
pub type R32RtcTrig = crate::Reg<r32_rtc_trig::R32RtcTrigSpec>;
#[doc = "RWA, RTC trigger value, SAM"]
pub mod r32_rtc_trig {
#[doc = "Register `R32_RTC_TRIG` reader"]
pub type R = crate::R<R32RtcTrigSpec>;
#[doc = "Register `R32_RTC_TRIG` writer"]
pub type W = crate::W<R32RtcTrigSpec>;
#[doc = "Field `R32_RTC_TRIG` reader - RWA, RTC trigger value"]
pub type R32RtcTrigR = crate::FieldReader<u32>;
#[doc = "Field `R32_RTC_TRIG` writer - RWA, RTC trigger value"]
pub type R32RtcTrigW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RWA, RTC trigger value"]
#[inline(always)]
pub fn r32_rtc_trig(&self) -> R32RtcTrigR {
R32RtcTrigR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RWA, RTC trigger value"]
#[inline(always)]
pub fn r32_rtc_trig(&mut self) -> R32RtcTrigW<R32RtcTrigSpec> {
R32RtcTrigW::new(self, 0)
}
}
#[doc = "RWA, RTC trigger value, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_rtc_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_rtc_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32RtcTrigSpec;
impl crate::RegisterSpec for R32RtcTrigSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_rtc_trig::R`](R) reader structure"]
impl crate::Readable for R32RtcTrigSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_rtc_trig::W`](W) writer structure"]
impl crate::Writable for R32RtcTrigSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_RTC_TRIG to value 0"]
impl crate::Resettable for R32RtcTrigSpec {}
}
#[doc = "R16_RTC_CNT_LSI (r) register accessor: RO, RTC count based lsi\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_rtc_cnt_lsi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_rtc_cnt_lsi`] module"]
#[doc(alias = "R16_RTC_CNT_LSI")]
pub type R16RtcCntLsi = crate::Reg<r16_rtc_cnt_lsi::R16RtcCntLsiSpec>;
#[doc = "RO, RTC count based lsi"]
pub mod r16_rtc_cnt_lsi {
#[doc = "Register `R16_RTC_CNT_LSI` reader"]
pub type R = crate::R<R16RtcCntLsiSpec>;
#[doc = "Field `R16_RTC_CNT_LSI` reader - R0,RTC count based lsi"]
pub type R16RtcCntLsiR = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - R0,RTC count based lsi"]
#[inline(always)]
pub fn r16_rtc_cnt_lsi(&self) -> R16RtcCntLsiR {
R16RtcCntLsiR::new(self.bits)
}
}
#[doc = "RO, RTC count based lsi\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_rtc_cnt_lsi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16RtcCntLsiSpec;
impl crate::RegisterSpec for R16RtcCntLsiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_rtc_cnt_lsi::R`](R) reader structure"]
impl crate::Readable for R16RtcCntLsiSpec {}
#[doc = "`reset()` method sets R16_RTC_CNT_LSI to value 0"]
impl crate::Resettable for R16RtcCntLsiSpec {}
}
#[doc = "R16_RTC_CNT_DIV1 (r) register accessor: RO, RTC count based 65536 LSI clock cycles\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_rtc_cnt_div1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_rtc_cnt_div1`] module"]
#[doc(alias = "R16_RTC_CNT_DIV1")]
pub type R16RtcCntDiv1 = crate::Reg<r16_rtc_cnt_div1::R16RtcCntDiv1Spec>;
#[doc = "RO, RTC count based 65536 LSI clock cycles"]
pub mod r16_rtc_cnt_div1 {
#[doc = "Register `R16_RTC_CNT_DIV1` reader"]
pub type R = crate::R<R16RtcCntDiv1Spec>;
#[doc = "Field `R16_RTC_CNT_DIV1` reader - RO, RTC count based 65536 LSI clock cycles"]
pub type R16RtcCntDiv1R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - RO, RTC count based 65536 LSI clock cycles"]
#[inline(always)]
pub fn r16_rtc_cnt_div1(&self) -> R16RtcCntDiv1R {
R16RtcCntDiv1R::new(self.bits)
}
}
#[doc = "RO, RTC count based 65536 LSI clock cycles\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_rtc_cnt_div1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16RtcCntDiv1Spec;
impl crate::RegisterSpec for R16RtcCntDiv1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_rtc_cnt_div1::R`](R) reader structure"]
impl crate::Readable for R16RtcCntDiv1Spec {}
#[doc = "`reset()` method sets R16_RTC_CNT_DIV1 to value 0"]
impl crate::Resettable for R16RtcCntDiv1Spec {}
}
#[doc = "R32_RTC_CNT_DIV2 (r) register accessor: RO, RTC count based 2831155200 LSI clock cycles, only low 14 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_rtc_cnt_div2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_rtc_cnt_div2`] module"]
#[doc(alias = "R32_RTC_CNT_DIV2")]
pub type R32RtcCntDiv2 = crate::Reg<r32_rtc_cnt_div2::R32RtcCntDiv2Spec>;
#[doc = "RO, RTC count based 2831155200 LSI clock cycles, only low 14 bit"]
pub mod r32_rtc_cnt_div2 {
#[doc = "Register `R32_RTC_CNT_DIV2` reader"]
pub type R = crate::R<R32RtcCntDiv2Spec>;
#[doc = "Field `R32_RTC_CNT_DIV2` reader - RWA,RTC count based 2831155200 LSI clock cycles"]
pub type R32RtcCntDiv2R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:13 - RWA,RTC count based 2831155200 LSI clock cycles"]
#[inline(always)]
pub fn r32_rtc_cnt_div2(&self) -> R32RtcCntDiv2R {
R32RtcCntDiv2R::new((self.bits & 0x3fff) as u16)
}
}
#[doc = "RO, RTC count based 2831155200 LSI clock cycles, only low 14 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_rtc_cnt_div2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32RtcCntDiv2Spec;
impl crate::RegisterSpec for R32RtcCntDiv2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_rtc_cnt_div2::R`](R) reader structure"]
impl crate::Readable for R32RtcCntDiv2Spec {}
#[doc = "`reset()` method sets R32_RTC_CNT_DIV2 to value 0"]
impl crate::Resettable for R32RtcCntDiv2Spec {}
}
}
#[doc = "System control related registers"]
pub type SystemControl = crate::Periph<system_control::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for SystemControl {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SystemControl").finish()
}
}
#[doc = "System control related registers"]
pub mod system_control {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x40],
r8_safe_access_sig: R8SafeAccessSig,
r8_chip_id: R8ChipId,
r8_safe_access_id: R8SafeAccessId,
r8_wdog_count: R8WdogCount,
r8_reset_status_r8_glob_rom_cfg: R8ResetStatusR8GlobRomCfg,
r8_glob_cfg_info: R8GlobCfgInfo,
r8_rst_wdog_ctrl: R8RstWdogCtrl,
r8_glob_reset_keep: R8GlobResetKeep,
_reserved8: [u8; 0x03],
r8_pll_config: R8PllConfig,
_reserved9: [u8; 0x02],
r8_xt32m_tune: R8Xt32mTune,
_reserved10: [u8; 0x01],
r16_osc_cal_cnt: R16OscCalCnt,
r8_osc_cal_ov_cnt: R8OscCalOvCnt,
r8_osc_cal_ctrl: R8OscCalCtrl,
}
impl RegisterBlock {
#[doc = "0x40 - WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode"]
#[inline(always)]
pub const fn r8_safe_access_sig(&self) -> &R8SafeAccessSig {
&self.r8_safe_access_sig
}
#[doc = "0x41 - RF, chip ID register, always is ID_CH57*"]
#[inline(always)]
pub const fn r8_chip_id(&self) -> &R8ChipId {
&self.r8_chip_id
}
#[doc = "0x42 - RF, safe accessing ID register, always 0x0C"]
#[inline(always)]
pub const fn r8_safe_access_id(&self) -> &R8SafeAccessId {
&self.r8_safe_access_id
}
#[doc = "0x43 - RW, watch-dog count, count by clock frequency Fsys/131072"]
#[inline(always)]
pub const fn r8_wdog_count(&self) -> &R8WdogCount {
&self.r8_wdog_count
}
#[doc = "0x44 - RWA, reset status, SAM or flash ROM configuration"]
#[inline(always)]
pub const fn r8_reset_status_r8_glob_rom_cfg(&self) -> &R8ResetStatusR8GlobRomCfg {
&self.r8_reset_status_r8_glob_rom_cfg
}
#[doc = "0x45 - RO, global configuration information and status"]
#[inline(always)]
pub const fn r8_glob_cfg_info(&self) -> &R8GlobCfgInfo {
&self.r8_glob_cfg_info
}
#[doc = "0x46 - RWA, reset and watch-dog control, SAM"]
#[inline(always)]
pub const fn r8_rst_wdog_ctrl(&self) -> &R8RstWdogCtrl {
&self.r8_rst_wdog_ctrl
}
#[doc = "0x47 - RW, value keeper during global reset"]
#[inline(always)]
pub const fn r8_glob_reset_keep(&self) -> &R8GlobResetKeep {
&self.r8_glob_reset_keep
}
#[doc = "0x4b - RWA, PLL configuration control, SAM"]
#[inline(always)]
pub const fn r8_pll_config(&self) -> &R8PllConfig {
&self.r8_pll_config
}
#[doc = "0x4e - RWA, external 32MHz oscillator tune control, SAM"]
#[inline(always)]
pub const fn r8_xt32m_tune(&self) -> &R8Xt32mTune {
&self.r8_xt32m_tune
}
#[doc = "0x50 - RO, system clock count value for 32KHz multi-cycles"]
#[inline(always)]
pub const fn r16_osc_cal_cnt(&self) -> &R16OscCalCnt {
&self.r16_osc_cal_cnt
}
#[doc = "0x52 - RO, oscillator frequency calibration overflow times"]
#[inline(always)]
pub const fn r8_osc_cal_ov_cnt(&self) -> &R8OscCalOvCnt {
&self.r8_osc_cal_ov_cnt
}
#[doc = "0x53 - RWA, oscillator frequency calibration control, SAM"]
#[inline(always)]
pub const fn r8_osc_cal_ctrl(&self) -> &R8OscCalCtrl {
&self.r8_osc_cal_ctrl
}
}
#[doc = "R8_SAFE_ACCESS_SIG (rw) register accessor: WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_safe_access_sig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_safe_access_sig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_safe_access_sig`] module"]
#[doc(alias = "R8_SAFE_ACCESS_SIG")]
pub type R8SafeAccessSig = crate::Reg<r8_safe_access_sig::R8SafeAccessSigSpec>;
#[doc = "WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode"]
pub mod r8_safe_access_sig {
#[doc = "Register `R8_SAFE_ACCESS_SIG` reader"]
pub type R = crate::R<R8SafeAccessSigSpec>;
#[doc = "Register `R8_SAFE_ACCESS_SIG` writer"]
pub type W = crate::W<R8SafeAccessSigSpec>;
#[doc = "Field `RB_SAFE_ACC_MODE` reader - RO, current safe accessing mode: 11=safe unlocked (SAM), other=locked (00..01..10..11)"]
pub type RbSafeAccModeR = crate::FieldReader;
#[doc = "Field `R8_SAFE_ACCESS_SIG` writer - WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode"]
pub type R8SafeAccessSigW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RB_SAFE_ACC_ACT` reader - RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled"]
pub type RbSafeAccActR = crate::BitReader;
#[doc = "Field `RB_SAFE_ACC_TIMER` reader - RO, safe accessing timer bit mask (16*clock number)"]
pub type RbSafeAccTimerR = crate::FieldReader;
impl R {
#[doc = "Bits 0:1 - RO, current safe accessing mode: 11=safe unlocked (SAM), other=locked (00..01..10..11)"]
#[inline(always)]
pub fn rb_safe_acc_mode(&self) -> RbSafeAccModeR {
RbSafeAccModeR::new(self.bits & 3)
}
#[doc = "Bit 2 - RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled"]
#[inline(always)]
pub fn rb_safe_acc_act(&self) -> RbSafeAccActR {
RbSafeAccActR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:7 - RO, safe accessing timer bit mask (16*clock number)"]
#[inline(always)]
pub fn rb_safe_acc_timer(&self) -> RbSafeAccTimerR {
RbSafeAccTimerR::new((self.bits >> 3) & 0x1f)
}
}
impl W {
#[doc = "Bits 0:7 - WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode"]
#[inline(always)]
pub fn r8_safe_access_sig(&mut self) -> R8SafeAccessSigW<R8SafeAccessSigSpec> {
R8SafeAccessSigW::new(self, 0)
}
}
#[doc = "WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_safe_access_sig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_safe_access_sig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SafeAccessSigSpec;
impl crate::RegisterSpec for R8SafeAccessSigSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_safe_access_sig::R`](R) reader structure"]
impl crate::Readable for R8SafeAccessSigSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_safe_access_sig::W`](W) writer structure"]
impl crate::Writable for R8SafeAccessSigSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SAFE_ACCESS_SIG to value 0"]
impl crate::Resettable for R8SafeAccessSigSpec {}
}
#[doc = "R8_CHIP_ID (r) register accessor: RF, chip ID register, always is ID_CH57*\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_chip_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_chip_id`] module"]
#[doc(alias = "R8_CHIP_ID")]
pub type R8ChipId = crate::Reg<r8_chip_id::R8ChipIdSpec>;
#[doc = "RF, chip ID register, always is ID_CH57*"]
pub mod r8_chip_id {
#[doc = "Register `R8_CHIP_ID` reader"]
pub type R = crate::R<R8ChipIdSpec>;
#[doc = "Field `R8_CHIP_ID` reader - RF,chip ID register"]
pub type R8ChipIdR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RF,chip ID register"]
#[inline(always)]
pub fn r8_chip_id(&self) -> R8ChipIdR {
R8ChipIdR::new(self.bits)
}
}
#[doc = "RF, chip ID register, always is ID_CH57*\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_chip_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8ChipIdSpec;
impl crate::RegisterSpec for R8ChipIdSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_chip_id::R`](R) reader structure"]
impl crate::Readable for R8ChipIdSpec {}
#[doc = "`reset()` method sets R8_CHIP_ID to value 0x72"]
impl crate::Resettable for R8ChipIdSpec {
const RESET_VALUE: u8 = 0x72;
}
}
#[doc = "R8_SAFE_ACCESS_ID (r) register accessor: RF, safe accessing ID register, always 0x0C\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_safe_access_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_safe_access_id`] module"]
#[doc(alias = "R8_SAFE_ACCESS_ID")]
pub type R8SafeAccessId = crate::Reg<r8_safe_access_id::R8SafeAccessIdSpec>;
#[doc = "RF, safe accessing ID register, always 0x0C"]
pub mod r8_safe_access_id {
#[doc = "Register `R8_SAFE_ACCESS_ID` reader"]
pub type R = crate::R<R8SafeAccessIdSpec>;
#[doc = "Field `R8_SAFE_ACCESS_ID` reader - RF,safe accessing ID register"]
pub type R8SafeAccessIdR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RF,safe accessing ID register"]
#[inline(always)]
pub fn r8_safe_access_id(&self) -> R8SafeAccessIdR {
R8SafeAccessIdR::new(self.bits)
}
}
#[doc = "RF, safe accessing ID register, always 0x0C\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_safe_access_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SafeAccessIdSpec;
impl crate::RegisterSpec for R8SafeAccessIdSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_safe_access_id::R`](R) reader structure"]
impl crate::Readable for R8SafeAccessIdSpec {}
#[doc = "`reset()` method sets R8_SAFE_ACCESS_ID to value 0x0c"]
impl crate::Resettable for R8SafeAccessIdSpec {
const RESET_VALUE: u8 = 0x0c;
}
}
#[doc = "R8_WDOG_COUNT (rw) register accessor: RW, watch-dog count, count by clock frequency Fsys/131072\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_wdog_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_wdog_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_wdog_count`] module"]
#[doc(alias = "R8_WDOG_COUNT")]
pub type R8WdogCount = crate::Reg<r8_wdog_count::R8WdogCountSpec>;
#[doc = "RW, watch-dog count, count by clock frequency Fsys/131072"]
pub mod r8_wdog_count {
#[doc = "Register `R8_WDOG_COUNT` reader"]
pub type R = crate::R<R8WdogCountSpec>;
#[doc = "Register `R8_WDOG_COUNT` writer"]
pub type W = crate::W<R8WdogCountSpec>;
#[doc = "Field `R8_WDOG_COUNT` reader - RW,watch-dog count, count by clock frequency Fsys/131072"]
pub type R8WdogCountR = crate::FieldReader;
#[doc = "Field `R8_WDOG_COUNT` writer - RW,watch-dog count, count by clock frequency Fsys/131072"]
pub type R8WdogCountW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW,watch-dog count, count by clock frequency Fsys/131072"]
#[inline(always)]
pub fn r8_wdog_count(&self) -> R8WdogCountR {
R8WdogCountR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RW,watch-dog count, count by clock frequency Fsys/131072"]
#[inline(always)]
pub fn r8_wdog_count(&mut self) -> R8WdogCountW<R8WdogCountSpec> {
R8WdogCountW::new(self, 0)
}
}
#[doc = "RW, watch-dog count, count by clock frequency Fsys/131072\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_wdog_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_wdog_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8WdogCountSpec;
impl crate::RegisterSpec for R8WdogCountSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_wdog_count::R`](R) reader structure"]
impl crate::Readable for R8WdogCountSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_wdog_count::W`](W) writer structure"]
impl crate::Writable for R8WdogCountSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_WDOG_COUNT to value 0"]
impl crate::Resettable for R8WdogCountSpec {}
}
#[doc = "R8_RESET_STATUS_R8_GLOB_ROM_CFG (r) register accessor: RWA, reset status, SAM or flash ROM configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_reset_status_r8_glob_rom_cfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_reset_status_r8_glob_rom_cfg`] module"]
#[doc(alias = "R8_RESET_STATUS_R8_GLOB_ROM_CFG")]
pub type R8ResetStatusR8GlobRomCfg =
crate::Reg<r8_reset_status_r8_glob_rom_cfg::R8ResetStatusR8GlobRomCfgSpec>;
#[doc = "RWA, reset status, SAM or flash ROM configuration"]
pub mod r8_reset_status_r8_glob_rom_cfg {
#[doc = "Register `R8_RESET_STATUS_R8_GLOB_ROM_CFG` reader"]
pub type R = crate::R<R8ResetStatusR8GlobRomCfgSpec>;
#[doc = "Field `RB_RESET_FLAG` reader - RO, recent reset flag"]
pub type RbResetFlagR = crate::FieldReader;
#[doc = "Field `RB_ROM_CODE_OFS` reader - RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x008000"]
pub type RbRomCodeOfsR = crate::BitReader;
#[doc = "Field `RB_ROM_CTRL_EN` reader - RWA, enable flash ROM control interface enable"]
pub type RbRomCtrlEnR = crate::BitReader;
#[doc = "Field `RB_ROM_CODE_WE` reader - RWA, enable flash ROM code area being erase or write"]
pub type RbRomCodeWeR = crate::FieldReader;
impl R {
#[doc = "Bits 0:2 - RO, recent reset flag"]
#[inline(always)]
pub fn rb_reset_flag(&self) -> RbResetFlagR {
RbResetFlagR::new(self.bits & 7)
}
#[doc = "Bit 4 - RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x008000"]
#[inline(always)]
pub fn rb_rom_code_ofs(&self) -> RbRomCodeOfsR {
RbRomCodeOfsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RWA, enable flash ROM control interface enable"]
#[inline(always)]
pub fn rb_rom_ctrl_en(&self) -> RbRomCtrlEnR {
RbRomCtrlEnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - RWA, enable flash ROM code area being erase or write"]
#[inline(always)]
pub fn rb_rom_code_we(&self) -> RbRomCodeWeR {
RbRomCodeWeR::new((self.bits >> 6) & 3)
}
}
#[doc = "RWA, reset status, SAM or flash ROM configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_reset_status_r8_glob_rom_cfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8ResetStatusR8GlobRomCfgSpec;
impl crate::RegisterSpec for R8ResetStatusR8GlobRomCfgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_reset_status_r8_glob_rom_cfg::R`](R) reader structure"]
impl crate::Readable for R8ResetStatusR8GlobRomCfgSpec {}
#[doc = "`reset()` method sets R8_RESET_STATUS_R8_GLOB_ROM_CFG to value 0x01"]
impl crate::Resettable for R8ResetStatusR8GlobRomCfgSpec {
const RESET_VALUE: u8 = 0x01;
}
}
#[doc = "R8_GLOB_CFG_INFO (r) register accessor: RO, global configuration information and status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_glob_cfg_info::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_glob_cfg_info`] module"]
#[doc(alias = "R8_GLOB_CFG_INFO")]
pub type R8GlobCfgInfo = crate::Reg<r8_glob_cfg_info::R8GlobCfgInfoSpec>;
#[doc = "RO, global configuration information and status"]
pub mod r8_glob_cfg_info {
#[doc = "Register `R8_GLOB_CFG_INFO` reader"]
pub type R = crate::R<R8GlobCfgInfoSpec>;
#[doc = "Field `RB_CFG_RESET_EN` reader - RO, manual reset input enable status"]
pub type RbCfgResetEnR = crate::BitReader;
#[doc = "Field `RB_CFG_BOOT_EN` reader - RO, boot-loader enable status"]
pub type RbCfgBootEnR = crate::BitReader;
#[doc = "Field `RB_CFG_RST_PIN` reader - RO, Reset pin selection"]
pub type RbCfgRstPinR = crate::BitReader;
#[doc = "Field `RB_BOOT_LOADER` reader - RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status"]
pub type RbBootLoaderR = crate::BitReader;
impl R {
#[doc = "Bit 2 - RO, manual reset input enable status"]
#[inline(always)]
pub fn rb_cfg_reset_en(&self) -> RbCfgResetEnR {
RbCfgResetEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RO, boot-loader enable status"]
#[inline(always)]
pub fn rb_cfg_boot_en(&self) -> RbCfgBootEnR {
RbCfgBootEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RO, Reset pin selection"]
#[inline(always)]
pub fn rb_cfg_rst_pin(&self) -> RbCfgRstPinR {
RbCfgRstPinR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status"]
#[inline(always)]
pub fn rb_boot_loader(&self) -> RbBootLoaderR {
RbBootLoaderR::new(((self.bits >> 5) & 1) != 0)
}
}
#[doc = "RO, global configuration information and status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_glob_cfg_info::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8GlobCfgInfoSpec;
impl crate::RegisterSpec for R8GlobCfgInfoSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_glob_cfg_info::R`](R) reader structure"]
impl crate::Readable for R8GlobCfgInfoSpec {}
#[doc = "`reset()` method sets R8_GLOB_CFG_INFO to value 0"]
impl crate::Resettable for R8GlobCfgInfoSpec {}
}
#[doc = "R8_RST_WDOG_CTRL (rw) register accessor: RWA, reset and watch-dog control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rst_wdog_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rst_wdog_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_rst_wdog_ctrl`] module"]
#[doc(alias = "R8_RST_WDOG_CTRL")]
pub type R8RstWdogCtrl = crate::Reg<r8_rst_wdog_ctrl::R8RstWdogCtrlSpec>;
#[doc = "RWA, reset and watch-dog control, SAM"]
pub mod r8_rst_wdog_ctrl {
#[doc = "Register `R8_RST_WDOG_CTRL` reader"]
pub type R = crate::R<R8RstWdogCtrlSpec>;
#[doc = "Register `R8_RST_WDOG_CTRL` writer"]
pub type W = crate::W<R8RstWdogCtrlSpec>;
#[doc = "Field `RB_SOFTWARE_RESET` reader - WA or WZ, global software reset, high action, auto clear"]
pub type RbSoftwareResetR = crate::BitReader;
#[doc = "Field `RB_SOFTWARE_RESET` writer - WA or WZ, global software reset, high action, auto clear"]
pub type RbSoftwareResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_BOOT_LOAD_MAN` reader - read-only, Manually enter BOOT Loader flag"]
pub type RbBootLoadManR = crate::BitReader;
#[doc = "Field `RB_BOOT_LOAD_MAN` writer - read-only, Manually enter BOOT Loader flag"]
pub type RbBootLoadManW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_WDOG_RST_EN` reader - RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow"]
pub type RbWdogRstEnR = crate::BitReader;
#[doc = "Field `RB_WDOG_RST_EN` writer - RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow"]
pub type RbWdogRstEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_WDOG_INT_EN` reader - RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable"]
pub type RbWdogIntEnR = crate::BitReader;
#[doc = "Field `RB_WDOG_INT_EN` writer - RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable"]
pub type RbWdogIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_WDOG_INT_FLAG` reader - RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event)"]
pub type RbWdogIntFlagR = crate::BitReader;
#[doc = "Field `RB_WDOG_INT_FLAG` writer - RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event)"]
pub type RbWdogIntFlagW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - WA or WZ, global software reset, high action, auto clear"]
#[inline(always)]
pub fn rb_software_reset(&self) -> RbSoftwareResetR {
RbSoftwareResetR::new((self.bits & 1) != 0)
}
#[doc = "Bit 0 - read-only, Manually enter BOOT Loader flag"]
#[inline(always)]
pub fn rb_boot_load_man(&self) -> RbBootLoadManR {
RbBootLoadManR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow"]
#[inline(always)]
pub fn rb_wdog_rst_en(&self) -> RbWdogRstEnR {
RbWdogRstEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable"]
#[inline(always)]
pub fn rb_wdog_int_en(&self) -> RbWdogIntEnR {
RbWdogIntEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event)"]
#[inline(always)]
pub fn rb_wdog_int_flag(&self) -> RbWdogIntFlagR {
RbWdogIntFlagR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - WA or WZ, global software reset, high action, auto clear"]
#[inline(always)]
pub fn rb_software_reset(&mut self) -> RbSoftwareResetW<R8RstWdogCtrlSpec> {
RbSoftwareResetW::new(self, 0)
}
#[doc = "Bit 0 - read-only, Manually enter BOOT Loader flag"]
#[inline(always)]
pub fn rb_boot_load_man(&mut self) -> RbBootLoadManW<R8RstWdogCtrlSpec> {
RbBootLoadManW::new(self, 0)
}
#[doc = "Bit 1 - RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow"]
#[inline(always)]
pub fn rb_wdog_rst_en(&mut self) -> RbWdogRstEnW<R8RstWdogCtrlSpec> {
RbWdogRstEnW::new(self, 1)
}
#[doc = "Bit 2 - RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable"]
#[inline(always)]
pub fn rb_wdog_int_en(&mut self) -> RbWdogIntEnW<R8RstWdogCtrlSpec> {
RbWdogIntEnW::new(self, 2)
}
#[doc = "Bit 4 - RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event)"]
#[inline(always)]
pub fn rb_wdog_int_flag(&mut self) -> RbWdogIntFlagW<R8RstWdogCtrlSpec> {
RbWdogIntFlagW::new(self, 4)
}
}
#[doc = "RWA, reset and watch-dog control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_rst_wdog_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_rst_wdog_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8RstWdogCtrlSpec;
impl crate::RegisterSpec for R8RstWdogCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_rst_wdog_ctrl::R`](R) reader structure"]
impl crate::Readable for R8RstWdogCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_rst_wdog_ctrl::W`](W) writer structure"]
impl crate::Writable for R8RstWdogCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_RST_WDOG_CTRL to value 0"]
impl crate::Resettable for R8RstWdogCtrlSpec {}
}
#[doc = "R8_GLOB_RESET_KEEP (rw) register accessor: RW, value keeper during global reset\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_glob_reset_keep::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_glob_reset_keep::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_glob_reset_keep`] module"]
#[doc(alias = "R8_GLOB_RESET_KEEP")]
pub type R8GlobResetKeep = crate::Reg<r8_glob_reset_keep::R8GlobResetKeepSpec>;
#[doc = "RW, value keeper during global reset"]
pub mod r8_glob_reset_keep {
#[doc = "Register `R8_GLOB_RESET_KEEP` reader"]
pub type R = crate::R<R8GlobResetKeepSpec>;
#[doc = "Register `R8_GLOB_RESET_KEEP` writer"]
pub type W = crate::W<R8GlobResetKeepSpec>;
#[doc = "Field `R8_GLOB_RESET_KEEP` reader - RW, value keeper during global reset"]
pub type R8GlobResetKeepR = crate::FieldReader;
#[doc = "Field `R8_GLOB_RESET_KEEP` writer - RW, value keeper during global reset"]
pub type R8GlobResetKeepW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, value keeper during global reset"]
#[inline(always)]
pub fn r8_glob_reset_keep(&self) -> R8GlobResetKeepR {
R8GlobResetKeepR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RW, value keeper during global reset"]
#[inline(always)]
pub fn r8_glob_reset_keep(&mut self) -> R8GlobResetKeepW<R8GlobResetKeepSpec> {
R8GlobResetKeepW::new(self, 0)
}
}
#[doc = "RW, value keeper during global reset\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_glob_reset_keep::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_glob_reset_keep::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8GlobResetKeepSpec;
impl crate::RegisterSpec for R8GlobResetKeepSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_glob_reset_keep::R`](R) reader structure"]
impl crate::Readable for R8GlobResetKeepSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_glob_reset_keep::W`](W) writer structure"]
impl crate::Writable for R8GlobResetKeepSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_GLOB_RESET_KEEP to value 0"]
impl crate::Resettable for R8GlobResetKeepSpec {}
}
#[doc = "R8_PLL_CONFIG (rw) register accessor: RWA, PLL configuration control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pll_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pll_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pll_config`] module"]
#[doc(alias = "R8_PLL_CONFIG")]
pub type R8PllConfig = crate::Reg<r8_pll_config::R8PllConfigSpec>;
#[doc = "RWA, PLL configuration control, SAM"]
pub mod r8_pll_config {
#[doc = "Register `R8_PLL_CONFIG` reader"]
pub type R = crate::R<R8PllConfigSpec>;
#[doc = "Register `R8_PLL_CONFIG` writer"]
pub type W = crate::W<R8PllConfigSpec>;
#[doc = "Field `RB_PLL_CFG_DAT` reader - RWA, PLL configure data"]
pub type RbPllCfgDatR = crate::FieldReader;
#[doc = "Field `RB_PLL_CFG_DAT` writer - RWA, PLL configure data"]
pub type RbPllCfgDatW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bits 0:5 - RWA, PLL configure data"]
#[inline(always)]
pub fn rb_pll_cfg_dat(&self) -> RbPllCfgDatR {
RbPllCfgDatR::new(self.bits & 0x3f)
}
}
impl W {
#[doc = "Bits 0:5 - RWA, PLL configure data"]
#[inline(always)]
pub fn rb_pll_cfg_dat(&mut self) -> RbPllCfgDatW<R8PllConfigSpec> {
RbPllCfgDatW::new(self, 0)
}
}
#[doc = "RWA, PLL configuration control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pll_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pll_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PllConfigSpec;
impl crate::RegisterSpec for R8PllConfigSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pll_config::R`](R) reader structure"]
impl crate::Readable for R8PllConfigSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pll_config::W`](W) writer structure"]
impl crate::Writable for R8PllConfigSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PLL_CONFIG to value 0x0a"]
impl crate::Resettable for R8PllConfigSpec {
const RESET_VALUE: u8 = 0x0a;
}
}
#[doc = "R8_XT32M_TUNE (rw) register accessor: RWA, external 32MHz oscillator tune control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_xt32m_tune::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_xt32m_tune::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_xt32m_tune`] module"]
#[doc(alias = "R8_XT32M_TUNE")]
pub type R8Xt32mTune = crate::Reg<r8_xt32m_tune::R8Xt32mTuneSpec>;
#[doc = "RWA, external 32MHz oscillator tune control, SAM"]
pub mod r8_xt32m_tune {
#[doc = "Register `R8_XT32M_TUNE` reader"]
pub type R = crate::R<R8Xt32mTuneSpec>;
#[doc = "Register `R8_XT32M_TUNE` writer"]
pub type W = crate::W<R8Xt32mTuneSpec>;
#[doc = "Field `RB_XT32M_I_BIAS` reader - RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current"]
pub type RbXt32mIBiasR = crate::FieldReader;
#[doc = "Field `RB_XT32M_I_BIAS` writer - RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current"]
pub type RbXt32mIBiasW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_XT32M_C_LOAD` reader - RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF"]
pub type RbXt32mCLoadR = crate::FieldReader;
#[doc = "Field `RB_XT32M_C_LOAD` writer - RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF"]
pub type RbXt32mCLoadW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 0:1 - RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current"]
#[inline(always)]
pub fn rb_xt32m_i_bias(&self) -> RbXt32mIBiasR {
RbXt32mIBiasR::new(self.bits & 3)
}
#[doc = "Bits 4:6 - RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF"]
#[inline(always)]
pub fn rb_xt32m_c_load(&self) -> RbXt32mCLoadR {
RbXt32mCLoadR::new((self.bits >> 4) & 7)
}
}
impl W {
#[doc = "Bits 0:1 - RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current"]
#[inline(always)]
pub fn rb_xt32m_i_bias(&mut self) -> RbXt32mIBiasW<R8Xt32mTuneSpec> {
RbXt32mIBiasW::new(self, 0)
}
#[doc = "Bits 4:6 - RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF"]
#[inline(always)]
pub fn rb_xt32m_c_load(&mut self) -> RbXt32mCLoadW<R8Xt32mTuneSpec> {
RbXt32mCLoadW::new(self, 4)
}
}
#[doc = "RWA, external 32MHz oscillator tune control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_xt32m_tune::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_xt32m_tune::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Xt32mTuneSpec;
impl crate::RegisterSpec for R8Xt32mTuneSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_xt32m_tune::R`](R) reader structure"]
impl crate::Readable for R8Xt32mTuneSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_xt32m_tune::W`](W) writer structure"]
impl crate::Writable for R8Xt32mTuneSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_XT32M_TUNE to value 0x52"]
impl crate::Resettable for R8Xt32mTuneSpec {
const RESET_VALUE: u8 = 0x52;
}
}
#[doc = "R16_OSC_CAL_CNT (r) register accessor: RO, system clock count value for 32KHz multi-cycles\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_osc_cal_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_osc_cal_cnt`] module"]
#[doc(alias = "R16_OSC_CAL_CNT")]
pub type R16OscCalCnt = crate::Reg<r16_osc_cal_cnt::R16OscCalCntSpec>;
#[doc = "RO, system clock count value for 32KHz multi-cycles"]
pub mod r16_osc_cal_cnt {
#[doc = "Register `R16_OSC_CAL_CNT` reader"]
pub type R = crate::R<R16OscCalCntSpec>;
#[doc = "Field `RB_OSC_CAL_CNT` reader - RO, system clock count value for 32KHz multi-cycles"]
pub type RbOscCalCntR = crate::FieldReader<u16>;
#[doc = "Field `RB_OSC_CAL_OV_CLR` reader - RW1, indicate R8_OSC_CAL_OV_CNT not zero, set 1 to clear R8_OSC_CAL_OV_CNT"]
pub type RbOscCalOvClrR = crate::BitReader;
#[doc = "Field `RB_OSC_CAL_IF` reader - RW1, interrupt flag for oscillator capture end, set 1 to clear"]
pub type RbOscCalIfR = crate::BitReader;
impl R {
#[doc = "Bits 0:13 - RO, system clock count value for 32KHz multi-cycles"]
#[inline(always)]
pub fn rb_osc_cal_cnt(&self) -> RbOscCalCntR {
RbOscCalCntR::new(self.bits & 0x3fff)
}
#[doc = "Bit 14 - RW1, indicate R8_OSC_CAL_OV_CNT not zero, set 1 to clear R8_OSC_CAL_OV_CNT"]
#[inline(always)]
pub fn rb_osc_cal_ov_clr(&self) -> RbOscCalOvClrR {
RbOscCalOvClrR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - RW1, interrupt flag for oscillator capture end, set 1 to clear"]
#[inline(always)]
pub fn rb_osc_cal_if(&self) -> RbOscCalIfR {
RbOscCalIfR::new(((self.bits >> 15) & 1) != 0)
}
}
#[doc = "RO, system clock count value for 32KHz multi-cycles\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_osc_cal_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16OscCalCntSpec;
impl crate::RegisterSpec for R16OscCalCntSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_osc_cal_cnt::R`](R) reader structure"]
impl crate::Readable for R16OscCalCntSpec {}
#[doc = "`reset()` method sets R16_OSC_CAL_CNT to value 0"]
impl crate::Resettable for R16OscCalCntSpec {}
}
#[doc = "R8_OSC_CAL_OV_CNT (r) register accessor: RO, oscillator frequency calibration overflow times\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_osc_cal_ov_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_osc_cal_ov_cnt`] module"]
#[doc(alias = "R8_OSC_CAL_OV_CNT")]
pub type R8OscCalOvCnt = crate::Reg<r8_osc_cal_ov_cnt::R8OscCalOvCntSpec>;
#[doc = "RO, oscillator frequency calibration overflow times"]
pub mod r8_osc_cal_ov_cnt {
#[doc = "Register `R8_OSC_CAL_OV_CNT` reader"]
pub type R = crate::R<R8OscCalOvCntSpec>;
#[doc = "Field `R8_OSC_CAL_OV_CNT` reader - RO, oscillator frequency calibration overflow times"]
pub type R8OscCalOvCntR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RO, oscillator frequency calibration overflow times"]
#[inline(always)]
pub fn r8_osc_cal_ov_cnt(&self) -> R8OscCalOvCntR {
R8OscCalOvCntR::new(self.bits)
}
}
#[doc = "RO, oscillator frequency calibration overflow times\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_osc_cal_ov_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8OscCalOvCntSpec;
impl crate::RegisterSpec for R8OscCalOvCntSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_osc_cal_ov_cnt::R`](R) reader structure"]
impl crate::Readable for R8OscCalOvCntSpec {}
#[doc = "`reset()` method sets R8_OSC_CAL_OV_CNT to value 0"]
impl crate::Resettable for R8OscCalOvCntSpec {}
}
#[doc = "R8_OSC_CAL_CTRL (rw) register accessor: RWA, oscillator frequency calibration control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_osc_cal_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_osc_cal_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_osc_cal_ctrl`] module"]
#[doc(alias = "R8_OSC_CAL_CTRL")]
pub type R8OscCalCtrl = crate::Reg<r8_osc_cal_ctrl::R8OscCalCtrlSpec>;
#[doc = "RWA, oscillator frequency calibration control, SAM"]
pub mod r8_osc_cal_ctrl {
#[doc = "Register `R8_OSC_CAL_CTRL` reader"]
pub type R = crate::R<R8OscCalCtrlSpec>;
#[doc = "Register `R8_OSC_CAL_CTRL` writer"]
pub type W = crate::W<R8OscCalCtrlSpec>;
#[doc = "Field `RB_OSC_CNT_TOTAL` reader - RWA, total cycles mode for oscillator capture"]
pub type RbOscCntTotalR = crate::FieldReader;
#[doc = "Field `RB_OSC_CNT_TOTAL` writer - RWA, total cycles mode for oscillator capture"]
pub type RbOscCntTotalW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_OSC_CNT_HALT` reader - RO, calibration counter halt status: 0=counting, 1=halt for reading count value"]
pub type RbOscCntHaltR = crate::BitReader;
#[doc = "Field `RB_OSC_CAL_IE` reader - RWA, interrupt enable for oscillator capture end"]
pub type RbOscCalIeR = crate::BitReader;
#[doc = "Field `RB_OSC_CAL_IE` writer - RWA, interrupt enable for oscillator capture end"]
pub type RbOscCalIeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_OSC_CNT_EN` reader - RWA, calibration counter enable"]
pub type RbOscCntEnR = crate::BitReader;
#[doc = "Field `RB_OSC_CNT_EN` writer - RWA, calibration counter enable"]
pub type RbOscCntEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_OSC_CNT_END` reader - RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles"]
pub type RbOscCntEndR = crate::BitReader;
#[doc = "Field `RB_OSC_CNT_END` writer - RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles"]
pub type RbOscCntEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CNT_CLR` reader - RWA, Software reset RB_SSC_CNT_TOTAL"]
pub type RbCntClrR = crate::BitReader;
#[doc = "Field `RB_CNT_CLR` writer - RWA, Software reset RB_SSC_CNT_TOTAL"]
pub type RbCntClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - RWA, total cycles mode for oscillator capture"]
#[inline(always)]
pub fn rb_osc_cnt_total(&self) -> RbOscCntTotalR {
RbOscCntTotalR::new(self.bits & 7)
}
#[doc = "Bit 3 - RO, calibration counter halt status: 0=counting, 1=halt for reading count value"]
#[inline(always)]
pub fn rb_osc_cnt_halt(&self) -> RbOscCntHaltR {
RbOscCntHaltR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RWA, interrupt enable for oscillator capture end"]
#[inline(always)]
pub fn rb_osc_cal_ie(&self) -> RbOscCalIeR {
RbOscCalIeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RWA, calibration counter enable"]
#[inline(always)]
pub fn rb_osc_cnt_en(&self) -> RbOscCntEnR {
RbOscCntEnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles"]
#[inline(always)]
pub fn rb_osc_cnt_end(&self) -> RbOscCntEndR {
RbOscCntEndR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RWA, Software reset RB_SSC_CNT_TOTAL"]
#[inline(always)]
pub fn rb_cnt_clr(&self) -> RbCntClrR {
RbCntClrR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - RWA, total cycles mode for oscillator capture"]
#[inline(always)]
pub fn rb_osc_cnt_total(&mut self) -> RbOscCntTotalW<R8OscCalCtrlSpec> {
RbOscCntTotalW::new(self, 0)
}
#[doc = "Bit 4 - RWA, interrupt enable for oscillator capture end"]
#[inline(always)]
pub fn rb_osc_cal_ie(&mut self) -> RbOscCalIeW<R8OscCalCtrlSpec> {
RbOscCalIeW::new(self, 4)
}
#[doc = "Bit 5 - RWA, calibration counter enable"]
#[inline(always)]
pub fn rb_osc_cnt_en(&mut self) -> RbOscCntEnW<R8OscCalCtrlSpec> {
RbOscCntEnW::new(self, 5)
}
#[doc = "Bit 6 - RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles"]
#[inline(always)]
pub fn rb_osc_cnt_end(&mut self) -> RbOscCntEndW<R8OscCalCtrlSpec> {
RbOscCntEndW::new(self, 6)
}
#[doc = "Bit 7 - RWA, Software reset RB_SSC_CNT_TOTAL"]
#[inline(always)]
pub fn rb_cnt_clr(&mut self) -> RbCntClrW<R8OscCalCtrlSpec> {
RbCntClrW::new(self, 7)
}
}
#[doc = "RWA, oscillator frequency calibration control, SAM\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_osc_cal_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_osc_cal_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8OscCalCtrlSpec;
impl crate::RegisterSpec for R8OscCalCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_osc_cal_ctrl::R`](R) reader structure"]
impl crate::Readable for R8OscCalCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_osc_cal_ctrl::W`](W) writer structure"]
impl crate::Writable for R8OscCalCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_OSC_CAL_CTRL to value 0x09"]
impl crate::Resettable for R8OscCalCtrlSpec {
const RESET_VALUE: u8 = 0x09;
}
}
}
#[doc = "Comparer"]
pub type Cmp = crate::Periph<cmp::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Cmp {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cmp").finish()
}
}
#[doc = "Comparer"]
pub mod cmp {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x54],
r32_cmp_ctrl: R32CmpCtrl,
}
impl RegisterBlock {
#[doc = "0x54 - RW, Comparator control register"]
#[inline(always)]
pub const fn r32_cmp_ctrl(&self) -> &R32CmpCtrl {
&self.r32_cmp_ctrl
}
}
#[doc = "R32_CMP_CTRL (rw) register accessor: RW, Comparator control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_cmp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_cmp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_cmp_ctrl`] module"]
#[doc(alias = "R32_CMP_CTRL")]
pub type R32CmpCtrl = crate::Reg<r32_cmp_ctrl::R32CmpCtrlSpec>;
#[doc = "RW, Comparator control register"]
pub mod r32_cmp_ctrl {
#[doc = "Register `R32_CMP_CTRL` reader"]
pub type R = crate::R<R32CmpCtrlSpec>;
#[doc = "Register `R32_CMP_CTRL` writer"]
pub type W = crate::W<R32CmpCtrlSpec>;
#[doc = "Field `RB_CMP_EN` reader - RW, Comparator enabled"]
pub type RbCmpEnR = crate::BitReader;
#[doc = "Field `RB_CMP_EN` writer - RW, Comparator enabled"]
pub type RbCmpEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CMP_CAP` reader - RW, Timer captures channel signal source selection"]
pub type RbCmpCapR = crate::BitReader;
#[doc = "Field `RB_CMP_CAP` writer - RW, Timer captures channel signal source selection"]
pub type RbCmpCapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CMP_SW` reader - RW, Comparator channel selection"]
pub type RbCmpSwR = crate::FieldReader;
#[doc = "Field `RB_CMP_SW` writer - RW, Comparator channel selection"]
pub type RbCmpSwW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_CMP_NREF_LEVEL` reader - RW, Selection of negative reference level for comparator"]
pub type RbCmpNrefLevelR = crate::FieldReader;
#[doc = "Field `RB_CMP_NREF_LEVEL` writer - RW, Selection of negative reference level for comparator"]
pub type RbCmpNrefLevelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RB_CMP_INT` reader - RW, Comparator interrupt enable"]
pub type RbCmpIntR = crate::BitReader;
#[doc = "Field `RB_CMP_INT` writer - RW, Comparator interrupt enable"]
pub type RbCmpIntW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CMP_OUT_SEL` reader - RW, Comparator interrupt generates event selection"]
pub type RbCmpOutSelR = crate::FieldReader;
#[doc = "Field `RB_CMP_IF` reader - RW1, Comparator interrupt flag, write 1 to reset to zero"]
pub type RbCmpIfR = crate::BitReader;
#[doc = "Field `RB_CMP_IF` writer - RW1, Comparator interrupt flag, write 1 to reset to zero"]
pub type RbCmpIfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_APR_OUT_CMP` reader - RW, Real time output signal of comparator"]
pub type RbAprOutCmpR = crate::BitReader;
#[doc = "Field `RB_APR_OUT_CMP` writer - RW, Real time output signal of comparator"]
pub type RbAprOutCmpW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Comparator enabled"]
#[inline(always)]
pub fn rb_cmp_en(&self) -> RbCmpEnR {
RbCmpEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Timer captures channel signal source selection"]
#[inline(always)]
pub fn rb_cmp_cap(&self) -> RbCmpCapR {
RbCmpCapR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3 - RW, Comparator channel selection"]
#[inline(always)]
pub fn rb_cmp_sw(&self) -> RbCmpSwR {
RbCmpSwR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7 - RW, Selection of negative reference level for comparator"]
#[inline(always)]
pub fn rb_cmp_nref_level(&self) -> RbCmpNrefLevelR {
RbCmpNrefLevelR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - RW, Comparator interrupt enable"]
#[inline(always)]
pub fn rb_cmp_int(&self) -> RbCmpIntR {
RbCmpIntR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 10:11 - RW, Comparator interrupt generates event selection"]
#[inline(always)]
pub fn rb_cmp_out_sel(&self) -> RbCmpOutSelR {
RbCmpOutSelR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 16 - RW1, Comparator interrupt flag, write 1 to reset to zero"]
#[inline(always)]
pub fn rb_cmp_if(&self) -> RbCmpIfR {
RbCmpIfR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 25 - RW, Real time output signal of comparator"]
#[inline(always)]
pub fn rb_apr_out_cmp(&self) -> RbAprOutCmpR {
RbAprOutCmpR::new(((self.bits >> 25) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Comparator enabled"]
#[inline(always)]
pub fn rb_cmp_en(&mut self) -> RbCmpEnW<R32CmpCtrlSpec> {
RbCmpEnW::new(self, 0)
}
#[doc = "Bit 1 - RW, Timer captures channel signal source selection"]
#[inline(always)]
pub fn rb_cmp_cap(&mut self) -> RbCmpCapW<R32CmpCtrlSpec> {
RbCmpCapW::new(self, 1)
}
#[doc = "Bits 2:3 - RW, Comparator channel selection"]
#[inline(always)]
pub fn rb_cmp_sw(&mut self) -> RbCmpSwW<R32CmpCtrlSpec> {
RbCmpSwW::new(self, 2)
}
#[doc = "Bits 4:7 - RW, Selection of negative reference level for comparator"]
#[inline(always)]
pub fn rb_cmp_nref_level(&mut self) -> RbCmpNrefLevelW<R32CmpCtrlSpec> {
RbCmpNrefLevelW::new(self, 4)
}
#[doc = "Bit 8 - RW, Comparator interrupt enable"]
#[inline(always)]
pub fn rb_cmp_int(&mut self) -> RbCmpIntW<R32CmpCtrlSpec> {
RbCmpIntW::new(self, 8)
}
#[doc = "Bit 16 - RW1, Comparator interrupt flag, write 1 to reset to zero"]
#[inline(always)]
pub fn rb_cmp_if(&mut self) -> RbCmpIfW<R32CmpCtrlSpec> {
RbCmpIfW::new(self, 16)
}
#[doc = "Bit 25 - RW, Real time output signal of comparator"]
#[inline(always)]
pub fn rb_apr_out_cmp(&mut self) -> RbAprOutCmpW<R32CmpCtrlSpec> {
RbAprOutCmpW::new(self, 25)
}
}
#[doc = "RW, Comparator control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_cmp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_cmp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32CmpCtrlSpec;
impl crate::RegisterSpec for R32CmpCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_cmp_ctrl::R`](R) reader structure"]
impl crate::Readable for R32CmpCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_cmp_ctrl::W`](W) writer structure"]
impl crate::Writable for R32CmpCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_CMP_CTRL to value 0"]
impl crate::Resettable for R32CmpCtrlSpec {}
}
}
#[doc = "keys scanning"]
pub type Keyscan = crate::Periph<keyscan::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Keyscan {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Keyscan").finish()
}
}
#[doc = "keys scanning"]
pub mod keyscan {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x64],
r16_key_scan_ctrl: R16KeyScanCtrl,
r8_key_scan_int_en: R8KeyScanIntEn,
r8_key_scan_int_flag: R8KeyScanIntFlag,
r32_key_scan_numb: R32KeyScanNumb,
}
impl RegisterBlock {
#[doc = "0x64 - RW, Key scan control register"]
#[inline(always)]
pub const fn r16_key_scan_ctrl(&self) -> &R16KeyScanCtrl {
&self.r16_key_scan_ctrl
}
#[doc = "0x66 - RW, Press button scan interrupt enable register"]
#[inline(always)]
pub const fn r8_key_scan_int_en(&self) -> &R8KeyScanIntEn {
&self.r8_key_scan_int_en
}
#[doc = "0x67 - RW, Press the button to scan the interrupt flag register"]
#[inline(always)]
pub const fn r8_key_scan_int_flag(&self) -> &R8KeyScanIntFlag {
&self.r8_key_scan_int_flag
}
#[doc = "0x68 - RW, Scan key number register"]
#[inline(always)]
pub const fn r32_key_scan_numb(&self) -> &R32KeyScanNumb {
&self.r32_key_scan_numb
}
}
#[doc = "R16_KEY_SCAN_CTRL (rw) register accessor: RW, Key scan control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_key_scan_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_key_scan_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_key_scan_ctrl`] module"]
#[doc(alias = "R16_KEY_SCAN_CTRL")]
pub type R16KeyScanCtrl = crate::Reg<r16_key_scan_ctrl::R16KeyScanCtrlSpec>;
#[doc = "RW, Key scan control register"]
pub mod r16_key_scan_ctrl {
#[doc = "Register `R16_KEY_SCAN_CTRL` reader"]
pub type R = crate::R<R16KeyScanCtrlSpec>;
#[doc = "Register `R16_KEY_SCAN_CTRL` writer"]
pub type W = crate::W<R16KeyScanCtrlSpec>;
#[doc = "Field `RB_SCAN_START_EN` reader - RW, Start scanning enable"]
pub type RbScanStartEnR = crate::BitReader;
#[doc = "Field `RB_SCAN_START_EN` writer - RW, Start scanning enable"]
pub type RbScanStartEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SCAN_CNT_END` reader - RW, Set the number of times to scan to the same key value"]
pub type RbScanCntEndR = crate::FieldReader;
#[doc = "Field `RB_SCAN_CNT_END` writer - RW, Set the number of times to scan to the same key value"]
pub type RbScanCntEndW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RB_SCAN_CLK_DIV` reader - RW, Scan clock frequency division"]
pub type RbScanClkDivR = crate::FieldReader;
#[doc = "Field `RB_SCAN_CLK_DIV` writer - RW, Scan clock frequency division"]
pub type RbScanClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RB_PIN_SCAN_EN` reader - RW, Enable I/O pins involved in key scanning"]
pub type RbPinScanEnR = crate::FieldReader;
#[doc = "Field `RB_PIN_SCAN_EN` writer - RW, Enable I/O pins involved in key scanning"]
pub type RbPinScanEnW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RB_SCAN_1END_WAKE_EN` reader - RW, Activate wake-up signal after a single scan"]
pub type RbScan1endWakeEnR = crate::BitReader;
#[doc = "Field `RB_SCAN_1END_WAKE_EN` writer - RW, Activate wake-up signal after a single scan"]
pub type RbScan1endWakeEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_CLR_WAKEUP_EN` reader - RW, Enable automatic clearing of wake-up signal after wake-up"]
pub type RbClrWakeupEnR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RW, Start scanning enable"]
#[inline(always)]
pub fn rb_scan_start_en(&self) -> RbScanStartEnR {
RbScanStartEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:3 - RW, Set the number of times to scan to the same key value"]
#[inline(always)]
pub fn rb_scan_cnt_end(&self) -> RbScanCntEndR {
RbScanCntEndR::new(((self.bits >> 1) & 7) as u8)
}
#[doc = "Bits 4:7 - RW, Scan clock frequency division"]
#[inline(always)]
pub fn rb_scan_clk_div(&self) -> RbScanClkDivR {
RbScanClkDivR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:12 - RW, Enable I/O pins involved in key scanning"]
#[inline(always)]
pub fn rb_pin_scan_en(&self) -> RbPinScanEnR {
RbPinScanEnR::new(((self.bits >> 8) & 0x1f) as u8)
}
#[doc = "Bit 13 - RW, Activate wake-up signal after a single scan"]
#[inline(always)]
pub fn rb_scan_1end_wake_en(&self) -> RbScan1endWakeEnR {
RbScan1endWakeEnR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - RW, Enable automatic clearing of wake-up signal after wake-up"]
#[inline(always)]
pub fn rb_clr_wakeup_en(&self) -> RbClrWakeupEnR {
RbClrWakeupEnR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Start scanning enable"]
#[inline(always)]
pub fn rb_scan_start_en(&mut self) -> RbScanStartEnW<R16KeyScanCtrlSpec> {
RbScanStartEnW::new(self, 0)
}
#[doc = "Bits 1:3 - RW, Set the number of times to scan to the same key value"]
#[inline(always)]
pub fn rb_scan_cnt_end(&mut self) -> RbScanCntEndW<R16KeyScanCtrlSpec> {
RbScanCntEndW::new(self, 1)
}
#[doc = "Bits 4:7 - RW, Scan clock frequency division"]
#[inline(always)]
pub fn rb_scan_clk_div(&mut self) -> RbScanClkDivW<R16KeyScanCtrlSpec> {
RbScanClkDivW::new(self, 4)
}
#[doc = "Bits 8:12 - RW, Enable I/O pins involved in key scanning"]
#[inline(always)]
pub fn rb_pin_scan_en(&mut self) -> RbPinScanEnW<R16KeyScanCtrlSpec> {
RbPinScanEnW::new(self, 8)
}
#[doc = "Bit 13 - RW, Activate wake-up signal after a single scan"]
#[inline(always)]
pub fn rb_scan_1end_wake_en(&mut self) -> RbScan1endWakeEnW<R16KeyScanCtrlSpec> {
RbScan1endWakeEnW::new(self, 13)
}
}
#[doc = "RW, Key scan control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_key_scan_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_key_scan_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16KeyScanCtrlSpec;
impl crate::RegisterSpec for R16KeyScanCtrlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_key_scan_ctrl::R`](R) reader structure"]
impl crate::Readable for R16KeyScanCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_key_scan_ctrl::W`](W) writer structure"]
impl crate::Writable for R16KeyScanCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_KEY_SCAN_CTRL to value 0"]
impl crate::Resettable for R16KeyScanCtrlSpec {}
}
#[doc = "R8_KEY_SCAN_INT_EN (rw) register accessor: RW, Press button scan interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_key_scan_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_key_scan_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_key_scan_int_en`] module"]
#[doc(alias = "R8_KEY_SCAN_INT_EN")]
pub type R8KeyScanIntEn = crate::Reg<r8_key_scan_int_en::R8KeyScanIntEnSpec>;
#[doc = "RW, Press button scan interrupt enable register"]
pub mod r8_key_scan_int_en {
#[doc = "Register `R8_KEY_SCAN_INT_EN` reader"]
pub type R = crate::R<R8KeyScanIntEnSpec>;
#[doc = "Register `R8_KEY_SCAN_INT_EN` writer"]
pub type W = crate::W<R8KeyScanIntEnSpec>;
#[doc = "Field `RB_KEY_PRESSED_IE` reader - RW, Detected key press and interrupted when the same key value is reached the set value"]
pub type RbKeyPressedIeR = crate::BitReader;
#[doc = "Field `RB_KEY_PRESSED_IE` writer - RW, Detected key press and interrupted when the same key value is reached the set value"]
pub type RbKeyPressedIeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SCAN_1END_IE` reader - RW, Interrupt enable after a single scan is completed"]
pub type RbScan1endIeR = crate::BitReader;
#[doc = "Field `RB_SCAN_1END_IE` writer - RW, Interrupt enable after a single scan is completed"]
pub type RbScan1endIeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Detected key press and interrupted when the same key value is reached the set value"]
#[inline(always)]
pub fn rb_key_pressed_ie(&self) -> RbKeyPressedIeR {
RbKeyPressedIeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Interrupt enable after a single scan is completed"]
#[inline(always)]
pub fn rb_scan_1end_ie(&self) -> RbScan1endIeR {
RbScan1endIeR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Detected key press and interrupted when the same key value is reached the set value"]
#[inline(always)]
pub fn rb_key_pressed_ie(&mut self) -> RbKeyPressedIeW<R8KeyScanIntEnSpec> {
RbKeyPressedIeW::new(self, 0)
}
#[doc = "Bit 1 - RW, Interrupt enable after a single scan is completed"]
#[inline(always)]
pub fn rb_scan_1end_ie(&mut self) -> RbScan1endIeW<R8KeyScanIntEnSpec> {
RbScan1endIeW::new(self, 1)
}
}
#[doc = "RW, Press button scan interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_key_scan_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_key_scan_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8KeyScanIntEnSpec;
impl crate::RegisterSpec for R8KeyScanIntEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_key_scan_int_en::R`](R) reader structure"]
impl crate::Readable for R8KeyScanIntEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_key_scan_int_en::W`](W) writer structure"]
impl crate::Writable for R8KeyScanIntEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_KEY_SCAN_INT_EN to value 0"]
impl crate::Resettable for R8KeyScanIntEnSpec {}
}
#[doc = "R8_KEY_SCAN_INT_FLAG (rw) register accessor: RW, Press the button to scan the interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_key_scan_int_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_key_scan_int_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_key_scan_int_flag`] module"]
#[doc(alias = "R8_KEY_SCAN_INT_FLAG")]
pub type R8KeyScanIntFlag = crate::Reg<r8_key_scan_int_flag::R8KeyScanIntFlagSpec>;
#[doc = "RW, Press the button to scan the interrupt flag register"]
pub mod r8_key_scan_int_flag {
#[doc = "Register `R8_KEY_SCAN_INT_FLAG` reader"]
pub type R = crate::R<R8KeyScanIntFlagSpec>;
#[doc = "Register `R8_KEY_SCAN_INT_FLAG` writer"]
pub type W = crate::W<R8KeyScanIntFlagSpec>;
#[doc = "Field `RB_KEY_PRESSED_IF` reader - RW, Detected button press, and the same button value reaches the set value for the number of times interrupt flag"]
pub type RbKeyPressedIfR = crate::BitReader;
#[doc = "Field `RB_KEY_PRESSED_IF` writer - RW, Detected button press, and the same button value reaches the set value for the number of times interrupt flag"]
pub type RbKeyPressedIfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SCAN_1END_IF` reader - RW, Interrupt flag after word scanning is completed"]
pub type RbScan1endIfR = crate::BitReader;
#[doc = "Field `RB_SCAN_1END_IF` writer - RW, Interrupt flag after word scanning is completed"]
pub type RbScan1endIfW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Detected button press, and the same button value reaches the set value for the number of times interrupt flag"]
#[inline(always)]
pub fn rb_key_pressed_if(&self) -> RbKeyPressedIfR {
RbKeyPressedIfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Interrupt flag after word scanning is completed"]
#[inline(always)]
pub fn rb_scan_1end_if(&self) -> RbScan1endIfR {
RbScan1endIfR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Detected button press, and the same button value reaches the set value for the number of times interrupt flag"]
#[inline(always)]
pub fn rb_key_pressed_if(&mut self) -> RbKeyPressedIfW<R8KeyScanIntFlagSpec> {
RbKeyPressedIfW::new(self, 0)
}
#[doc = "Bit 1 - RW, Interrupt flag after word scanning is completed"]
#[inline(always)]
pub fn rb_scan_1end_if(&mut self) -> RbScan1endIfW<R8KeyScanIntFlagSpec> {
RbScan1endIfW::new(self, 1)
}
}
#[doc = "RW, Press the button to scan the interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_key_scan_int_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_key_scan_int_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8KeyScanIntFlagSpec;
impl crate::RegisterSpec for R8KeyScanIntFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_key_scan_int_flag::R`](R) reader structure"]
impl crate::Readable for R8KeyScanIntFlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_key_scan_int_flag::W`](W) writer structure"]
impl crate::Writable for R8KeyScanIntFlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_KEY_SCAN_INT_FLAG to value 0"]
impl crate::Resettable for R8KeyScanIntFlagSpec {}
}
#[doc = "R32_KEY_SCAN_NUMB (r) register accessor: RW, Scan key number register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_key_scan_numb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_key_scan_numb`] module"]
#[doc(alias = "R32_KEY_SCAN_NUMB")]
pub type R32KeyScanNumb = crate::Reg<r32_key_scan_numb::R32KeyScanNumbSpec>;
#[doc = "RW, Scan key number register"]
pub mod r32_key_scan_numb {
#[doc = "Register `R32_KEY_SCAN_NUMB` reader"]
pub type R = crate::R<R32KeyScanNumbSpec>;
#[doc = "Field `RB_KEY_SCAN_NUMB` reader - RO, Current key number value"]
pub type RbKeyScanNumbR = crate::FieldReader<u32>;
#[doc = "Field `RB_KEY_SCAN_CNT` reader - RO, Current number of key scans"]
pub type RbKeyScanCntR = crate::FieldReader;
impl R {
#[doc = "Bits 0:19 - RO, Current key number value"]
#[inline(always)]
pub fn rb_key_scan_numb(&self) -> RbKeyScanNumbR {
RbKeyScanNumbR::new(self.bits & 0x000f_ffff)
}
#[doc = "Bits 20:22 - RO, Current number of key scans"]
#[inline(always)]
pub fn rb_key_scan_cnt(&self) -> RbKeyScanCntR {
RbKeyScanCntR::new(((self.bits >> 20) & 7) as u8)
}
}
#[doc = "RW, Scan key number register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_key_scan_numb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32KeyScanNumbSpec;
impl crate::RegisterSpec for R32KeyScanNumbSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_key_scan_numb::R`](R) reader structure"]
impl crate::Readable for R32KeyScanNumbSpec {}
#[doc = "`reset()` method sets R32_KEY_SCAN_NUMB to value 0"]
impl crate::Resettable for R32KeyScanNumbSpec {}
}
}
#[doc = "General porpose intput output"]
pub type Gpio = crate::Periph<gpio::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Gpio {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio").finish()
}
}
#[doc = "General porpose intput output"]
pub mod gpio {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x90],
r16_pa_int_en: R16PaIntEn,
_reserved1: [u8; 0x02],
r16_pa_int_mode: R16PaIntMode,
_reserved2: [u8; 0x06],
r16_pa_int_if: R16PaIntIf,
_reserved3: [u8; 0x02],
r32_pa_dir: R32PaDir,
r32_pa_pin: R32PaPin,
r32_pa_out: R32PaOut,
r32_pa_clr: R32PaClr,
r32_pa_pu: R32PaPu,
r32_pa_pd_drv: R32PaPdDrv,
r32_pa_set: R32PaSet,
}
impl RegisterBlock {
#[doc = "0x90 - RW, GPIO PA interrupt enable"]
#[inline(always)]
pub const fn r16_pa_int_en(&self) -> &R16PaIntEn {
&self.r16_pa_int_en
}
#[doc = "0x94 - RW, GPIO PA interrupt mode: 0=level action, 1=edge action"]
#[inline(always)]
pub const fn r16_pa_int_mode(&self) -> &R16PaIntMode {
&self.r16_pa_int_mode
}
#[doc = "0x9c - RW1, GPIO PA interrupt flag"]
#[inline(always)]
pub const fn r16_pa_int_if(&self) -> &R16PaIntIf {
&self.r16_pa_int_if
}
#[doc = "0xa0 - RW, GPIO PA I/O direction: 0=in, 1=out"]
#[inline(always)]
pub const fn r32_pa_dir(&self) -> &R32PaDir {
&self.r32_pa_dir
}
#[doc = "0xa4 - RO, GPIO PA input"]
#[inline(always)]
pub const fn r32_pa_pin(&self) -> &R32PaPin {
&self.r32_pa_pin
}
#[doc = "0xa8 - RW, GPIO PA output"]
#[inline(always)]
pub const fn r32_pa_out(&self) -> &R32PaOut {
&self.r32_pa_out
}
#[doc = "0xac - WZ, GPIO PA clear output: 0=keep, 1=clear"]
#[inline(always)]
pub const fn r32_pa_clr(&self) -> &R32PaClr {
&self.r32_pa_clr
}
#[doc = "0xb0 - RW, GPIO PA pullup resistance enable"]
#[inline(always)]
pub const fn r32_pa_pu(&self) -> &R32PaPu {
&self.r32_pa_pu
}
#[doc = "0xb4 - RW, PA pulldown for input or PA driving capability for output"]
#[inline(always)]
pub const fn r32_pa_pd_drv(&self) -> &R32PaPdDrv {
&self.r32_pa_pd_drv
}
#[doc = "0xb8 - RW, PA port output set register"]
#[inline(always)]
pub const fn r32_pa_set(&self) -> &R32PaSet {
&self.r32_pa_set
}
}
#[doc = "R16_PA_INT_EN (rw) register accessor: RW, GPIO PA interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pa_int_en`] module"]
#[doc(alias = "R16_PA_INT_EN")]
pub type R16PaIntEn = crate::Reg<r16_pa_int_en::R16PaIntEnSpec>;
#[doc = "RW, GPIO PA interrupt enable"]
pub mod r16_pa_int_en {
#[doc = "Register `R16_PA_INT_EN` reader"]
pub type R = crate::R<R16PaIntEnSpec>;
#[doc = "Register `R16_PA_INT_EN` writer"]
pub type W = crate::W<R16PaIntEnSpec>;
#[doc = "Field `R16_PA_INT_EN` reader - GPIO PA interrupt enable"]
pub type R16PaIntEnR = crate::FieldReader<u16>;
#[doc = "Field `R16_PA_INT_EN` writer - GPIO PA interrupt enable"]
pub type R16PaIntEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - GPIO PA interrupt enable"]
#[inline(always)]
pub fn r16_pa_int_en(&self) -> R16PaIntEnR {
R16PaIntEnR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - GPIO PA interrupt enable"]
#[inline(always)]
pub fn r16_pa_int_en(&mut self) -> R16PaIntEnW<R16PaIntEnSpec> {
R16PaIntEnW::new(self, 0)
}
}
#[doc = "RW, GPIO PA interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PaIntEnSpec;
impl crate::RegisterSpec for R16PaIntEnSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pa_int_en::R`](R) reader structure"]
impl crate::Readable for R16PaIntEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pa_int_en::W`](W) writer structure"]
impl crate::Writable for R16PaIntEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PA_INT_EN to value 0"]
impl crate::Resettable for R16PaIntEnSpec {}
}
#[doc = "R16_PA_INT_MODE (rw) register accessor: RW, GPIO PA interrupt mode: 0=level action, 1=edge action\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pa_int_mode`] module"]
#[doc(alias = "R16_PA_INT_MODE")]
pub type R16PaIntMode = crate::Reg<r16_pa_int_mode::R16PaIntModeSpec>;
#[doc = "RW, GPIO PA interrupt mode: 0=level action, 1=edge action"]
pub mod r16_pa_int_mode {
#[doc = "Register `R16_PA_INT_MODE` reader"]
pub type R = crate::R<R16PaIntModeSpec>;
#[doc = "Register `R16_PA_INT_MODE` writer"]
pub type W = crate::W<R16PaIntModeSpec>;
#[doc = "Field `R16_PA_INT_MODE` reader - GPIO PA interrupt mode"]
pub type R16PaIntModeR = crate::FieldReader<u16>;
#[doc = "Field `R16_PA_INT_MODE` writer - GPIO PA interrupt mode"]
pub type R16PaIntModeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - GPIO PA interrupt mode"]
#[inline(always)]
pub fn r16_pa_int_mode(&self) -> R16PaIntModeR {
R16PaIntModeR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - GPIO PA interrupt mode"]
#[inline(always)]
pub fn r16_pa_int_mode(&mut self) -> R16PaIntModeW<R16PaIntModeSpec> {
R16PaIntModeW::new(self, 0)
}
}
#[doc = "RW, GPIO PA interrupt mode: 0=level action, 1=edge action\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PaIntModeSpec;
impl crate::RegisterSpec for R16PaIntModeSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pa_int_mode::R`](R) reader structure"]
impl crate::Readable for R16PaIntModeSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pa_int_mode::W`](W) writer structure"]
impl crate::Writable for R16PaIntModeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PA_INT_MODE to value 0"]
impl crate::Resettable for R16PaIntModeSpec {}
}
#[doc = "R16_PA_INT_IF (rw) register accessor: RW1, GPIO PA interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_if::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_if::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pa_int_if`] module"]
#[doc(alias = "R16_PA_INT_IF")]
pub type R16PaIntIf = crate::Reg<r16_pa_int_if::R16PaIntIfSpec>;
#[doc = "RW1, GPIO PA interrupt flag"]
pub mod r16_pa_int_if {
#[doc = "Register `R16_PA_INT_IF` reader"]
pub type R = crate::R<R16PaIntIfSpec>;
#[doc = "Register `R16_PA_INT_IF` writer"]
pub type W = crate::W<R16PaIntIfSpec>;
#[doc = "Field `R16_PA_INT_IF` reader - GPIO PA interrupt flag"]
pub type R16PaIntIfR = crate::FieldReader<u16>;
#[doc = "Field `R16_PA_INT_IF` writer - GPIO PA interrupt flag"]
pub type R16PaIntIfW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - GPIO PA interrupt flag"]
#[inline(always)]
pub fn r16_pa_int_if(&self) -> R16PaIntIfR {
R16PaIntIfR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - GPIO PA interrupt flag"]
#[inline(always)]
pub fn r16_pa_int_if(&mut self) -> R16PaIntIfW<R16PaIntIfSpec> {
R16PaIntIfW::new(self, 0)
}
}
#[doc = "RW1, GPIO PA interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pa_int_if::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pa_int_if::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PaIntIfSpec;
impl crate::RegisterSpec for R16PaIntIfSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pa_int_if::R`](R) reader structure"]
impl crate::Readable for R16PaIntIfSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pa_int_if::W`](W) writer structure"]
impl crate::Writable for R16PaIntIfSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PA_INT_IF to value 0"]
impl crate::Resettable for R16PaIntIfSpec {}
}
#[doc = "R32_PA_DIR (rw) register accessor: RW, GPIO PA I/O direction: 0=in, 1=out\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_dir`] module"]
#[doc(alias = "R32_PA_DIR")]
pub type R32PaDir = crate::Reg<r32_pa_dir::R32PaDirSpec>;
#[doc = "RW, GPIO PA I/O direction: 0=in, 1=out"]
pub mod r32_pa_dir {
#[doc = "Register `R32_PA_DIR` reader"]
pub type R = crate::R<R32PaDirSpec>;
#[doc = "Register `R32_PA_DIR` writer"]
pub type W = crate::W<R32PaDirSpec>;
#[doc = "Field `R8_PA_DIR_0` reader - GPIO PA I/O direction byte 0"]
pub type R8PaDir0R = crate::FieldReader;
#[doc = "Field `R8_PA_DIR_0` writer - GPIO PA I/O direction byte 0"]
pub type R8PaDir0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_DIR_1` reader - GPIO PA I/O direction byte 1"]
pub type R8PaDir1R = crate::FieldReader;
#[doc = "Field `R8_PA_DIR_1` writer - GPIO PA I/O direction byte 1"]
pub type R8PaDir1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - GPIO PA I/O direction byte 0"]
#[inline(always)]
pub fn r8_pa_dir_0(&self) -> R8PaDir0R {
R8PaDir0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - GPIO PA I/O direction byte 1"]
#[inline(always)]
pub fn r8_pa_dir_1(&self) -> R8PaDir1R {
R8PaDir1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - GPIO PA I/O direction byte 0"]
#[inline(always)]
pub fn r8_pa_dir_0(&mut self) -> R8PaDir0W<R32PaDirSpec> {
R8PaDir0W::new(self, 0)
}
#[doc = "Bits 8:15 - GPIO PA I/O direction byte 1"]
#[inline(always)]
pub fn r8_pa_dir_1(&mut self) -> R8PaDir1W<R32PaDirSpec> {
R8PaDir1W::new(self, 8)
}
}
#[doc = "RW, GPIO PA I/O direction: 0=in, 1=out\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaDirSpec;
impl crate::RegisterSpec for R32PaDirSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_dir::R`](R) reader structure"]
impl crate::Readable for R32PaDirSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pa_dir::W`](W) writer structure"]
impl crate::Writable for R32PaDirSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_DIR to value 0"]
impl crate::Resettable for R32PaDirSpec {}
}
#[doc = "R32_PA_PIN (r) register accessor: RO, GPIO PA input\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_pin`] module"]
#[doc(alias = "R32_PA_PIN")]
pub type R32PaPin = crate::Reg<r32_pa_pin::R32PaPinSpec>;
#[doc = "RO, GPIO PA input"]
pub mod r32_pa_pin {
#[doc = "Register `R32_PA_PIN` reader"]
pub type R = crate::R<R32PaPinSpec>;
#[doc = "Field `R8_PA_PIN_0` reader - GPIO PA input byte 0"]
pub type R8PaPin0R = crate::FieldReader;
#[doc = "Field `R8_PA_PIN_1` reader - GPIO PA input byte 1"]
pub type R8PaPin1R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - GPIO PA input byte 0"]
#[inline(always)]
pub fn r8_pa_pin_0(&self) -> R8PaPin0R {
R8PaPin0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - GPIO PA input byte 1"]
#[inline(always)]
pub fn r8_pa_pin_1(&self) -> R8PaPin1R {
R8PaPin1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
#[doc = "RO, GPIO PA input\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pin::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaPinSpec;
impl crate::RegisterSpec for R32PaPinSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_pin::R`](R) reader structure"]
impl crate::Readable for R32PaPinSpec {}
#[doc = "`reset()` method sets R32_PA_PIN to value 0"]
impl crate::Resettable for R32PaPinSpec {}
}
#[doc = "R32_PA_OUT (rw) register accessor: RW, GPIO PA output\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_out`] module"]
#[doc(alias = "R32_PA_OUT")]
pub type R32PaOut = crate::Reg<r32_pa_out::R32PaOutSpec>;
#[doc = "RW, GPIO PA output"]
pub mod r32_pa_out {
#[doc = "Register `R32_PA_OUT` reader"]
pub type R = crate::R<R32PaOutSpec>;
#[doc = "Register `R32_PA_OUT` writer"]
pub type W = crate::W<R32PaOutSpec>;
#[doc = "Field `R8_PA_OUT_0` reader - GPIO PA output byte 0"]
pub type R8PaOut0R = crate::FieldReader;
#[doc = "Field `R8_PA_OUT_0` writer - GPIO PA output byte 0"]
pub type R8PaOut0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_OUT_1` reader - GPIO PA output byte 1"]
pub type R8PaOut1R = crate::FieldReader;
#[doc = "Field `R8_PA_OUT_1` writer - GPIO PA output byte 1"]
pub type R8PaOut1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - GPIO PA output byte 0"]
#[inline(always)]
pub fn r8_pa_out_0(&self) -> R8PaOut0R {
R8PaOut0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - GPIO PA output byte 1"]
#[inline(always)]
pub fn r8_pa_out_1(&self) -> R8PaOut1R {
R8PaOut1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - GPIO PA output byte 0"]
#[inline(always)]
pub fn r8_pa_out_0(&mut self) -> R8PaOut0W<R32PaOutSpec> {
R8PaOut0W::new(self, 0)
}
#[doc = "Bits 8:15 - GPIO PA output byte 1"]
#[inline(always)]
pub fn r8_pa_out_1(&mut self) -> R8PaOut1W<R32PaOutSpec> {
R8PaOut1W::new(self, 8)
}
}
#[doc = "RW, GPIO PA output\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaOutSpec;
impl crate::RegisterSpec for R32PaOutSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_out::R`](R) reader structure"]
impl crate::Readable for R32PaOutSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pa_out::W`](W) writer structure"]
impl crate::Writable for R32PaOutSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_OUT to value 0"]
impl crate::Resettable for R32PaOutSpec {}
}
#[doc = "R32_PA_CLR (w) register accessor: WZ, GPIO PA clear output: 0=keep, 1=clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_clr`] module"]
#[doc(alias = "R32_PA_CLR")]
pub type R32PaClr = crate::Reg<r32_pa_clr::R32PaClrSpec>;
#[doc = "WZ, GPIO PA clear output: 0=keep, 1=clear"]
pub mod r32_pa_clr {
#[doc = "Register `R32_PA_CLR` writer"]
pub type W = crate::W<R32PaClrSpec>;
#[doc = "Field `R8_PA_CLR_0` writer - GPIO PA clear output byte 0"]
pub type R8PaClr0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_CLR_1` writer - GPIO PA clear output byte 1"]
pub type R8PaClr1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl W {
#[doc = "Bits 0:7 - GPIO PA clear output byte 0"]
#[inline(always)]
pub fn r8_pa_clr_0(&mut self) -> R8PaClr0W<R32PaClrSpec> {
R8PaClr0W::new(self, 0)
}
#[doc = "Bits 8:15 - GPIO PA clear output byte 1"]
#[inline(always)]
pub fn r8_pa_clr_1(&mut self) -> R8PaClr1W<R32PaClrSpec> {
R8PaClr1W::new(self, 8)
}
}
#[doc = "WZ, GPIO PA clear output: 0=keep, 1=clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaClrSpec;
impl crate::RegisterSpec for R32PaClrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pa_clr::W`](W) writer structure"]
impl crate::Writable for R32PaClrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_CLR to value 0"]
impl crate::Resettable for R32PaClrSpec {}
}
#[doc = "R32_PA_PU (rw) register accessor: RW, GPIO PA pullup resistance enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pu::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_pu::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_pu`] module"]
#[doc(alias = "R32_PA_PU")]
pub type R32PaPu = crate::Reg<r32_pa_pu::R32PaPuSpec>;
#[doc = "RW, GPIO PA pullup resistance enable"]
pub mod r32_pa_pu {
#[doc = "Register `R32_PA_PU` reader"]
pub type R = crate::R<R32PaPuSpec>;
#[doc = "Register `R32_PA_PU` writer"]
pub type W = crate::W<R32PaPuSpec>;
#[doc = "Field `R8_PA_PU_0` reader - GPIO PA pullup resistance enable byte 0"]
pub type R8PaPu0R = crate::FieldReader;
#[doc = "Field `R8_PA_PU_0` writer - GPIO PA pullup resistance enable byte 0"]
pub type R8PaPu0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_PU_1` reader - GPIO PA pullup resistance enable byte 0"]
pub type R8PaPu1R = crate::FieldReader;
#[doc = "Field `R8_PA_PU_1` writer - GPIO PA pullup resistance enable byte 0"]
pub type R8PaPu1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - GPIO PA pullup resistance enable byte 0"]
#[inline(always)]
pub fn r8_pa_pu_0(&self) -> R8PaPu0R {
R8PaPu0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - GPIO PA pullup resistance enable byte 0"]
#[inline(always)]
pub fn r8_pa_pu_1(&self) -> R8PaPu1R {
R8PaPu1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - GPIO PA pullup resistance enable byte 0"]
#[inline(always)]
pub fn r8_pa_pu_0(&mut self) -> R8PaPu0W<R32PaPuSpec> {
R8PaPu0W::new(self, 0)
}
#[doc = "Bits 8:15 - GPIO PA pullup resistance enable byte 0"]
#[inline(always)]
pub fn r8_pa_pu_1(&mut self) -> R8PaPu1W<R32PaPuSpec> {
R8PaPu1W::new(self, 8)
}
}
#[doc = "RW, GPIO PA pullup resistance enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pu::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_pu::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaPuSpec;
impl crate::RegisterSpec for R32PaPuSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_pu::R`](R) reader structure"]
impl crate::Readable for R32PaPuSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pa_pu::W`](W) writer structure"]
impl crate::Writable for R32PaPuSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_PU to value 0"]
impl crate::Resettable for R32PaPuSpec {}
}
#[doc = "R32_PA_PD_DRV (rw) register accessor: RW, PA pulldown for input or PA driving capability for output\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pd_drv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_pd_drv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_pd_drv`] module"]
#[doc(alias = "R32_PA_PD_DRV")]
pub type R32PaPdDrv = crate::Reg<r32_pa_pd_drv::R32PaPdDrvSpec>;
#[doc = "RW, PA pulldown for input or PA driving capability for output"]
pub mod r32_pa_pd_drv {
#[doc = "Register `R32_PA_PD_DRV` reader"]
pub type R = crate::R<R32PaPdDrvSpec>;
#[doc = "Register `R32_PA_PD_DRV` writer"]
pub type W = crate::W<R32PaPdDrvSpec>;
#[doc = "Field `R8_PA_PD_DRV_0` reader - PA pulldown for input or PA driving capability for output byte 0"]
pub type R8PaPdDrv0R = crate::FieldReader;
#[doc = "Field `R8_PA_PD_DRV_0` writer - PA pulldown for input or PA driving capability for output byte 0"]
pub type R8PaPdDrv0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_PD_DRV_1` reader - PA pulldown for input or PA driving capability for output byte 1"]
pub type R8PaPdDrv1R = crate::FieldReader;
#[doc = "Field `R8_PA_PD_DRV_1` writer - PA pulldown for input or PA driving capability for output byte 1"]
pub type R8PaPdDrv1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - PA pulldown for input or PA driving capability for output byte 0"]
#[inline(always)]
pub fn r8_pa_pd_drv_0(&self) -> R8PaPdDrv0R {
R8PaPdDrv0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - PA pulldown for input or PA driving capability for output byte 1"]
#[inline(always)]
pub fn r8_pa_pd_drv_1(&self) -> R8PaPdDrv1R {
R8PaPdDrv1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - PA pulldown for input or PA driving capability for output byte 0"]
#[inline(always)]
pub fn r8_pa_pd_drv_0(&mut self) -> R8PaPdDrv0W<R32PaPdDrvSpec> {
R8PaPdDrv0W::new(self, 0)
}
#[doc = "Bits 8:15 - PA pulldown for input or PA driving capability for output byte 1"]
#[inline(always)]
pub fn r8_pa_pd_drv_1(&mut self) -> R8PaPdDrv1W<R32PaPdDrvSpec> {
R8PaPdDrv1W::new(self, 8)
}
}
#[doc = "RW, PA pulldown for input or PA driving capability for output\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_pd_drv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_pd_drv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaPdDrvSpec;
impl crate::RegisterSpec for R32PaPdDrvSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_pd_drv::R`](R) reader structure"]
impl crate::Readable for R32PaPdDrvSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pa_pd_drv::W`](W) writer structure"]
impl crate::Writable for R32PaPdDrvSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_PD_DRV to value 0"]
impl crate::Resettable for R32PaPdDrvSpec {}
}
#[doc = "R32_PA_SET (rw) register accessor: RW, PA port output set register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pa_set`] module"]
#[doc(alias = "R32_PA_SET")]
pub type R32PaSet = crate::Reg<r32_pa_set::R32PaSetSpec>;
#[doc = "RW, PA port output set register"]
pub mod r32_pa_set {
#[doc = "Register `R32_PA_SET` reader"]
pub type R = crate::R<R32PaSetSpec>;
#[doc = "Register `R32_PA_SET` writer"]
pub type W = crate::W<R32PaSetSpec>;
#[doc = "Field `R8_PA_SET_0` reader - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
pub type R8PaSet0R = crate::FieldReader;
#[doc = "Field `R8_PA_SET_0` writer - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
pub type R8PaSet0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PA_SET_1` reader - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
pub type R8PaSet1R = crate::FieldReader;
#[doc = "Field `R8_PA_SET_1` writer - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
pub type R8PaSet1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
#[inline(always)]
pub fn r8_pa_set_0(&self) -> R8PaSet0R {
R8PaSet0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
#[inline(always)]
pub fn r8_pa_set_1(&self) -> R8PaSet1R {
R8PaSet1R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
#[inline(always)]
pub fn r8_pa_set_0(&mut self) -> R8PaSet0W<R32PaSetSpec> {
R8PaSet0W::new(self, 0)
}
#[doc = "Bits 8:15 - When the corresponding bit of the set register R3_2PA_SET is 0, the output of the PA pin remains unchanged; When it is 1, the PA pin outputs a high level"]
#[inline(always)]
pub fn r8_pa_set_1(&mut self) -> R8PaSet1W<R32PaSetSpec> {
R8PaSet1W::new(self, 8)
}
}
#[doc = "RW, PA port output set register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pa_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pa_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PaSetSpec;
impl crate::RegisterSpec for R32PaSetSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pa_set::R`](R) reader structure"]
impl crate::Readable for R32PaSetSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pa_set::W`](W) writer structure"]
impl crate::Writable for R32PaSetSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PA_SET to value 0"]
impl crate::Resettable for R32PaSetSpec {}
}
}
#[doc = "Timer register"]
pub type Tmr = crate::Periph<tmr::RegisterBlock, 0x4000_2400>;
impl core::fmt::Debug for Tmr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tmr").finish()
}
}
#[doc = "Timer register"]
pub mod tmr {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r8_tmr_ctrl_mod: R8TmrCtrlMod,
r8_tmr_ctrl_dma: R8TmrCtrlDma,
r8_tmr_inter_en: R8TmrInterEn,
_reserved3: [u8; 0x03],
r8_tmr_int_flag: R8TmrIntFlag,
r8_tmr_fifo_count: R8TmrFifoCount,
r32_tmr_count: R32TmrCount,
r32_tmr_cnt_end: R32TmrCntEnd,
r32_tmr_fifo: R32TmrFifo,
r32_tmr_dma_now: R32TmrDmaNow,
r32_tmr_dma_beg: R32TmrDmaBeg,
r32_tmr_dma_end: R32TmrDmaEnd,
r8_enc_reg_ctrl: R8EncRegCtrl,
r8_enc_inter_en: R8EncInterEn,
r8_enc_int_flag: R8EncIntFlag,
_reserved14: [u8; 0x01],
r32_enc_reg_cend: R32EncRegCend,
r32_enc_reg_ccnt: R32EncRegCcnt,
}
impl RegisterBlock {
#[doc = "0x00 - RW, TMR mode control"]
#[inline(always)]
pub const fn r8_tmr_ctrl_mod(&self) -> &R8TmrCtrlMod {
&self.r8_tmr_ctrl_mod
}
#[doc = "0x01 - RO/WO, DMA control register"]
#[inline(always)]
pub const fn r8_tmr_ctrl_dma(&self) -> &R8TmrCtrlDma {
&self.r8_tmr_ctrl_dma
}
#[doc = "0x02 - RW, TMR interrupt enable"]
#[inline(always)]
pub const fn r8_tmr_inter_en(&self) -> &R8TmrInterEn {
&self.r8_tmr_inter_en
}
#[doc = "0x06 - RW1, TMR interrupt flag"]
#[inline(always)]
pub const fn r8_tmr_int_flag(&self) -> &R8TmrIntFlag {
&self.r8_tmr_int_flag
}
#[doc = "0x07 - RO, TMR FIFO count status"]
#[inline(always)]
pub const fn r8_tmr_fifo_count(&self) -> &R8TmrFifoCount {
&self.r8_tmr_fifo_count
}
#[doc = "0x08 - RO, TMR current count"]
#[inline(always)]
pub const fn r32_tmr_count(&self) -> &R32TmrCount {
&self.r32_tmr_count
}
#[doc = "0x0c - RW, TMR end count value, only low 26 bit"]
#[inline(always)]
pub const fn r32_tmr_cnt_end(&self) -> &R32TmrCntEnd {
&self.r32_tmr_cnt_end
}
#[doc = "0x10 - RO/WO, TMR FIFO register, only low 26 bit"]
#[inline(always)]
pub const fn r32_tmr_fifo(&self) -> &R32TmrFifo {
&self.r32_tmr_fifo
}
#[doc = "0x14 - RO, DMA current buffer address"]
#[inline(always)]
pub const fn r32_tmr_dma_now(&self) -> &R32TmrDmaNow {
&self.r32_tmr_dma_now
}
#[doc = "0x18 - RW, DMA start buffer address"]
#[inline(always)]
pub const fn r32_tmr_dma_beg(&self) -> &R32TmrDmaBeg {
&self.r32_tmr_dma_beg
}
#[doc = "0x1c - RW, DMA end buffer address"]
#[inline(always)]
pub const fn r32_tmr_dma_end(&self) -> &R32TmrDmaEnd {
&self.r32_tmr_dma_end
}
#[doc = "0x20 - RW, Encoder mode control register"]
#[inline(always)]
pub const fn r8_enc_reg_ctrl(&self) -> &R8EncRegCtrl {
&self.r8_enc_reg_ctrl
}
#[doc = "0x21 - RW, Encoder mode interrupt enable register"]
#[inline(always)]
pub const fn r8_enc_inter_en(&self) -> &R8EncInterEn {
&self.r8_enc_inter_en
}
#[doc = "0x22 - RW, Encoder mode interrupt flag register"]
#[inline(always)]
pub const fn r8_enc_int_flag(&self) -> &R8EncIntFlag {
&self.r8_enc_int_flag
}
#[doc = "0x24 - RW, Encoder mode final value configuration register"]
#[inline(always)]
pub const fn r32_enc_reg_cend(&self) -> &R32EncRegCend {
&self.r32_enc_reg_cend
}
#[doc = "0x28 - RW, Encoder mode current value configuration register"]
#[inline(always)]
pub const fn r32_enc_reg_ccnt(&self) -> &R32EncRegCcnt {
&self.r32_enc_reg_ccnt
}
}
#[doc = "R8_TMR_CTRL_MOD (rw) register accessor: RW, TMR mode control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_ctrl_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_ctrl_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_tmr_ctrl_mod`] module"]
#[doc(alias = "R8_TMR_CTRL_MOD")]
pub type R8TmrCtrlMod = crate::Reg<r8_tmr_ctrl_mod::R8TmrCtrlModSpec>;
#[doc = "RW, TMR mode control"]
pub mod r8_tmr_ctrl_mod {
#[doc = "Register `R8_TMR_CTRL_MOD` reader"]
pub type R = crate::R<R8TmrCtrlModSpec>;
#[doc = "Register `R8_TMR_CTRL_MOD` writer"]
pub type W = crate::W<R8TmrCtrlModSpec>;
#[doc = "Field `RB_TMR_MODE_IN` reader - RW, timer in mode: 0=timer/PWM, 1=capture/count"]
pub type RbTmrModeInR = crate::BitReader;
#[doc = "Field `RB_TMR_MODE_IN` writer - RW, timer in mode: 0=timer/PWM, 1=capture/count"]
pub type RbTmrModeInW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_ALL_CLEAR` reader - RW, force clear timer FIFO and count"]
pub type RbTmrAllClearR = crate::BitReader;
#[doc = "Field `RB_TMR_ALL_CLEAR` writer - RW, force clear timer FIFO and count"]
pub type RbTmrAllClearW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_COUNT_EN` reader - RW, timer count enable"]
pub type RbTmrCountEnR = crate::BitReader;
#[doc = "Field `RB_TMR_COUNT_EN` writer - RW, timer count enable"]
pub type RbTmrCountEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_OUT_EN` reader - RW, timer output enable"]
pub type RbTmrOutEnR = crate::BitReader;
#[doc = "Field `RB_TMR_OUT_EN` writer - RW, timer output enable"]
pub type RbTmrOutEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT` reader - RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action;RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count"]
pub type RbTmrOutPolarrbTmrCapCountR = crate::BitReader;
#[doc = "Field `RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT` writer - RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action;RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count"]
pub type RbTmrOutPolarrbTmrCapCountW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE` reader - RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16;RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise"]
pub type RbTmrPwmRepeatrbTmrCapEdgeR = crate::FieldReader;
#[doc = "Field `RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE` writer - RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16;RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise"]
pub type RbTmrPwmRepeatrbTmrCapEdgeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bit 0 - RW, timer in mode: 0=timer/PWM, 1=capture/count"]
#[inline(always)]
pub fn rb_tmr_mode_in(&self) -> RbTmrModeInR {
RbTmrModeInR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, force clear timer FIFO and count"]
#[inline(always)]
pub fn rb_tmr_all_clear(&self) -> RbTmrAllClearR {
RbTmrAllClearR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, timer count enable"]
#[inline(always)]
pub fn rb_tmr_count_en(&self) -> RbTmrCountEnR {
RbTmrCountEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, timer output enable"]
#[inline(always)]
pub fn rb_tmr_out_en(&self) -> RbTmrOutEnR {
RbTmrOutEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action;RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count"]
#[inline(always)]
pub fn rb_tmr_out_polarrb_tmr_cap_count(&self) -> RbTmrOutPolarrbTmrCapCountR {
RbTmrOutPolarrbTmrCapCountR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 6:7 - RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16;RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise"]
#[inline(always)]
pub fn rb_tmr_pwm_repeatrb_tmr_cap_edge(&self) -> RbTmrPwmRepeatrbTmrCapEdgeR {
RbTmrPwmRepeatrbTmrCapEdgeR::new((self.bits >> 6) & 3)
}
}
impl W {
#[doc = "Bit 0 - RW, timer in mode: 0=timer/PWM, 1=capture/count"]
#[inline(always)]
pub fn rb_tmr_mode_in(&mut self) -> RbTmrModeInW<R8TmrCtrlModSpec> {
RbTmrModeInW::new(self, 0)
}
#[doc = "Bit 1 - RW, force clear timer FIFO and count"]
#[inline(always)]
pub fn rb_tmr_all_clear(&mut self) -> RbTmrAllClearW<R8TmrCtrlModSpec> {
RbTmrAllClearW::new(self, 1)
}
#[doc = "Bit 2 - RW, timer count enable"]
#[inline(always)]
pub fn rb_tmr_count_en(&mut self) -> RbTmrCountEnW<R8TmrCtrlModSpec> {
RbTmrCountEnW::new(self, 2)
}
#[doc = "Bit 3 - RW, timer output enable"]
#[inline(always)]
pub fn rb_tmr_out_en(&mut self) -> RbTmrOutEnW<R8TmrCtrlModSpec> {
RbTmrOutEnW::new(self, 3)
}
#[doc = "Bit 4 - RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action;RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count"]
#[inline(always)]
pub fn rb_tmr_out_polarrb_tmr_cap_count(
&mut self,
) -> RbTmrOutPolarrbTmrCapCountW<R8TmrCtrlModSpec> {
RbTmrOutPolarrbTmrCapCountW::new(self, 4)
}
#[doc = "Bits 6:7 - RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16;RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise"]
#[inline(always)]
pub fn rb_tmr_pwm_repeatrb_tmr_cap_edge(
&mut self,
) -> RbTmrPwmRepeatrbTmrCapEdgeW<R8TmrCtrlModSpec> {
RbTmrPwmRepeatrbTmrCapEdgeW::new(self, 6)
}
}
#[doc = "RW, TMR mode control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_ctrl_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_ctrl_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8TmrCtrlModSpec;
impl crate::RegisterSpec for R8TmrCtrlModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_tmr_ctrl_mod::R`](R) reader structure"]
impl crate::Readable for R8TmrCtrlModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_tmr_ctrl_mod::W`](W) writer structure"]
impl crate::Writable for R8TmrCtrlModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_TMR_CTRL_MOD to value 0x02"]
impl crate::Resettable for R8TmrCtrlModSpec {
const RESET_VALUE: u8 = 0x02;
}
}
#[doc = "R8_TMR_CTRL_DMA (rw) register accessor: RO/WO, DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_ctrl_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_ctrl_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_tmr_ctrl_dma`] module"]
#[doc(alias = "R8_TMR_CTRL_DMA")]
pub type R8TmrCtrlDma = crate::Reg<r8_tmr_ctrl_dma::R8TmrCtrlDmaSpec>;
#[doc = "RO/WO, DMA control register"]
pub mod r8_tmr_ctrl_dma {
#[doc = "Register `R8_TMR_CTRL_DMA` reader"]
pub type R = crate::R<R8TmrCtrlDmaSpec>;
#[doc = "Register `R8_TMR_CTRL_DMA` writer"]
pub type W = crate::W<R8TmrCtrlDmaSpec>;
#[doc = "Field `RB_TMR_DMA_ENABLE` reader - RW, DMA function enable bit"]
pub type RbTmrDmaEnableR = crate::BitReader;
#[doc = "Field `RB_TMR_DMA_ENABLE` writer - RW, DMA function enable bit"]
pub type RbTmrDmaEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_DMA_LOOP` reader - RW, Enable bit for DMA address loop function"]
pub type RbTmrDmaLoopR = crate::BitReader;
#[doc = "Field `RB_TMR_DMA_LOOP` writer - RW, Enable bit for DMA address loop function"]
pub type RbTmrDmaLoopW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, DMA function enable bit"]
#[inline(always)]
pub fn rb_tmr_dma_enable(&self) -> RbTmrDmaEnableR {
RbTmrDmaEnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - RW, Enable bit for DMA address loop function"]
#[inline(always)]
pub fn rb_tmr_dma_loop(&self) -> RbTmrDmaLoopR {
RbTmrDmaLoopR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, DMA function enable bit"]
#[inline(always)]
pub fn rb_tmr_dma_enable(&mut self) -> RbTmrDmaEnableW<R8TmrCtrlDmaSpec> {
RbTmrDmaEnableW::new(self, 0)
}
#[doc = "Bit 2 - RW, Enable bit for DMA address loop function"]
#[inline(always)]
pub fn rb_tmr_dma_loop(&mut self) -> RbTmrDmaLoopW<R8TmrCtrlDmaSpec> {
RbTmrDmaLoopW::new(self, 2)
}
}
#[doc = "RO/WO, DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_ctrl_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_ctrl_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8TmrCtrlDmaSpec;
impl crate::RegisterSpec for R8TmrCtrlDmaSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_tmr_ctrl_dma::R`](R) reader structure"]
impl crate::Readable for R8TmrCtrlDmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_tmr_ctrl_dma::W`](W) writer structure"]
impl crate::Writable for R8TmrCtrlDmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_TMR_CTRL_DMA to value 0"]
impl crate::Resettable for R8TmrCtrlDmaSpec {}
}
#[doc = "R8_TMR_INTER_EN (rw) register accessor: RW, TMR interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_inter_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_inter_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_tmr_inter_en`] module"]
#[doc(alias = "R8_TMR_INTER_EN")]
pub type R8TmrInterEn = crate::Reg<r8_tmr_inter_en::R8TmrInterEnSpec>;
#[doc = "RW, TMR interrupt enable"]
pub mod r8_tmr_inter_en {
#[doc = "Register `R8_TMR_INTER_EN` reader"]
pub type R = crate::R<R8TmrInterEnSpec>;
#[doc = "Register `R8_TMR_INTER_EN` writer"]
pub type W = crate::W<R8TmrInterEnSpec>;
#[doc = "Field `RB_TMR_IE_CYC_END` reader - RW, enable interrupt for timer capture count timeout or PWM cycle end"]
pub type RbTmrIeCycEndR = crate::BitReader;
#[doc = "Field `RB_TMR_IE_CYC_END` writer - RW, enable interrupt for timer capture count timeout or PWM cycle end"]
pub type RbTmrIeCycEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IE_DATA_ACT` reader - RW, enable interrupt for timer capture input action or PWM trigger"]
pub type RbTmrIeDataActR = crate::BitReader;
#[doc = "Field `RB_TMR_IE_DATA_ACT` writer - RW, enable interrupt for timer capture input action or PWM trigger"]
pub type RbTmrIeDataActW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IE_FIFO_HF` reader - RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3)"]
pub type RbTmrIeFifoHfR = crate::BitReader;
#[doc = "Field `RB_TMR_IE_FIFO_HF` writer - RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3)"]
pub type RbTmrIeFifoHfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IE_DMA_END` reader - RW, enable interrupt for timer1/2 DMA completion"]
pub type RbTmrIeDmaEndR = crate::BitReader;
#[doc = "Field `RB_TMR_IE_DMA_END` writer - RW, enable interrupt for timer1/2 DMA completion"]
pub type RbTmrIeDmaEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IE_FIFO_OV` reader - RW, enable interrupt for timer FIFO overflow"]
pub type RbTmrIeFifoOvR = crate::BitReader;
#[doc = "Field `RB_TMR_IE_FIFO_OV` writer - RW, enable interrupt for timer FIFO overflow"]
pub type RbTmrIeFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, enable interrupt for timer capture count timeout or PWM cycle end"]
#[inline(always)]
pub fn rb_tmr_ie_cyc_end(&self) -> RbTmrIeCycEndR {
RbTmrIeCycEndR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, enable interrupt for timer capture input action or PWM trigger"]
#[inline(always)]
pub fn rb_tmr_ie_data_act(&self) -> RbTmrIeDataActR {
RbTmrIeDataActR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3)"]
#[inline(always)]
pub fn rb_tmr_ie_fifo_hf(&self) -> RbTmrIeFifoHfR {
RbTmrIeFifoHfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, enable interrupt for timer1/2 DMA completion"]
#[inline(always)]
pub fn rb_tmr_ie_dma_end(&self) -> RbTmrIeDmaEndR {
RbTmrIeDmaEndR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, enable interrupt for timer FIFO overflow"]
#[inline(always)]
pub fn rb_tmr_ie_fifo_ov(&self) -> RbTmrIeFifoOvR {
RbTmrIeFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, enable interrupt for timer capture count timeout or PWM cycle end"]
#[inline(always)]
pub fn rb_tmr_ie_cyc_end(&mut self) -> RbTmrIeCycEndW<R8TmrInterEnSpec> {
RbTmrIeCycEndW::new(self, 0)
}
#[doc = "Bit 1 - RW, enable interrupt for timer capture input action or PWM trigger"]
#[inline(always)]
pub fn rb_tmr_ie_data_act(&mut self) -> RbTmrIeDataActW<R8TmrInterEnSpec> {
RbTmrIeDataActW::new(self, 1)
}
#[doc = "Bit 2 - RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3)"]
#[inline(always)]
pub fn rb_tmr_ie_fifo_hf(&mut self) -> RbTmrIeFifoHfW<R8TmrInterEnSpec> {
RbTmrIeFifoHfW::new(self, 2)
}
#[doc = "Bit 3 - RW, enable interrupt for timer1/2 DMA completion"]
#[inline(always)]
pub fn rb_tmr_ie_dma_end(&mut self) -> RbTmrIeDmaEndW<R8TmrInterEnSpec> {
RbTmrIeDmaEndW::new(self, 3)
}
#[doc = "Bit 4 - RW, enable interrupt for timer FIFO overflow"]
#[inline(always)]
pub fn rb_tmr_ie_fifo_ov(&mut self) -> RbTmrIeFifoOvW<R8TmrInterEnSpec> {
RbTmrIeFifoOvW::new(self, 4)
}
}
#[doc = "RW, TMR interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_inter_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_inter_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8TmrInterEnSpec;
impl crate::RegisterSpec for R8TmrInterEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_tmr_inter_en::R`](R) reader structure"]
impl crate::Readable for R8TmrInterEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_tmr_inter_en::W`](W) writer structure"]
impl crate::Writable for R8TmrInterEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_TMR_INTER_EN to value 0"]
impl crate::Resettable for R8TmrInterEnSpec {}
}
#[doc = "R8_TMR_INT_FLAG (rw) register accessor: RW1, TMR interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_int_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_int_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_tmr_int_flag`] module"]
#[doc(alias = "R8_TMR_INT_FLAG")]
pub type R8TmrIntFlag = crate::Reg<r8_tmr_int_flag::R8TmrIntFlagSpec>;
#[doc = "RW1, TMR interrupt flag"]
pub mod r8_tmr_int_flag {
#[doc = "Register `R8_TMR_INT_FLAG` reader"]
pub type R = crate::R<R8TmrIntFlagSpec>;
#[doc = "Register `R8_TMR_INT_FLAG` writer"]
pub type W = crate::W<R8TmrIntFlagSpec>;
#[doc = "Field `RB_TMR_IF_CYC_END` reader - RW1, interrupt flag for timer capture count timeout or PWM cycle end"]
pub type RbTmrIfCycEndR = crate::BitReader;
#[doc = "Field `RB_TMR_IF_CYC_END` writer - RW1, interrupt flag for timer capture count timeout or PWM cycle end"]
pub type RbTmrIfCycEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IF_DATA_ACT` reader - RW1, interrupt flag for timer capture input action or PWM trigger"]
pub type RbTmrIfDataActR = crate::BitReader;
#[doc = "Field `RB_TMR_IF_DATA_ACT` writer - RW1, interrupt flag for timer capture input action or PWM trigger"]
pub type RbTmrIfDataActW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IF_FIFO_HF` reader - RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3"]
pub type RbTmrIfFifoHfR = crate::BitReader;
#[doc = "Field `RB_TMR_IF_FIFO_HF` writer - RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3"]
pub type RbTmrIfFifoHfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IF_DMA_END` reader - RW1, interrupt flag for timer1/2 DMA completion"]
pub type RbTmrIfDmaEndR = crate::BitReader;
#[doc = "Field `RB_TMR_IF_DMA_END` writer - RW1, interrupt flag for timer1/2 DMA completion"]
pub type RbTmrIfDmaEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_TMR_IF_FIFO_OV` reader - RW1, interrupt flag for timer FIFO overflow"]
pub type RbTmrIfFifoOvR = crate::BitReader;
#[doc = "Field `RB_TMR_IF_FIFO_OV` writer - RW1, interrupt flag for timer FIFO overflow"]
pub type RbTmrIfFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW1, interrupt flag for timer capture count timeout or PWM cycle end"]
#[inline(always)]
pub fn rb_tmr_if_cyc_end(&self) -> RbTmrIfCycEndR {
RbTmrIfCycEndR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW1, interrupt flag for timer capture input action or PWM trigger"]
#[inline(always)]
pub fn rb_tmr_if_data_act(&self) -> RbTmrIfDataActR {
RbTmrIfDataActR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3"]
#[inline(always)]
pub fn rb_tmr_if_fifo_hf(&self) -> RbTmrIfFifoHfR {
RbTmrIfFifoHfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW1, interrupt flag for timer1/2 DMA completion"]
#[inline(always)]
pub fn rb_tmr_if_dma_end(&self) -> RbTmrIfDmaEndR {
RbTmrIfDmaEndR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW1, interrupt flag for timer FIFO overflow"]
#[inline(always)]
pub fn rb_tmr_if_fifo_ov(&self) -> RbTmrIfFifoOvR {
RbTmrIfFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW1, interrupt flag for timer capture count timeout or PWM cycle end"]
#[inline(always)]
pub fn rb_tmr_if_cyc_end(&mut self) -> RbTmrIfCycEndW<R8TmrIntFlagSpec> {
RbTmrIfCycEndW::new(self, 0)
}
#[doc = "Bit 1 - RW1, interrupt flag for timer capture input action or PWM trigger"]
#[inline(always)]
pub fn rb_tmr_if_data_act(&mut self) -> RbTmrIfDataActW<R8TmrIntFlagSpec> {
RbTmrIfDataActW::new(self, 1)
}
#[doc = "Bit 2 - RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3"]
#[inline(always)]
pub fn rb_tmr_if_fifo_hf(&mut self) -> RbTmrIfFifoHfW<R8TmrIntFlagSpec> {
RbTmrIfFifoHfW::new(self, 2)
}
#[doc = "Bit 3 - RW1, interrupt flag for timer1/2 DMA completion"]
#[inline(always)]
pub fn rb_tmr_if_dma_end(&mut self) -> RbTmrIfDmaEndW<R8TmrIntFlagSpec> {
RbTmrIfDmaEndW::new(self, 3)
}
#[doc = "Bit 4 - RW1, interrupt flag for timer FIFO overflow"]
#[inline(always)]
pub fn rb_tmr_if_fifo_ov(&mut self) -> RbTmrIfFifoOvW<R8TmrIntFlagSpec> {
RbTmrIfFifoOvW::new(self, 4)
}
}
#[doc = "RW1, TMR interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_int_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_tmr_int_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8TmrIntFlagSpec;
impl crate::RegisterSpec for R8TmrIntFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_tmr_int_flag::R`](R) reader structure"]
impl crate::Readable for R8TmrIntFlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_tmr_int_flag::W`](W) writer structure"]
impl crate::Writable for R8TmrIntFlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_TMR_INT_FLAG to value 0"]
impl crate::Resettable for R8TmrIntFlagSpec {}
}
#[doc = "R8_TMR_FIFO_COUNT (r) register accessor: RO, TMR FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_fifo_count::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_tmr_fifo_count`] module"]
#[doc(alias = "R8_TMR_FIFO_COUNT")]
pub type R8TmrFifoCount = crate::Reg<r8_tmr_fifo_count::R8TmrFifoCountSpec>;
#[doc = "RO, TMR FIFO count status"]
pub mod r8_tmr_fifo_count {
#[doc = "Register `R8_TMR_FIFO_COUNT` reader"]
pub type R = crate::R<R8TmrFifoCountSpec>;
#[doc = "Field `R8_TMR_FIFO_COUNT` reader - R0,TMR FIFO count status"]
pub type R8TmrFifoCountR = crate::FieldReader;
impl R {
#[doc = "Bits 0:3 - R0,TMR FIFO count status"]
#[inline(always)]
pub fn r8_tmr_fifo_count(&self) -> R8TmrFifoCountR {
R8TmrFifoCountR::new(self.bits & 0x0f)
}
}
#[doc = "RO, TMR FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_tmr_fifo_count::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8TmrFifoCountSpec;
impl crate::RegisterSpec for R8TmrFifoCountSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_tmr_fifo_count::R`](R) reader structure"]
impl crate::Readable for R8TmrFifoCountSpec {}
#[doc = "`reset()` method sets R8_TMR_FIFO_COUNT to value 0"]
impl crate::Resettable for R8TmrFifoCountSpec {}
}
#[doc = "R32_TMR_COUNT (r) register accessor: RO, TMR current count\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_count::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_count`] module"]
#[doc(alias = "R32_TMR_COUNT")]
pub type R32TmrCount = crate::Reg<r32_tmr_count::R32TmrCountSpec>;
#[doc = "RO, TMR current count"]
pub mod r32_tmr_count {
#[doc = "Register `R32_TMR_COUNT` reader"]
pub type R = crate::R<R32TmrCountSpec>;
#[doc = "Field `R32_TMR_COUNT` reader - RW1,TMR current count"]
pub type R32TmrCountR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:25 - RW1,TMR current count"]
#[inline(always)]
pub fn r32_tmr_count(&self) -> R32TmrCountR {
R32TmrCountR::new(self.bits & 0x03ff_ffff)
}
}
#[doc = "RO, TMR current count\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_count::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrCountSpec;
impl crate::RegisterSpec for R32TmrCountSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_count::R`](R) reader structure"]
impl crate::Readable for R32TmrCountSpec {}
#[doc = "`reset()` method sets R32_TMR_COUNT to value 0"]
impl crate::Resettable for R32TmrCountSpec {}
}
#[doc = "R32_TMR_CNT_END (rw) register accessor: RW, TMR end count value, only low 26 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_cnt_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_cnt_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_cnt_end`] module"]
#[doc(alias = "R32_TMR_CNT_END")]
pub type R32TmrCntEnd = crate::Reg<r32_tmr_cnt_end::R32TmrCntEndSpec>;
#[doc = "RW, TMR end count value, only low 26 bit"]
pub mod r32_tmr_cnt_end {
#[doc = "Register `R32_TMR_CNT_END` reader"]
pub type R = crate::R<R32TmrCntEndSpec>;
#[doc = "Register `R32_TMR_CNT_END` writer"]
pub type W = crate::W<R32TmrCntEndSpec>;
#[doc = "Field `R32_TMR_CNT_END` reader - RW1,TMR end count value"]
pub type R32TmrCntEndR = crate::FieldReader<u32>;
#[doc = "Field `R32_TMR_CNT_END` writer - RW1,TMR end count value"]
pub type R32TmrCntEndW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW1,TMR end count value"]
#[inline(always)]
pub fn r32_tmr_cnt_end(&self) -> R32TmrCntEndR {
R32TmrCntEndR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW1,TMR end count value"]
#[inline(always)]
pub fn r32_tmr_cnt_end(&mut self) -> R32TmrCntEndW<R32TmrCntEndSpec> {
R32TmrCntEndW::new(self, 0)
}
}
#[doc = "RW, TMR end count value, only low 26 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_cnt_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_cnt_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrCntEndSpec;
impl crate::RegisterSpec for R32TmrCntEndSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_cnt_end::R`](R) reader structure"]
impl crate::Readable for R32TmrCntEndSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_tmr_cnt_end::W`](W) writer structure"]
impl crate::Writable for R32TmrCntEndSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_TMR_CNT_END to value 0"]
impl crate::Resettable for R32TmrCntEndSpec {}
}
#[doc = "R32_TMR_FIFO (r) register accessor: RO/WO, TMR FIFO register, only low 26 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_fifo`] module"]
#[doc(alias = "R32_TMR_FIFO")]
pub type R32TmrFifo = crate::Reg<r32_tmr_fifo::R32TmrFifoSpec>;
#[doc = "RO/WO, TMR FIFO register, only low 26 bit"]
pub mod r32_tmr_fifo {
#[doc = "Register `R32_TMR_FIFO` reader"]
pub type R = crate::R<R32TmrFifoSpec>;
#[doc = "Field `R32_TMR_FIFO` reader - RW1,TMR FIFO register"]
pub type R32TmrFifoR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - RW1,TMR FIFO register"]
#[inline(always)]
pub fn r32_tmr_fifo(&self) -> R32TmrFifoR {
R32TmrFifoR::new(self.bits)
}
}
#[doc = "RO/WO, TMR FIFO register, only low 26 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrFifoSpec;
impl crate::RegisterSpec for R32TmrFifoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_fifo::R`](R) reader structure"]
impl crate::Readable for R32TmrFifoSpec {}
#[doc = "`reset()` method sets R32_TMR_FIFO to value 0"]
impl crate::Resettable for R32TmrFifoSpec {}
}
#[doc = "R32_TMR_DMA_NOW (r) register accessor: RO, DMA current buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_now::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_dma_now`] module"]
#[doc(alias = "R32_TMR_DMA_NOW")]
pub type R32TmrDmaNow = crate::Reg<r32_tmr_dma_now::R32TmrDmaNowSpec>;
#[doc = "RO, DMA current buffer address"]
pub mod r32_tmr_dma_now {
#[doc = "Register `R32_TMR_DMA_NOW` reader"]
pub type R = crate::R<R32TmrDmaNowSpec>;
#[doc = "Field `RB_TMR_DMA_NOW` reader - RW, DMA data buffer current address"]
pub type RbTmrDmaNowR = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 2:14 - RW, DMA data buffer current address"]
#[inline(always)]
pub fn rb_tmr_dma_now(&self) -> RbTmrDmaNowR {
RbTmrDmaNowR::new(((self.bits >> 2) & 0x1fff) as u16)
}
}
#[doc = "RO, DMA current buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_now::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrDmaNowSpec;
impl crate::RegisterSpec for R32TmrDmaNowSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_dma_now::R`](R) reader structure"]
impl crate::Readable for R32TmrDmaNowSpec {}
#[doc = "`reset()` method sets R32_TMR_DMA_NOW to value 0"]
impl crate::Resettable for R32TmrDmaNowSpec {}
}
#[doc = "R32_TMR_DMA_BEG (rw) register accessor: RW, DMA start buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_beg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_dma_beg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_dma_beg`] module"]
#[doc(alias = "R32_TMR_DMA_BEG")]
pub type R32TmrDmaBeg = crate::Reg<r32_tmr_dma_beg::R32TmrDmaBegSpec>;
#[doc = "RW, DMA start buffer address"]
pub mod r32_tmr_dma_beg {
#[doc = "Register `R32_TMR_DMA_BEG` reader"]
pub type R = crate::R<R32TmrDmaBegSpec>;
#[doc = "Register `R32_TMR_DMA_BEG` writer"]
pub type W = crate::W<R32TmrDmaBegSpec>;
#[doc = "Field `RB_TMR_DMA_BEG` reader - RW, The starting address of the DMA data buffer must be aligned with 4 bytes"]
pub type RbTmrDmaBegR = crate::FieldReader<u16>;
#[doc = "Field `RB_TMR_DMA_BEG` writer - RW, The starting address of the DMA data buffer must be aligned with 4 bytes"]
pub type RbTmrDmaBegW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bits 2:14 - RW, The starting address of the DMA data buffer must be aligned with 4 bytes"]
#[inline(always)]
pub fn rb_tmr_dma_beg(&self) -> RbTmrDmaBegR {
RbTmrDmaBegR::new(((self.bits >> 2) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bits 2:14 - RW, The starting address of the DMA data buffer must be aligned with 4 bytes"]
#[inline(always)]
pub fn rb_tmr_dma_beg(&mut self) -> RbTmrDmaBegW<R32TmrDmaBegSpec> {
RbTmrDmaBegW::new(self, 2)
}
}
#[doc = "RW, DMA start buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_beg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_dma_beg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrDmaBegSpec;
impl crate::RegisterSpec for R32TmrDmaBegSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_dma_beg::R`](R) reader structure"]
impl crate::Readable for R32TmrDmaBegSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_tmr_dma_beg::W`](W) writer structure"]
impl crate::Writable for R32TmrDmaBegSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_TMR_DMA_BEG to value 0"]
impl crate::Resettable for R32TmrDmaBegSpec {}
}
#[doc = "R32_TMR_DMA_END (rw) register accessor: RW, DMA end buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_dma_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_tmr_dma_end`] module"]
#[doc(alias = "R32_TMR_DMA_END")]
pub type R32TmrDmaEnd = crate::Reg<r32_tmr_dma_end::R32TmrDmaEndSpec>;
#[doc = "RW, DMA end buffer address"]
pub mod r32_tmr_dma_end {
#[doc = "Register `R32_TMR_DMA_END` reader"]
pub type R = crate::R<R32TmrDmaEndSpec>;
#[doc = "Register `R32_TMR_DMA_END` writer"]
pub type W = crate::W<R32TmrDmaEndSpec>;
#[doc = "Field `RB_TMR_DMA_END` reader - RW, DMA data buffer end address (excluding), the address must be aligned with 4 bytes"]
pub type RbTmrDmaEndR = crate::FieldReader<u16>;
#[doc = "Field `RB_TMR_DMA_END` writer - RW, DMA data buffer end address (excluding), the address must be aligned with 4 bytes"]
pub type RbTmrDmaEndW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bits 2:14 - RW, DMA data buffer end address (excluding), the address must be aligned with 4 bytes"]
#[inline(always)]
pub fn rb_tmr_dma_end(&self) -> RbTmrDmaEndR {
RbTmrDmaEndR::new(((self.bits >> 2) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bits 2:14 - RW, DMA data buffer end address (excluding), the address must be aligned with 4 bytes"]
#[inline(always)]
pub fn rb_tmr_dma_end(&mut self) -> RbTmrDmaEndW<R32TmrDmaEndSpec> {
RbTmrDmaEndW::new(self, 2)
}
}
#[doc = "RW, DMA end buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_tmr_dma_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_tmr_dma_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32TmrDmaEndSpec;
impl crate::RegisterSpec for R32TmrDmaEndSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_tmr_dma_end::R`](R) reader structure"]
impl crate::Readable for R32TmrDmaEndSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_tmr_dma_end::W`](W) writer structure"]
impl crate::Writable for R32TmrDmaEndSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_TMR_DMA_END to value 0"]
impl crate::Resettable for R32TmrDmaEndSpec {}
}
#[doc = "R8_ENC_REG_CTRL (rw) register accessor: RW, Encoder mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_reg_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_reg_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_enc_reg_ctrl`] module"]
#[doc(alias = "R8_ENC_REG_CTRL")]
pub type R8EncRegCtrl = crate::Reg<r8_enc_reg_ctrl::R8EncRegCtrlSpec>;
#[doc = "RW, Encoder mode control register"]
pub mod r8_enc_reg_ctrl {
#[doc = "Register `R8_ENC_REG_CTRL` reader"]
pub type R = crate::R<R8EncRegCtrlSpec>;
#[doc = "Register `R8_ENC_REG_CTRL` writer"]
pub type W = crate::W<R8EncRegCtrlSpec>;
#[doc = "Field `RB_START_ENC_EN` reader - RW, Enable encoder mode operation"]
pub type RbStartEncEnR = crate::BitReader;
#[doc = "Field `RB_START_ENC_EN` writer - RW, Enable encoder mode operation"]
pub type RbStartEncEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SMS_MODE` reader - RW, Encoder mode edge working mode"]
pub type RbSmsModeR = crate::FieldReader;
#[doc = "Field `RB_SMS_MODE` writer - RW, Encoder mode edge working mode"]
pub type RbSmsModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_RD_CLR_EN` reader - RW, Encoder mode reads count and resets to zero"]
pub type RbRdClrEnR = crate::BitReader;
#[doc = "Field `RB_RD_CLR_EN` writer - RW, Encoder mode reads count and resets to zero"]
pub type RbRdClrEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_ENC_DIR` reader - RO, Current direction of encoder"]
pub type RbEncDirR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RW, Enable encoder mode operation"]
#[inline(always)]
pub fn rb_start_enc_en(&self) -> RbStartEncEnR {
RbStartEncEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - RW, Encoder mode edge working mode"]
#[inline(always)]
pub fn rb_sms_mode(&self) -> RbSmsModeR {
RbSmsModeR::new((self.bits >> 1) & 3)
}
#[doc = "Bit 3 - RW, Encoder mode reads count and resets to zero"]
#[inline(always)]
pub fn rb_rd_clr_en(&self) -> RbRdClrEnR {
RbRdClrEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5 - RO, Current direction of encoder"]
#[inline(always)]
pub fn rb_enc_dir(&self) -> RbEncDirR {
RbEncDirR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Enable encoder mode operation"]
#[inline(always)]
pub fn rb_start_enc_en(&mut self) -> RbStartEncEnW<R8EncRegCtrlSpec> {
RbStartEncEnW::new(self, 0)
}
#[doc = "Bits 1:2 - RW, Encoder mode edge working mode"]
#[inline(always)]
pub fn rb_sms_mode(&mut self) -> RbSmsModeW<R8EncRegCtrlSpec> {
RbSmsModeW::new(self, 1)
}
#[doc = "Bit 3 - RW, Encoder mode reads count and resets to zero"]
#[inline(always)]
pub fn rb_rd_clr_en(&mut self) -> RbRdClrEnW<R8EncRegCtrlSpec> {
RbRdClrEnW::new(self, 3)
}
}
#[doc = "RW, Encoder mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_reg_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_reg_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8EncRegCtrlSpec;
impl crate::RegisterSpec for R8EncRegCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_enc_reg_ctrl::R`](R) reader structure"]
impl crate::Readable for R8EncRegCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_enc_reg_ctrl::W`](W) writer structure"]
impl crate::Writable for R8EncRegCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_ENC_REG_CTRL to value 0"]
impl crate::Resettable for R8EncRegCtrlSpec {}
}
#[doc = "R8_ENC_INTER_EN (rw) register accessor: RW, Encoder mode interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_inter_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_inter_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_enc_inter_en`] module"]
#[doc(alias = "R8_ENC_INTER_EN")]
pub type R8EncInterEn = crate::Reg<r8_enc_inter_en::R8EncInterEnSpec>;
#[doc = "RW, Encoder mode interrupt enable register"]
pub mod r8_enc_inter_en {
#[doc = "Register `R8_ENC_INTER_EN` reader"]
pub type R = crate::R<R8EncInterEnSpec>;
#[doc = "Register `R8_ENC_INTER_EN` writer"]
pub type W = crate::W<R8EncInterEnSpec>;
#[doc = "Field `RB_IE_DIR_INC` reader - RW, Encoder mode forward interrupt enable"]
pub type RbIeDirIncR = crate::BitReader;
#[doc = "Field `RB_IE_DIR_INC` writer - RW, Encoder mode forward interrupt enable"]
pub type RbIeDirIncW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_IE_DIR_DEC` reader - RW, Encoder mode backward interrupt enable"]
pub type RbIeDirDecR = crate::BitReader;
#[doc = "Field `RB_IE_DIR_DEC` writer - RW, Encoder mode backward interrupt enable"]
pub type RbIeDirDecW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Encoder mode forward interrupt enable"]
#[inline(always)]
pub fn rb_ie_dir_inc(&self) -> RbIeDirIncR {
RbIeDirIncR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Encoder mode backward interrupt enable"]
#[inline(always)]
pub fn rb_ie_dir_dec(&self) -> RbIeDirDecR {
RbIeDirDecR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Encoder mode forward interrupt enable"]
#[inline(always)]
pub fn rb_ie_dir_inc(&mut self) -> RbIeDirIncW<R8EncInterEnSpec> {
RbIeDirIncW::new(self, 0)
}
#[doc = "Bit 1 - RW, Encoder mode backward interrupt enable"]
#[inline(always)]
pub fn rb_ie_dir_dec(&mut self) -> RbIeDirDecW<R8EncInterEnSpec> {
RbIeDirDecW::new(self, 1)
}
}
#[doc = "RW, Encoder mode interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_inter_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_inter_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8EncInterEnSpec;
impl crate::RegisterSpec for R8EncInterEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_enc_inter_en::R`](R) reader structure"]
impl crate::Readable for R8EncInterEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_enc_inter_en::W`](W) writer structure"]
impl crate::Writable for R8EncInterEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_ENC_INTER_EN to value 0"]
impl crate::Resettable for R8EncInterEnSpec {}
}
#[doc = "R8_ENC_INT_FLAG (rw) register accessor: RW, Encoder mode interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_int_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_int_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_enc_int_flag`] module"]
#[doc(alias = "R8_ENC_INT_FLAG")]
pub type R8EncIntFlag = crate::Reg<r8_enc_int_flag::R8EncIntFlagSpec>;
#[doc = "RW, Encoder mode interrupt flag register"]
pub mod r8_enc_int_flag {
#[doc = "Register `R8_ENC_INT_FLAG` reader"]
pub type R = crate::R<R8EncIntFlagSpec>;
#[doc = "Register `R8_ENC_INT_FLAG` writer"]
pub type W = crate::W<R8EncIntFlagSpec>;
#[doc = "Field `RB_IF_DIR_INC` reader - RW, Encoder mode forward interrupt flag"]
pub type RbIfDirIncR = crate::BitReader;
#[doc = "Field `RB_IF_DIR_INC` writer - RW, Encoder mode forward interrupt flag"]
pub type RbIfDirIncW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_IF_DIR_DEC` reader - RW, Encoder mode backward interrupt flag"]
pub type RbIfDirDecR = crate::BitReader;
#[doc = "Field `RB_IF_DIR_DEC` writer - RW, Encoder mode backward interrupt flag"]
pub type RbIfDirDecW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Encoder mode forward interrupt flag"]
#[inline(always)]
pub fn rb_if_dir_inc(&self) -> RbIfDirIncR {
RbIfDirIncR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Encoder mode backward interrupt flag"]
#[inline(always)]
pub fn rb_if_dir_dec(&self) -> RbIfDirDecR {
RbIfDirDecR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Encoder mode forward interrupt flag"]
#[inline(always)]
pub fn rb_if_dir_inc(&mut self) -> RbIfDirIncW<R8EncIntFlagSpec> {
RbIfDirIncW::new(self, 0)
}
#[doc = "Bit 1 - RW, Encoder mode backward interrupt flag"]
#[inline(always)]
pub fn rb_if_dir_dec(&mut self) -> RbIfDirDecW<R8EncIntFlagSpec> {
RbIfDirDecW::new(self, 1)
}
}
#[doc = "RW, Encoder mode interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_enc_int_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_enc_int_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8EncIntFlagSpec;
impl crate::RegisterSpec for R8EncIntFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_enc_int_flag::R`](R) reader structure"]
impl crate::Readable for R8EncIntFlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_enc_int_flag::W`](W) writer structure"]
impl crate::Writable for R8EncIntFlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_ENC_INT_FLAG to value 0"]
impl crate::Resettable for R8EncIntFlagSpec {}
}
#[doc = "R32_ENC_REG_CEND (rw) register accessor: RW, Encoder mode final value configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_enc_reg_cend::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_enc_reg_cend::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_enc_reg_cend`] module"]
#[doc(alias = "R32_ENC_REG_CEND")]
pub type R32EncRegCend = crate::Reg<r32_enc_reg_cend::R32EncRegCendSpec>;
#[doc = "RW, Encoder mode final value configuration register"]
pub mod r32_enc_reg_cend {
#[doc = "Register `R32_ENC_REG_CEND` reader"]
pub type R = crate::R<R32EncRegCendSpec>;
#[doc = "Register `R32_ENC_REG_CEND` writer"]
pub type W = crate::W<R32EncRegCendSpec>;
#[doc = "Field `R32_ENC_REG_CEND` reader - RW, Preset encoder mode final value"]
pub type R32EncRegCendR = crate::FieldReader<u32>;
#[doc = "Field `R32_ENC_REG_CEND` writer - RW, Preset encoder mode final value"]
pub type R32EncRegCendW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, Preset encoder mode final value"]
#[inline(always)]
pub fn r32_enc_reg_cend(&self) -> R32EncRegCendR {
R32EncRegCendR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, Preset encoder mode final value"]
#[inline(always)]
pub fn r32_enc_reg_cend(&mut self) -> R32EncRegCendW<R32EncRegCendSpec> {
R32EncRegCendW::new(self, 0)
}
}
#[doc = "RW, Encoder mode final value configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_enc_reg_cend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_enc_reg_cend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32EncRegCendSpec;
impl crate::RegisterSpec for R32EncRegCendSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_enc_reg_cend::R`](R) reader structure"]
impl crate::Readable for R32EncRegCendSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_enc_reg_cend::W`](W) writer structure"]
impl crate::Writable for R32EncRegCendSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_ENC_REG_CEND to value 0"]
impl crate::Resettable for R32EncRegCendSpec {}
}
#[doc = "R32_ENC_REG_CCNT (r) register accessor: RW, Encoder mode current value configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_enc_reg_ccnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_enc_reg_ccnt`] module"]
#[doc(alias = "R32_ENC_REG_CCNT")]
pub type R32EncRegCcnt = crate::Reg<r32_enc_reg_ccnt::R32EncRegCcntSpec>;
#[doc = "RW, Encoder mode current value configuration register"]
pub mod r32_enc_reg_ccnt {
#[doc = "Register `R32_ENC_REG_CCNT` reader"]
pub type R = crate::R<R32EncRegCcntSpec>;
#[doc = "Field `R32_ENC_REG_CCNT` reader - RO, Current encoder mode value"]
pub type R32EncRegCcntR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - RO, Current encoder mode value"]
#[inline(always)]
pub fn r32_enc_reg_ccnt(&self) -> R32EncRegCcntR {
R32EncRegCcntR::new(self.bits)
}
}
#[doc = "RW, Encoder mode current value configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_enc_reg_ccnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32EncRegCcntSpec;
impl crate::RegisterSpec for R32EncRegCcntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_enc_reg_ccnt::R`](R) reader structure"]
impl crate::Readable for R32EncRegCcntSpec {}
#[doc = "`reset()` method sets R32_ENC_REG_CCNT to value 0"]
impl crate::Resettable for R32EncRegCcntSpec {}
}
}
#[doc = "UART register"]
pub type Uart = crate::Periph<uart::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for Uart {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart").finish()
}
}
#[doc = "UART register"]
pub mod uart {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r8_uart_mcr: R8UartMcr,
r8_uart_ier: R8UartIer,
r8_uart_fcr: R8UartFcr,
r8_uart_lcr: R8UartLcr,
r8_uart_iir: R8UartIir,
r8_uart_lsr: R8UartLsr,
_reserved6: [u8; 0x02],
_reserved_6_r8_uart: [u8; 0x01],
_reserved7: [u8; 0x01],
r8_uart_rfc: R8UartRfc,
r8_uart_tfc: R8UartTfc,
r16_uart_dl: R16UartDl,
r8_uart_div: R8UartDiv,
}
impl RegisterBlock {
#[doc = "0x00 - RW, UART modem control"]
#[inline(always)]
pub const fn r8_uart_mcr(&self) -> &R8UartMcr {
&self.r8_uart_mcr
}
#[doc = "0x01 - RW, UART interrupt enable"]
#[inline(always)]
pub const fn r8_uart_ier(&self) -> &R8UartIer {
&self.r8_uart_ier
}
#[doc = "0x02 - RW, UART FIFO control"]
#[inline(always)]
pub const fn r8_uart_fcr(&self) -> &R8UartFcr {
&self.r8_uart_fcr
}
#[doc = "0x03 - RW, UART line control"]
#[inline(always)]
pub const fn r8_uart_lcr(&self) -> &R8UartLcr {
&self.r8_uart_lcr
}
#[doc = "0x04 - RO, UART interrupt identification"]
#[inline(always)]
pub const fn r8_uart_iir(&self) -> &R8UartIir {
&self.r8_uart_iir
}
#[doc = "0x05 - RO, UART line status"]
#[inline(always)]
pub const fn r8_uart_lsr(&self) -> &R8UartLsr {
&self.r8_uart_lsr
}
#[doc = "0x08 - WO, UART transmitter holding, transmittal byte"]
#[inline(always)]
pub const fn r8_uart_thr(&self) -> &R8UartThr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).cast() }
}
#[doc = "0x08 - RO, UART receiver buffer, receiving byte"]
#[inline(always)]
pub const fn r8_uart_rbr(&self) -> &R8UartRbr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).cast() }
}
#[doc = "0x0a - RO, UART receiver FIFO count"]
#[inline(always)]
pub const fn r8_uart_rfc(&self) -> &R8UartRfc {
&self.r8_uart_rfc
}
#[doc = "0x0b - RO, UART transmitter FIFO count"]
#[inline(always)]
pub const fn r8_uart_tfc(&self) -> &R8UartTfc {
&self.r8_uart_tfc
}
#[doc = "0x0c - RW, UART divisor latch"]
#[inline(always)]
pub const fn r16_uart_dl(&self) -> &R16UartDl {
&self.r16_uart_dl
}
#[doc = "0x0e - RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
#[inline(always)]
pub const fn r8_uart_div(&self) -> &R8UartDiv {
&self.r8_uart_div
}
}
#[doc = "R8_UART_MCR (rw) register accessor: RW, UART modem control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_mcr`] module"]
#[doc(alias = "R8_UART_MCR")]
pub type R8UartMcr = crate::Reg<r8_uart_mcr::R8UartMcrSpec>;
#[doc = "RW, UART modem control"]
pub mod r8_uart_mcr {
#[doc = "Register `R8_UART_MCR` reader"]
pub type R = crate::R<R8UartMcrSpec>;
#[doc = "Register `R8_UART_MCR` writer"]
pub type W = crate::W<R8UartMcrSpec>;
#[doc = "Field `RB_MCR_OUT2/RB_MCR_INT_OE` reader - RW, UART control OUT2/UART interrupt output enable"]
pub type RbMcrOut2rbMcrIntOeR = crate::BitReader;
#[doc = "Field `RB_MCR_OUT2/RB_MCR_INT_OE` writer - RW, UART control OUT2/UART interrupt output enable"]
pub type RbMcrOut2rbMcrIntOeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 3 - RW, UART control OUT2/UART interrupt output enable"]
#[inline(always)]
pub fn rb_mcr_out2rb_mcr_int_oe(&self) -> RbMcrOut2rbMcrIntOeR {
RbMcrOut2rbMcrIntOeR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 3 - RW, UART control OUT2/UART interrupt output enable"]
#[inline(always)]
pub fn rb_mcr_out2rb_mcr_int_oe(&mut self) -> RbMcrOut2rbMcrIntOeW<R8UartMcrSpec> {
RbMcrOut2rbMcrIntOeW::new(self, 3)
}
}
#[doc = "RW, UART modem control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartMcrSpec;
impl crate::RegisterSpec for R8UartMcrSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_mcr::R`](R) reader structure"]
impl crate::Readable for R8UartMcrSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uart_mcr::W`](W) writer structure"]
impl crate::Writable for R8UartMcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_MCR to value 0"]
impl crate::Resettable for R8UartMcrSpec {}
}
#[doc = "R8_UART_IER (rw) register accessor: RW, UART interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_ier`] module"]
#[doc(alias = "R8_UART_IER")]
pub type R8UartIer = crate::Reg<r8_uart_ier::R8UartIerSpec>;
#[doc = "RW, UART interrupt enable"]
pub mod r8_uart_ier {
#[doc = "Register `R8_UART_IER` reader"]
pub type R = crate::R<R8UartIerSpec>;
#[doc = "Register `R8_UART_IER` writer"]
pub type W = crate::W<R8UartIerSpec>;
#[doc = "Field `RB_IER_RECV_RDY` reader - RW, UART interrupt enable for receiver data ready"]
pub type RbIerRecvRdyR = crate::BitReader;
#[doc = "Field `RB_IER_RECV_RDY` writer - RW, UART interrupt enable for receiver data ready"]
pub type RbIerRecvRdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_IER_THR_EMPTY` reader - RW, UART interrupt enable for THR empty"]
pub type RbIerThrEmptyR = crate::BitReader;
#[doc = "Field `RB_IER_THR_EMPTY` writer - RW, UART interrupt enable for THR empty"]
pub type RbIerThrEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_IER_LINE_STAT` reader - RW, UART interrupt enable for receiver line status"]
pub type RbIerLineStatR = crate::BitReader;
#[doc = "Field `RB_IER_LINE_STAT` writer - RW, UART interrupt enable for receiver line status"]
pub type RbIerLineStatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_IER_TXD_EN` reader - RW, UART TXD pin enable"]
pub type RbIerTxdEnR = crate::BitReader;
#[doc = "Field `RB_IER_TXD_EN` writer - RW, UART TXD pin enable"]
pub type RbIerTxdEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, UART interrupt enable for receiver data ready"]
#[inline(always)]
pub fn rb_ier_recv_rdy(&self) -> RbIerRecvRdyR {
RbIerRecvRdyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, UART interrupt enable for THR empty"]
#[inline(always)]
pub fn rb_ier_thr_empty(&self) -> RbIerThrEmptyR {
RbIerThrEmptyR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, UART interrupt enable for receiver line status"]
#[inline(always)]
pub fn rb_ier_line_stat(&self) -> RbIerLineStatR {
RbIerLineStatR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 6 - RW, UART TXD pin enable"]
#[inline(always)]
pub fn rb_ier_txd_en(&self) -> RbIerTxdEnR {
RbIerTxdEnR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, UART interrupt enable for receiver data ready"]
#[inline(always)]
pub fn rb_ier_recv_rdy(&mut self) -> RbIerRecvRdyW<R8UartIerSpec> {
RbIerRecvRdyW::new(self, 0)
}
#[doc = "Bit 1 - RW, UART interrupt enable for THR empty"]
#[inline(always)]
pub fn rb_ier_thr_empty(&mut self) -> RbIerThrEmptyW<R8UartIerSpec> {
RbIerThrEmptyW::new(self, 1)
}
#[doc = "Bit 2 - RW, UART interrupt enable for receiver line status"]
#[inline(always)]
pub fn rb_ier_line_stat(&mut self) -> RbIerLineStatW<R8UartIerSpec> {
RbIerLineStatW::new(self, 2)
}
#[doc = "Bit 6 - RW, UART TXD pin enable"]
#[inline(always)]
pub fn rb_ier_txd_en(&mut self) -> RbIerTxdEnW<R8UartIerSpec> {
RbIerTxdEnW::new(self, 6)
}
}
#[doc = "RW, UART interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartIerSpec;
impl crate::RegisterSpec for R8UartIerSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_ier::R`](R) reader structure"]
impl crate::Readable for R8UartIerSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uart_ier::W`](W) writer structure"]
impl crate::Writable for R8UartIerSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_IER to value 0"]
impl crate::Resettable for R8UartIerSpec {}
}
#[doc = "R8_UART_FCR (rw) register accessor: RW, UART FIFO control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_fcr`] module"]
#[doc(alias = "R8_UART_FCR")]
pub type R8UartFcr = crate::Reg<r8_uart_fcr::R8UartFcrSpec>;
#[doc = "RW, UART FIFO control"]
pub mod r8_uart_fcr {
#[doc = "Register `R8_UART_FCR` reader"]
pub type R = crate::R<R8UartFcrSpec>;
#[doc = "Register `R8_UART_FCR` writer"]
pub type W = crate::W<R8UartFcrSpec>;
#[doc = "Field `RB_FCR_FIFO_EN` reader - RW, UART FIFO enable"]
pub type RbFcrFifoEnR = crate::BitReader;
#[doc = "Field `RB_FCR_FIFO_EN` writer - RW, UART FIFO enable"]
pub type RbFcrFifoEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_FCR_FIFO_TRIG` reader - RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes"]
pub type RbFcrFifoTrigR = crate::FieldReader;
#[doc = "Field `RB_FCR_FIFO_TRIG` writer - RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes"]
pub type RbFcrFifoTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bit 0 - RW, UART FIFO enable"]
#[inline(always)]
pub fn rb_fcr_fifo_en(&self) -> RbFcrFifoEnR {
RbFcrFifoEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 6:7 - RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes"]
#[inline(always)]
pub fn rb_fcr_fifo_trig(&self) -> RbFcrFifoTrigR {
RbFcrFifoTrigR::new((self.bits >> 6) & 3)
}
}
impl W {
#[doc = "Bit 0 - RW, UART FIFO enable"]
#[inline(always)]
pub fn rb_fcr_fifo_en(&mut self) -> RbFcrFifoEnW<R8UartFcrSpec> {
RbFcrFifoEnW::new(self, 0)
}
#[doc = "Bits 6:7 - RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes"]
#[inline(always)]
pub fn rb_fcr_fifo_trig(&mut self) -> RbFcrFifoTrigW<R8UartFcrSpec> {
RbFcrFifoTrigW::new(self, 6)
}
}
#[doc = "RW, UART FIFO control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartFcrSpec;
impl crate::RegisterSpec for R8UartFcrSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_fcr::R`](R) reader structure"]
impl crate::Readable for R8UartFcrSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uart_fcr::W`](W) writer structure"]
impl crate::Writable for R8UartFcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_FCR to value 0"]
impl crate::Resettable for R8UartFcrSpec {}
}
#[doc = "R8_UART_LCR (rw) register accessor: RW, UART line control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_lcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_lcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_lcr`] module"]
#[doc(alias = "R8_UART_LCR")]
pub type R8UartLcr = crate::Reg<r8_uart_lcr::R8UartLcrSpec>;
#[doc = "RW, UART line control"]
pub mod r8_uart_lcr {
#[doc = "Register `R8_UART_LCR` reader"]
pub type R = crate::R<R8UartLcrSpec>;
#[doc = "Register `R8_UART_LCR` writer"]
pub type W = crate::W<R8UartLcrSpec>;
#[doc = "Field `RB_LCR_WORD_SZ` reader - RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit"]
pub type RbLcrWordSzR = crate::FieldReader;
#[doc = "Field `RB_LCR_WORD_SZ` writer - RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit"]
pub type RbLcrWordSzW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_LCR_STOP_BIT` reader - RW, UART stop bit length: 0-1bit, 1-2bit"]
pub type RbLcrStopBitR = crate::BitReader;
#[doc = "Field `RB_LCR_STOP_BIT` writer - RW, UART stop bit length: 0-1bit, 1-2bit"]
pub type RbLcrStopBitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_LCR_PAR_EN` reader - RW, UART parity enable"]
pub type RbLcrParEnR = crate::BitReader;
#[doc = "Field `RB_LCR_PAR_EN` writer - RW, UART parity enable"]
pub type RbLcrParEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_LCR_PAR_MOD` reader - RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space"]
pub type RbLcrParModR = crate::FieldReader;
#[doc = "Field `RB_LCR_PAR_MOD` writer - RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space"]
pub type RbLcrParModW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_LCR_BREAK_EN` reader - RW, UART break control enable"]
pub type RbLcrBreakEnR = crate::BitReader;
#[doc = "Field `RB_LCR_BREAK_EN` writer - RW, UART break control enable"]
pub type RbLcrBreakEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_LCR_GP_BIT/RB_LCR_DLAB` reader - RW, UART general purpose bit;RW, UART reserved bit"]
pub type RbLcrGpBitrbLcrDlabR = crate::BitReader;
#[doc = "Field `RB_LCR_GP_BIT/RB_LCR_DLAB` writer - RW, UART general purpose bit;RW, UART reserved bit"]
pub type RbLcrGpBitrbLcrDlabW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit"]
#[inline(always)]
pub fn rb_lcr_word_sz(&self) -> RbLcrWordSzR {
RbLcrWordSzR::new(self.bits & 3)
}
#[doc = "Bit 2 - RW, UART stop bit length: 0-1bit, 1-2bit"]
#[inline(always)]
pub fn rb_lcr_stop_bit(&self) -> RbLcrStopBitR {
RbLcrStopBitR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, UART parity enable"]
#[inline(always)]
pub fn rb_lcr_par_en(&self) -> RbLcrParEnR {
RbLcrParEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space"]
#[inline(always)]
pub fn rb_lcr_par_mod(&self) -> RbLcrParModR {
RbLcrParModR::new((self.bits >> 4) & 3)
}
#[doc = "Bit 6 - RW, UART break control enable"]
#[inline(always)]
pub fn rb_lcr_break_en(&self) -> RbLcrBreakEnR {
RbLcrBreakEnR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RW, UART general purpose bit;RW, UART reserved bit"]
#[inline(always)]
pub fn rb_lcr_gp_bitrb_lcr_dlab(&self) -> RbLcrGpBitrbLcrDlabR {
RbLcrGpBitrbLcrDlabR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit"]
#[inline(always)]
pub fn rb_lcr_word_sz(&mut self) -> RbLcrWordSzW<R8UartLcrSpec> {
RbLcrWordSzW::new(self, 0)
}
#[doc = "Bit 2 - RW, UART stop bit length: 0-1bit, 1-2bit"]
#[inline(always)]
pub fn rb_lcr_stop_bit(&mut self) -> RbLcrStopBitW<R8UartLcrSpec> {
RbLcrStopBitW::new(self, 2)
}
#[doc = "Bit 3 - RW, UART parity enable"]
#[inline(always)]
pub fn rb_lcr_par_en(&mut self) -> RbLcrParEnW<R8UartLcrSpec> {
RbLcrParEnW::new(self, 3)
}
#[doc = "Bits 4:5 - RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space"]
#[inline(always)]
pub fn rb_lcr_par_mod(&mut self) -> RbLcrParModW<R8UartLcrSpec> {
RbLcrParModW::new(self, 4)
}
#[doc = "Bit 6 - RW, UART break control enable"]
#[inline(always)]
pub fn rb_lcr_break_en(&mut self) -> RbLcrBreakEnW<R8UartLcrSpec> {
RbLcrBreakEnW::new(self, 6)
}
#[doc = "Bit 7 - RW, UART general purpose bit;RW, UART reserved bit"]
#[inline(always)]
pub fn rb_lcr_gp_bitrb_lcr_dlab(&mut self) -> RbLcrGpBitrbLcrDlabW<R8UartLcrSpec> {
RbLcrGpBitrbLcrDlabW::new(self, 7)
}
}
#[doc = "RW, UART line control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_lcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_lcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartLcrSpec;
impl crate::RegisterSpec for R8UartLcrSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_lcr::R`](R) reader structure"]
impl crate::Readable for R8UartLcrSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uart_lcr::W`](W) writer structure"]
impl crate::Writable for R8UartLcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_LCR to value 0"]
impl crate::Resettable for R8UartLcrSpec {}
}
#[doc = "R8_UART_IIR (r) register accessor: RO, UART interrupt identification\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_iir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_iir`] module"]
#[doc(alias = "R8_UART_IIR")]
pub type R8UartIir = crate::Reg<r8_uart_iir::R8UartIirSpec>;
#[doc = "RO, UART interrupt identification"]
pub mod r8_uart_iir {
#[doc = "Register `R8_UART_IIR` reader"]
pub type R = crate::R<R8UartIirSpec>;
#[doc = "Field `RB_IIR_NO_INT` reader - RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt"]
pub type RbIirNoIntR = crate::BitReader;
#[doc = "Field `RB_IIR_INT_MASK` reader - RO, UART interrupt flag bit mask"]
pub type RbIirIntMaskR = crate::FieldReader;
#[doc = "Field `RB_IIR_FIFO_ID` reader - RO, UART FIFO enabled flag"]
pub type RbIirFifoIdR = crate::FieldReader;
impl R {
#[doc = "Bit 0 - RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt"]
#[inline(always)]
pub fn rb_iir_no_int(&self) -> RbIirNoIntR {
RbIirNoIntR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:3 - RO, UART interrupt flag bit mask"]
#[inline(always)]
pub fn rb_iir_int_mask(&self) -> RbIirIntMaskR {
RbIirIntMaskR::new((self.bits >> 1) & 7)
}
#[doc = "Bits 6:7 - RO, UART FIFO enabled flag"]
#[inline(always)]
pub fn rb_iir_fifo_id(&self) -> RbIirFifoIdR {
RbIirFifoIdR::new((self.bits >> 6) & 3)
}
}
#[doc = "RO, UART interrupt identification\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_iir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartIirSpec;
impl crate::RegisterSpec for R8UartIirSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_iir::R`](R) reader structure"]
impl crate::Readable for R8UartIirSpec {}
#[doc = "`reset()` method sets R8_UART_IIR to value 0x01"]
impl crate::Resettable for R8UartIirSpec {
const RESET_VALUE: u8 = 0x01;
}
}
#[doc = "R8_UART_LSR (r) register accessor: RO, UART line status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_lsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_lsr`] module"]
#[doc(alias = "R8_UART_LSR")]
pub type R8UartLsr = crate::Reg<r8_uart_lsr::R8UartLsrSpec>;
#[doc = "RO, UART line status"]
pub mod r8_uart_lsr {
#[doc = "Register `R8_UART_LSR` reader"]
pub type R = crate::R<R8UartLsrSpec>;
#[doc = "Field `RB_LSR_DATA_RDY` reader - RO, UART receiver fifo data ready status"]
pub type RbLsrDataRdyR = crate::BitReader;
#[doc = "Field `RB_LSR_OVER_ERR` reader - RZ, UART receiver overrun error"]
pub type RbLsrOverErrR = crate::BitReader;
#[doc = "Field `RB_LSR_PAR_ERR` reader - RZ, UART receiver parity error"]
pub type RbLsrParErrR = crate::BitReader;
#[doc = "Field `RB_LSR_FRAME_ERR` reader - RZ, UART receiver frame error"]
pub type RbLsrFrameErrR = crate::BitReader;
#[doc = "Field `RB_LSR_BREAK_ERR` reader - RZ, UART receiver break error"]
pub type RbLsrBreakErrR = crate::BitReader;
#[doc = "Field `RB_LSR_TX_FIFO_EMP` reader - RO, UART transmitter fifo empty status"]
pub type RbLsrTxFifoEmpR = crate::BitReader;
#[doc = "Field `RB_LSR_TX_ALL_EMP` reader - RO, UART transmitter all empty status"]
pub type RbLsrTxAllEmpR = crate::BitReader;
#[doc = "Field `RB_LSR_ERR_RX_FIFO` reader - RO, indicate error in UART receiver fifo"]
pub type RbLsrErrRxFifoR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RO, UART receiver fifo data ready status"]
#[inline(always)]
pub fn rb_lsr_data_rdy(&self) -> RbLsrDataRdyR {
RbLsrDataRdyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RZ, UART receiver overrun error"]
#[inline(always)]
pub fn rb_lsr_over_err(&self) -> RbLsrOverErrR {
RbLsrOverErrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RZ, UART receiver parity error"]
#[inline(always)]
pub fn rb_lsr_par_err(&self) -> RbLsrParErrR {
RbLsrParErrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RZ, UART receiver frame error"]
#[inline(always)]
pub fn rb_lsr_frame_err(&self) -> RbLsrFrameErrR {
RbLsrFrameErrR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RZ, UART receiver break error"]
#[inline(always)]
pub fn rb_lsr_break_err(&self) -> RbLsrBreakErrR {
RbLsrBreakErrR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, UART transmitter fifo empty status"]
#[inline(always)]
pub fn rb_lsr_tx_fifo_emp(&self) -> RbLsrTxFifoEmpR {
RbLsrTxFifoEmpR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, UART transmitter all empty status"]
#[inline(always)]
pub fn rb_lsr_tx_all_emp(&self) -> RbLsrTxAllEmpR {
RbLsrTxAllEmpR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, indicate error in UART receiver fifo"]
#[inline(always)]
pub fn rb_lsr_err_rx_fifo(&self) -> RbLsrErrRxFifoR {
RbLsrErrRxFifoR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "RO, UART line status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_lsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartLsrSpec;
impl crate::RegisterSpec for R8UartLsrSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_lsr::R`](R) reader structure"]
impl crate::Readable for R8UartLsrSpec {}
#[doc = "`reset()` method sets R8_UART_LSR to value 0x60"]
impl crate::Resettable for R8UartLsrSpec {
const RESET_VALUE: u8 = 0x60;
}
}
#[doc = "R8_UART_RBR (r) register accessor: RO, UART receiver buffer, receiving byte\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_rbr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_rbr`] module"]
#[doc(alias = "R8_UART_RBR")]
pub type R8UartRbr = crate::Reg<r8_uart_rbr::R8UartRbrSpec>;
#[doc = "RO, UART receiver buffer, receiving byte"]
pub mod r8_uart_rbr {
#[doc = "Register `R8_UART_RBR` reader"]
pub type R = crate::R<R8UartRbrSpec>;
#[doc = "Field `R8_UART_RBR` reader - RO, UART receiver buffer, receiving byte"]
pub type R8UartRbrR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RO, UART receiver buffer, receiving byte"]
#[inline(always)]
pub fn r8_uart_rbr(&self) -> R8UartRbrR {
R8UartRbrR::new(self.bits)
}
}
#[doc = "RO, UART receiver buffer, receiving byte\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_rbr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartRbrSpec;
impl crate::RegisterSpec for R8UartRbrSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_rbr::R`](R) reader structure"]
impl crate::Readable for R8UartRbrSpec {}
#[doc = "`reset()` method sets R8_UART_RBR to value 0"]
impl crate::Resettable for R8UartRbrSpec {}
}
#[doc = "R8_UART_THR (w) register accessor: WO, UART transmitter holding, transmittal byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_thr`] module"]
#[doc(alias = "R8_UART_THR")]
pub type R8UartThr = crate::Reg<r8_uart_thr::R8UartThrSpec>;
#[doc = "WO, UART transmitter holding, transmittal byte"]
pub mod r8_uart_thr {
#[doc = "Register `R8_UART_THR` writer"]
pub type W = crate::W<R8UartThrSpec>;
#[doc = "Field `R8_UART_RBR` writer - WO, UART transmitter holding, transmittal byte"]
pub type R8UartRbrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl W {
#[doc = "Bits 0:7 - WO, UART transmitter holding, transmittal byte"]
#[inline(always)]
pub fn r8_uart_rbr(&mut self) -> R8UartRbrW<R8UartThrSpec> {
R8UartRbrW::new(self, 0)
}
}
#[doc = "WO, UART transmitter holding, transmittal byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartThrSpec;
impl crate::RegisterSpec for R8UartThrSpec {
type Ux = u8;
}
#[doc = "`write(|w| ..)` method takes [`r8_uart_thr::W`](W) writer structure"]
impl crate::Writable for R8UartThrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_THR to value 0"]
impl crate::Resettable for R8UartThrSpec {}
}
#[doc = "R8_UART_RFC (r) register accessor: RO, UART receiver FIFO count\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_rfc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_rfc`] module"]
#[doc(alias = "R8_UART_RFC")]
pub type R8UartRfc = crate::Reg<r8_uart_rfc::R8UartRfcSpec>;
#[doc = "RO, UART receiver FIFO count"]
pub mod r8_uart_rfc {
#[doc = "Register `R8_UART_RFC` reader"]
pub type R = crate::R<R8UartRfcSpec>;
#[doc = "Field `R8_UART_RFC` reader - RO, UART receiver FIFO count"]
pub type R8UartRfcR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RO, UART receiver FIFO count"]
#[inline(always)]
pub fn r8_uart_rfc(&self) -> R8UartRfcR {
R8UartRfcR::new(self.bits)
}
}
#[doc = "RO, UART receiver FIFO count\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_rfc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartRfcSpec;
impl crate::RegisterSpec for R8UartRfcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_rfc::R`](R) reader structure"]
impl crate::Readable for R8UartRfcSpec {}
#[doc = "`reset()` method sets R8_UART_RFC to value 0"]
impl crate::Resettable for R8UartRfcSpec {}
}
#[doc = "R8_UART_TFC (r) register accessor: RO, UART transmitter FIFO count\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_tfc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_tfc`] module"]
#[doc(alias = "R8_UART_TFC")]
pub type R8UartTfc = crate::Reg<r8_uart_tfc::R8UartTfcSpec>;
#[doc = "RO, UART transmitter FIFO count"]
pub mod r8_uart_tfc {
#[doc = "Register `R8_UART_TFC` reader"]
pub type R = crate::R<R8UartTfcSpec>;
#[doc = "Field `R8_UART_TFC` reader - RO, UART receiver FIFO count"]
pub type R8UartTfcR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RO, UART receiver FIFO count"]
#[inline(always)]
pub fn r8_uart_tfc(&self) -> R8UartTfcR {
R8UartTfcR::new(self.bits)
}
}
#[doc = "RO, UART transmitter FIFO count\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_tfc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartTfcSpec;
impl crate::RegisterSpec for R8UartTfcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_tfc::R`](R) reader structure"]
impl crate::Readable for R8UartTfcSpec {}
#[doc = "`reset()` method sets R8_UART_TFC to value 0"]
impl crate::Resettable for R8UartTfcSpec {}
}
#[doc = "R16_UART_DL (rw) register accessor: RW, UART divisor latch\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uart_dl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uart_dl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uart_dl`] module"]
#[doc(alias = "R16_UART_DL")]
pub type R16UartDl = crate::Reg<r16_uart_dl::R16UartDlSpec>;
#[doc = "RW, UART divisor latch"]
pub mod r16_uart_dl {
#[doc = "Register `R16_UART_DL` reader"]
pub type R = crate::R<R16UartDlSpec>;
#[doc = "Register `R16_UART_DL` writer"]
pub type W = crate::W<R16UartDlSpec>;
#[doc = "Field `R16_UART_DL` reader - RW, UART divisor latch"]
pub type R16UartDlR = crate::FieldReader<u16>;
#[doc = "Field `R16_UART_DL` writer - RW, UART divisor latch"]
pub type R16UartDlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW, UART divisor latch"]
#[inline(always)]
pub fn r16_uart_dl(&self) -> R16UartDlR {
R16UartDlR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW, UART divisor latch"]
#[inline(always)]
pub fn r16_uart_dl(&mut self) -> R16UartDlW<R16UartDlSpec> {
R16UartDlW::new(self, 0)
}
}
#[doc = "RW, UART divisor latch\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uart_dl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uart_dl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16UartDlSpec;
impl crate::RegisterSpec for R16UartDlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uart_dl::R`](R) reader structure"]
impl crate::Readable for R16UartDlSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uart_dl::W`](W) writer structure"]
impl crate::Writable for R16UartDlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UART_DL to value 0"]
impl crate::Resettable for R16UartDlSpec {}
}
#[doc = "R8_UART_DIV (rw) register accessor: RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uart_div`] module"]
#[doc(alias = "R8_UART_DIV")]
pub type R8UartDiv = crate::Reg<r8_uart_div::R8UartDivSpec>;
#[doc = "RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
pub mod r8_uart_div {
#[doc = "Register `R8_UART_DIV` reader"]
pub type R = crate::R<R8UartDivSpec>;
#[doc = "Register `R8_UART_DIV` writer"]
pub type W = crate::W<R8UartDivSpec>;
#[doc = "Field `R8_UART_DIV` reader - RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
pub type R8UartDivR = crate::FieldReader;
#[doc = "Field `R8_UART_DIV` writer - RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
pub type R8UartDivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
#[inline(always)]
pub fn r8_uart_div(&self) -> R8UartDivR {
R8UartDivR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128"]
#[inline(always)]
pub fn r8_uart_div(&mut self) -> R8UartDivW<R8UartDivSpec> {
R8UartDivW::new(self, 0)
}
}
#[doc = "RW, UART pre-divisor latch byte, only low 7 bit, from 1 to 128\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uart_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uart_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UartDivSpec;
impl crate::RegisterSpec for R8UartDivSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uart_div::R`](R) reader structure"]
impl crate::Readable for R8UartDivSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uart_div::W`](W) writer structure"]
impl crate::Writable for R8UartDivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UART_DIV to value 0"]
impl crate::Resettable for R8UartDivSpec {}
}
}
#[doc = "SPI register"]
pub type Spi = crate::Periph<spi::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for Spi {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi").finish()
}
}
#[doc = "SPI register"]
pub mod spi {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r8_spi_ctrl_mod: R8SpiCtrlMod,
r8_spi_ctrl_cfg: R8SpiCtrlCfg,
r8_spi_inter_en: R8SpiInterEn,
r8_spi_clock_divr8_spi_slave_pre: R8SpiClockDivr8SpiSlavePre,
r8_spi_buffer: R8SpiBuffer,
r8_spi_run_flag: R8SpiRunFlag,
r8_spi_int_flag: R8SpiIntFlag,
r8_spi_fifo_count: R8SpiFifoCount,
r8_spi_int_type: R8SpiIntType,
r8_spi_inter1_en: R8SpiInter1En,
r8_spi_int1_flag: R8SpiInt1Flag,
_reserved11: [u8; 0x01],
r16_spi_total_cnt: R16SpiTotalCnt,
_reserved12: [u8; 0x02],
r8_spi_fifo: R8SpiFifo,
_reserved13: [u8; 0x02],
r8_spi_fifo_count1: R8SpiFifoCount1,
r32_spi_dma_now: R32SpiDmaNow,
r32_spi_dma_beg: R32SpiDmaBeg,
r32_spi_dma_end: R32SpiDmaEnd,
}
impl RegisterBlock {
#[doc = "0x00 - RW, SPI mode control"]
#[inline(always)]
pub const fn r8_spi_ctrl_mod(&self) -> &R8SpiCtrlMod {
&self.r8_spi_ctrl_mod
}
#[doc = "0x01 - RW, SPI configuration control"]
#[inline(always)]
pub const fn r8_spi_ctrl_cfg(&self) -> &R8SpiCtrlCfg {
&self.r8_spi_ctrl_cfg
}
#[doc = "0x02 - RW, SPI interrupt enable"]
#[inline(always)]
pub const fn r8_spi_inter_en(&self) -> &R8SpiInterEn {
&self.r8_spi_inter_en
}
#[doc = "0x03 - RW, SPI master clock divisor;RW, SPI slave preset value"]
#[inline(always)]
pub const fn r8_spi_clock_divr8_spi_slave_pre(&self) -> &R8SpiClockDivr8SpiSlavePre {
&self.r8_spi_clock_divr8_spi_slave_pre
}
#[doc = "0x04 - RW, SPI data buffer"]
#[inline(always)]
pub const fn r8_spi_buffer(&self) -> &R8SpiBuffer {
&self.r8_spi_buffer
}
#[doc = "0x05 - RO, SPI work flag"]
#[inline(always)]
pub const fn r8_spi_run_flag(&self) -> &R8SpiRunFlag {
&self.r8_spi_run_flag
}
#[doc = "0x06 - RW1, SPI interrupt flag"]
#[inline(always)]
pub const fn r8_spi_int_flag(&self) -> &R8SpiIntFlag {
&self.r8_spi_int_flag
}
#[doc = "0x07 - RW, SPI FIFO count status"]
#[inline(always)]
pub const fn r8_spi_fifo_count(&self) -> &R8SpiFifoCount {
&self.r8_spi_fifo_count
}
#[doc = "0x08 - RW, SPI interrupt trigger mode selection register"]
#[inline(always)]
pub const fn r8_spi_int_type(&self) -> &R8SpiIntType {
&self.r8_spi_int_type
}
#[doc = "0x09 - RW, SPI Interrupt 1 Enable Register"]
#[inline(always)]
pub const fn r8_spi_inter1_en(&self) -> &R8SpiInter1En {
&self.r8_spi_inter1_en
}
#[doc = "0x0a - RW1, SPI interrupt 1 flag register"]
#[inline(always)]
pub const fn r8_spi_int1_flag(&self) -> &R8SpiInt1Flag {
&self.r8_spi_int1_flag
}
#[doc = "0x0c - RW, SPI total byte count, only low 12 bit"]
#[inline(always)]
pub const fn r16_spi_total_cnt(&self) -> &R16SpiTotalCnt {
&self.r16_spi_total_cnt
}
#[doc = "0x10 - RO/WO, SPI FIFO register"]
#[inline(always)]
pub const fn r8_spi_fifo(&self) -> &R8SpiFifo {
&self.r8_spi_fifo
}
#[doc = "0x13 - RO, SPI FIFO count status"]
#[inline(always)]
pub const fn r8_spi_fifo_count1(&self) -> &R8SpiFifoCount1 {
&self.r8_spi_fifo_count1
}
#[doc = "0x14 - RW, SPI DMA current address"]
#[inline(always)]
pub const fn r32_spi_dma_now(&self) -> &R32SpiDmaNow {
&self.r32_spi_dma_now
}
#[doc = "0x18 - RW, SPI DMA begin address"]
#[inline(always)]
pub const fn r32_spi_dma_beg(&self) -> &R32SpiDmaBeg {
&self.r32_spi_dma_beg
}
#[doc = "0x1c - RW, SPI DMA end address"]
#[inline(always)]
pub const fn r32_spi_dma_end(&self) -> &R32SpiDmaEnd {
&self.r32_spi_dma_end
}
}
#[doc = "R8_SPI_CTRL_MOD (rw) register accessor: RW, SPI mode control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_ctrl_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_ctrl_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_ctrl_mod`] module"]
#[doc(alias = "R8_SPI_CTRL_MOD")]
pub type R8SpiCtrlMod = crate::Reg<r8_spi_ctrl_mod::R8SpiCtrlModSpec>;
#[doc = "RW, SPI mode control"]
pub mod r8_spi_ctrl_mod {
#[doc = "Register `R8_SPI_CTRL_MOD` reader"]
pub type R = crate::R<R8SpiCtrlModSpec>;
#[doc = "Register `R8_SPI_CTRL_MOD` writer"]
pub type W = crate::W<R8SpiCtrlModSpec>;
#[doc = "Field `RB_SPI_MODE_SLAVE` reader - RW, SPI slave mode: 0=master or host, 1=slave or device"]
pub type RbSpiModeSlaveR = crate::BitReader;
#[doc = "Field `RB_SPI_MODE_SLAVE` writer - RW, SPI slave mode: 0=master or host, 1=slave or device"]
pub type RbSpiModeSlaveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_ALL_CLEAR` reader - RW, force clear SPI FIFO and count"]
pub type RbSpiAllClearR = crate::BitReader;
#[doc = "Field `RB_SPI_ALL_CLEAR` writer - RW, force clear SPI FIFO and count"]
pub type RbSpiAllClearW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_2WIRE_MOD` reader - RW, SPI enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
pub type RbSpi2wireModR = crate::BitReader;
#[doc = "Field `RB_SPI_2WIRE_MOD` writer - RW, SPI enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
pub type RbSpi2wireModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_MST_SCK_MOD/RB_SPI_SLV_CMD_MOD` reader - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI slave command mode: 0=byte stream, 1=first byte command"]
pub type RbSpiMstSckModrbSpiSlvCmdModR = crate::BitReader;
#[doc = "Field `RB_SPI_MST_SCK_MOD/RB_SPI_SLV_CMD_MOD` writer - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI slave command mode: 0=byte stream, 1=first byte command"]
pub type RbSpiMstSckModrbSpiSlvCmdModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_FIFO_DIR` reader - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
pub type RbSpiFifoDirR = crate::BitReader;
#[doc = "Field `RB_SPI_FIFO_DIR` writer - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
pub type RbSpiFifoDirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_SCK_OE` reader - RW, SPI SCK output enable"]
pub type RbSpiSckOeR = crate::BitReader;
#[doc = "Field `RB_SPI_SCK_OE` writer - RW, SPI SCK output enable"]
pub type RbSpiSckOeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_MOSI_OE` reader - RW, SPI MOSI output enable"]
pub type RbSpiMosiOeR = crate::BitReader;
#[doc = "Field `RB_SPI_MOSI_OE` writer - RW, SPI MOSI output enable"]
pub type RbSpiMosiOeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_MISO_OE` reader - RW, SPI MISO output enable"]
pub type RbSpiMisoOeR = crate::BitReader;
#[doc = "Field `RB_SPI_MISO_OE` writer - RW, SPI MISO output enable"]
pub type RbSpiMisoOeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, SPI slave mode: 0=master or host, 1=slave or device"]
#[inline(always)]
pub fn rb_spi_mode_slave(&self) -> RbSpiModeSlaveR {
RbSpiModeSlaveR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
#[inline(always)]
pub fn rb_spi_all_clear(&self) -> RbSpiAllClearR {
RbSpiAllClearR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, SPI enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
#[inline(always)]
pub fn rb_spi_2wire_mod(&self) -> RbSpi2wireModR {
RbSpi2wireModR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI slave command mode: 0=byte stream, 1=first byte command"]
#[inline(always)]
pub fn rb_spi_mst_sck_modrb_spi_slv_cmd_mod(&self) -> RbSpiMstSckModrbSpiSlvCmdModR {
RbSpiMstSckModrbSpiSlvCmdModR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
#[inline(always)]
pub fn rb_spi_fifo_dir(&self) -> RbSpiFifoDirR {
RbSpiFifoDirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RW, SPI SCK output enable"]
#[inline(always)]
pub fn rb_spi_sck_oe(&self) -> RbSpiSckOeR {
RbSpiSckOeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RW, SPI MOSI output enable"]
#[inline(always)]
pub fn rb_spi_mosi_oe(&self) -> RbSpiMosiOeR {
RbSpiMosiOeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RW, SPI MISO output enable"]
#[inline(always)]
pub fn rb_spi_miso_oe(&self) -> RbSpiMisoOeR {
RbSpiMisoOeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, SPI slave mode: 0=master or host, 1=slave or device"]
#[inline(always)]
pub fn rb_spi_mode_slave(&mut self) -> RbSpiModeSlaveW<R8SpiCtrlModSpec> {
RbSpiModeSlaveW::new(self, 0)
}
#[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
#[inline(always)]
pub fn rb_spi_all_clear(&mut self) -> RbSpiAllClearW<R8SpiCtrlModSpec> {
RbSpiAllClearW::new(self, 1)
}
#[doc = "Bit 2 - RW, SPI enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
#[inline(always)]
pub fn rb_spi_2wire_mod(&mut self) -> RbSpi2wireModW<R8SpiCtrlModSpec> {
RbSpi2wireModW::new(self, 2)
}
#[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI slave command mode: 0=byte stream, 1=first byte command"]
#[inline(always)]
pub fn rb_spi_mst_sck_modrb_spi_slv_cmd_mod(
&mut self,
) -> RbSpiMstSckModrbSpiSlvCmdModW<R8SpiCtrlModSpec> {
RbSpiMstSckModrbSpiSlvCmdModW::new(self, 3)
}
#[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
#[inline(always)]
pub fn rb_spi_fifo_dir(&mut self) -> RbSpiFifoDirW<R8SpiCtrlModSpec> {
RbSpiFifoDirW::new(self, 4)
}
#[doc = "Bit 5 - RW, SPI SCK output enable"]
#[inline(always)]
pub fn rb_spi_sck_oe(&mut self) -> RbSpiSckOeW<R8SpiCtrlModSpec> {
RbSpiSckOeW::new(self, 5)
}
#[doc = "Bit 6 - RW, SPI MOSI output enable"]
#[inline(always)]
pub fn rb_spi_mosi_oe(&mut self) -> RbSpiMosiOeW<R8SpiCtrlModSpec> {
RbSpiMosiOeW::new(self, 6)
}
#[doc = "Bit 7 - RW, SPI MISO output enable"]
#[inline(always)]
pub fn rb_spi_miso_oe(&mut self) -> RbSpiMisoOeW<R8SpiCtrlModSpec> {
RbSpiMisoOeW::new(self, 7)
}
}
#[doc = "RW, SPI mode control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_ctrl_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_ctrl_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiCtrlModSpec;
impl crate::RegisterSpec for R8SpiCtrlModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_ctrl_mod::R`](R) reader structure"]
impl crate::Readable for R8SpiCtrlModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_ctrl_mod::W`](W) writer structure"]
impl crate::Writable for R8SpiCtrlModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_CTRL_MOD to value 0x02"]
impl crate::Resettable for R8SpiCtrlModSpec {
const RESET_VALUE: u8 = 0x02;
}
}
#[doc = "R8_SPI_CTRL_CFG (rw) register accessor: RW, SPI configuration control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_ctrl_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_ctrl_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_ctrl_cfg`] module"]
#[doc(alias = "R8_SPI_CTRL_CFG")]
pub type R8SpiCtrlCfg = crate::Reg<r8_spi_ctrl_cfg::R8SpiCtrlCfgSpec>;
#[doc = "RW, SPI configuration control"]
pub mod r8_spi_ctrl_cfg {
#[doc = "Register `R8_SPI_CTRL_CFG` reader"]
pub type R = crate::R<R8SpiCtrlCfgSpec>;
#[doc = "Register `R8_SPI_CTRL_CFG` writer"]
pub type W = crate::W<R8SpiCtrlCfgSpec>;
#[doc = "Field `RB_SPI_DMA_ENABLE` reader - RW, SPI DMA enable"]
pub type RbSpiDmaEnableR = crate::BitReader;
#[doc = "Field `RB_SPI_DMA_ENABLE` writer - RW, SPI DMA enable"]
pub type RbSpiDmaEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_MST_CLK_SEL` reader - RW, When RB_SPI-PODE_SLAVE=0, select the main clock polarity; When RB_SPI-PODE_SLAVE=1, select the input and output direction for the two-wire mode slave machine"]
pub type RbMstClkSelR = crate::BitReader;
#[doc = "Field `RB_MST_CLK_SEL` writer - RW, When RB_SPI-PODE_SLAVE=0, select the main clock polarity; When RB_SPI-PODE_SLAVE=1, select the input and output direction for the two-wire mode slave machine"]
pub type RbMstClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_DMA_LOOP` reader - RW, SPI DMA address loop enable"]
pub type RbSpiDmaLoopR = crate::BitReader;
#[doc = "Field `RB_SPI_DMA_LOOP` writer - RW, SPI DMA address loop enable"]
pub type RbSpiDmaLoopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_AUTO_IF` reader - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
pub type RbSpiAutoIfR = crate::BitReader;
#[doc = "Field `RB_SPI_AUTO_IF` writer - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
pub type RbSpiAutoIfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_BIT_ORDER` reader - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
pub type RbSpiBitOrderR = crate::BitReader;
#[doc = "Field `RB_SPI_BIT_ORDER` writer - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
pub type RbSpiBitOrderW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_MST_DLY_EN` reader - RW, SPI master input delay enable"]
pub type RbSpiMstDlyEnR = crate::BitReader;
#[doc = "Field `RB_SPI_MST_DLY_EN` writer - RW, SPI master input delay enable"]
pub type RbSpiMstDlyEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, SPI DMA enable"]
#[inline(always)]
pub fn rb_spi_dma_enable(&self) -> RbSpiDmaEnableR {
RbSpiDmaEnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, When RB_SPI-PODE_SLAVE=0, select the main clock polarity; When RB_SPI-PODE_SLAVE=1, select the input and output direction for the two-wire mode slave machine"]
#[inline(always)]
pub fn rb_mst_clk_sel(&self) -> RbMstClkSelR {
RbMstClkSelR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, SPI DMA address loop enable"]
#[inline(always)]
pub fn rb_spi_dma_loop(&self) -> RbSpiDmaLoopR {
RbSpiDmaLoopR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
#[inline(always)]
pub fn rb_spi_auto_if(&self) -> RbSpiAutoIfR {
RbSpiAutoIfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
#[inline(always)]
pub fn rb_spi_bit_order(&self) -> RbSpiBitOrderR {
RbSpiBitOrderR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RW, SPI master input delay enable"]
#[inline(always)]
pub fn rb_spi_mst_dly_en(&self) -> RbSpiMstDlyEnR {
RbSpiMstDlyEnR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, SPI DMA enable"]
#[inline(always)]
pub fn rb_spi_dma_enable(&mut self) -> RbSpiDmaEnableW<R8SpiCtrlCfgSpec> {
RbSpiDmaEnableW::new(self, 0)
}
#[doc = "Bit 1 - RW, When RB_SPI-PODE_SLAVE=0, select the main clock polarity; When RB_SPI-PODE_SLAVE=1, select the input and output direction for the two-wire mode slave machine"]
#[inline(always)]
pub fn rb_mst_clk_sel(&mut self) -> RbMstClkSelW<R8SpiCtrlCfgSpec> {
RbMstClkSelW::new(self, 1)
}
#[doc = "Bit 2 - RW, SPI DMA address loop enable"]
#[inline(always)]
pub fn rb_spi_dma_loop(&mut self) -> RbSpiDmaLoopW<R8SpiCtrlCfgSpec> {
RbSpiDmaLoopW::new(self, 2)
}
#[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
#[inline(always)]
pub fn rb_spi_auto_if(&mut self) -> RbSpiAutoIfW<R8SpiCtrlCfgSpec> {
RbSpiAutoIfW::new(self, 4)
}
#[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
#[inline(always)]
pub fn rb_spi_bit_order(&mut self) -> RbSpiBitOrderW<R8SpiCtrlCfgSpec> {
RbSpiBitOrderW::new(self, 5)
}
#[doc = "Bit 6 - RW, SPI master input delay enable"]
#[inline(always)]
pub fn rb_spi_mst_dly_en(&mut self) -> RbSpiMstDlyEnW<R8SpiCtrlCfgSpec> {
RbSpiMstDlyEnW::new(self, 6)
}
}
#[doc = "RW, SPI configuration control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_ctrl_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_ctrl_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiCtrlCfgSpec;
impl crate::RegisterSpec for R8SpiCtrlCfgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_ctrl_cfg::R`](R) reader structure"]
impl crate::Readable for R8SpiCtrlCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_ctrl_cfg::W`](W) writer structure"]
impl crate::Writable for R8SpiCtrlCfgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_CTRL_CFG to value 0"]
impl crate::Resettable for R8SpiCtrlCfgSpec {}
}
#[doc = "R8_SPI_INTER_EN (rw) register accessor: RW, SPI interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_inter_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_inter_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_inter_en`] module"]
#[doc(alias = "R8_SPI_INTER_EN")]
pub type R8SpiInterEn = crate::Reg<r8_spi_inter_en::R8SpiInterEnSpec>;
#[doc = "RW, SPI interrupt enable"]
pub mod r8_spi_inter_en {
#[doc = "Register `R8_SPI_INTER_EN` reader"]
pub type R = crate::R<R8SpiInterEnSpec>;
#[doc = "Register `R8_SPI_INTER_EN` writer"]
pub type W = crate::W<R8SpiInterEnSpec>;
#[doc = "Field `RB_SPI_IE_CNT_END` reader - RW, enable interrupt for SPI total byte count end"]
pub type RbSpiIeCntEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_CNT_END` writer - RW, enable interrupt for SPI total byte count end"]
pub type RbSpiIeCntEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_BYTE_END` reader - RW, enable interrupt for SPI byte exchanged"]
pub type RbSpiIeByteEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_BYTE_END` writer - RW, enable interrupt for SPI byte exchanged"]
pub type RbSpiIeByteEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_FIFO_HF` reader - RW, enable interrupt for SPI FIFO half"]
pub type RbSpiIeFifoHfR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FIFO_HF` writer - RW, enable interrupt for SPI FIFO half"]
pub type RbSpiIeFifoHfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_DMA_END` reader - RW, enable interrupt for SPI DMA completion"]
pub type RbSpiIeDmaEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_DMA_END` writer - RW, enable interrupt for SPI DMA completion"]
pub type RbSpiIeDmaEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_FIFO_OV` reader - RW, enable interrupt for SPI FIFO overflow"]
pub type RbSpiIeFifoOvR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FIFO_OV` writer - RW, enable interrupt for SPI FIFO overflow"]
pub type RbSpiIeFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_FST_BYTE` reader - RW, enable interrupt for SPI slave mode first byte received"]
pub type RbSpiIeFstByteR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FST_BYTE` writer - RW, enable interrupt for SPI slave mode first byte received"]
pub type RbSpiIeFstByteW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
#[inline(always)]
pub fn rb_spi_ie_cnt_end(&self) -> RbSpiIeCntEndR {
RbSpiIeCntEndR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
#[inline(always)]
pub fn rb_spi_ie_byte_end(&self) -> RbSpiIeByteEndR {
RbSpiIeByteEndR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
#[inline(always)]
pub fn rb_spi_ie_fifo_hf(&self) -> RbSpiIeFifoHfR {
RbSpiIeFifoHfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, enable interrupt for SPI DMA completion"]
#[inline(always)]
pub fn rb_spi_ie_dma_end(&self) -> RbSpiIeDmaEndR {
RbSpiIeDmaEndR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, enable interrupt for SPI FIFO overflow"]
#[inline(always)]
pub fn rb_spi_ie_fifo_ov(&self) -> RbSpiIeFifoOvR {
RbSpiIeFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7 - RW, enable interrupt for SPI slave mode first byte received"]
#[inline(always)]
pub fn rb_spi_ie_fst_byte(&self) -> RbSpiIeFstByteR {
RbSpiIeFstByteR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
#[inline(always)]
pub fn rb_spi_ie_cnt_end(&mut self) -> RbSpiIeCntEndW<R8SpiInterEnSpec> {
RbSpiIeCntEndW::new(self, 0)
}
#[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
#[inline(always)]
pub fn rb_spi_ie_byte_end(&mut self) -> RbSpiIeByteEndW<R8SpiInterEnSpec> {
RbSpiIeByteEndW::new(self, 1)
}
#[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
#[inline(always)]
pub fn rb_spi_ie_fifo_hf(&mut self) -> RbSpiIeFifoHfW<R8SpiInterEnSpec> {
RbSpiIeFifoHfW::new(self, 2)
}
#[doc = "Bit 3 - RW, enable interrupt for SPI DMA completion"]
#[inline(always)]
pub fn rb_spi_ie_dma_end(&mut self) -> RbSpiIeDmaEndW<R8SpiInterEnSpec> {
RbSpiIeDmaEndW::new(self, 3)
}
#[doc = "Bit 4 - RW, enable interrupt for SPI FIFO overflow"]
#[inline(always)]
pub fn rb_spi_ie_fifo_ov(&mut self) -> RbSpiIeFifoOvW<R8SpiInterEnSpec> {
RbSpiIeFifoOvW::new(self, 4)
}
#[doc = "Bit 7 - RW, enable interrupt for SPI slave mode first byte received"]
#[inline(always)]
pub fn rb_spi_ie_fst_byte(&mut self) -> RbSpiIeFstByteW<R8SpiInterEnSpec> {
RbSpiIeFstByteW::new(self, 7)
}
}
#[doc = "RW, SPI interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_inter_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_inter_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiInterEnSpec;
impl crate::RegisterSpec for R8SpiInterEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_inter_en::R`](R) reader structure"]
impl crate::Readable for R8SpiInterEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_inter_en::W`](W) writer structure"]
impl crate::Writable for R8SpiInterEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_INTER_EN to value 0"]
impl crate::Resettable for R8SpiInterEnSpec {}
}
#[doc = "R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE (rw) register accessor: RW, SPI master clock divisor;RW, SPI slave preset value\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_clock_divr8_spi_slave_pre::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_clock_divr8_spi_slave_pre::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_clock_divr8_spi_slave_pre`] module"]
#[doc(alias = "R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE")]
pub type R8SpiClockDivr8SpiSlavePre =
crate::Reg<r8_spi_clock_divr8_spi_slave_pre::R8SpiClockDivr8SpiSlavePreSpec>;
#[doc = "RW, SPI master clock divisor;RW, SPI slave preset value"]
pub mod r8_spi_clock_divr8_spi_slave_pre {
#[doc = "Register `R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE` reader"]
pub type R = crate::R<R8SpiClockDivr8SpiSlavePreSpec>;
#[doc = "Register `R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE` writer"]
pub type W = crate::W<R8SpiClockDivr8SpiSlavePreSpec>;
#[doc = "Field `R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE` reader - RW, SPI master clock divisor;RW, SPI slave preset value"]
pub type R8SpiClockDivr8SpiSlavePreR = crate::FieldReader;
#[doc = "Field `R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE` writer - RW, SPI master clock divisor;RW, SPI slave preset value"]
pub type R8SpiClockDivr8SpiSlavePreW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, SPI master clock divisor;RW, SPI slave preset value"]
#[inline(always)]
pub fn r8_spi_clock_divr8_spi_slave_pre(&self) -> R8SpiClockDivr8SpiSlavePreR {
R8SpiClockDivr8SpiSlavePreR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RW, SPI master clock divisor;RW, SPI slave preset value"]
#[inline(always)]
pub fn r8_spi_clock_divr8_spi_slave_pre(
&mut self,
) -> R8SpiClockDivr8SpiSlavePreW<R8SpiClockDivr8SpiSlavePreSpec> {
R8SpiClockDivr8SpiSlavePreW::new(self, 0)
}
}
#[doc = "RW, SPI master clock divisor;RW, SPI slave preset value\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_clock_divr8_spi_slave_pre::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_clock_divr8_spi_slave_pre::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiClockDivr8SpiSlavePreSpec;
impl crate::RegisterSpec for R8SpiClockDivr8SpiSlavePreSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_clock_divr8_spi_slave_pre::R`](R) reader structure"]
impl crate::Readable for R8SpiClockDivr8SpiSlavePreSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_clock_divr8_spi_slave_pre::W`](W) writer structure"]
impl crate::Writable for R8SpiClockDivr8SpiSlavePreSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_CLOCK_DIV/R8_SPI_SLAVE_PRE to value 0x10"]
impl crate::Resettable for R8SpiClockDivr8SpiSlavePreSpec {
const RESET_VALUE: u8 = 0x10;
}
}
#[doc = "R8_SPI_BUFFER (rw) register accessor: RW, SPI data buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_buffer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_buffer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_buffer`] module"]
#[doc(alias = "R8_SPI_BUFFER")]
pub type R8SpiBuffer = crate::Reg<r8_spi_buffer::R8SpiBufferSpec>;
#[doc = "RW, SPI data buffer"]
pub mod r8_spi_buffer {
#[doc = "Register `R8_SPI_BUFFER` reader"]
pub type R = crate::R<R8SpiBufferSpec>;
#[doc = "Register `R8_SPI_BUFFER` writer"]
pub type W = crate::W<R8SpiBufferSpec>;
#[doc = "Field `R8_SPI_BUFFER` reader - RW, SPI data buffer"]
pub type R8SpiBufferR = crate::FieldReader;
#[doc = "Field `R8_SPI_BUFFER` writer - RW, SPI data buffer"]
pub type R8SpiBufferW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, SPI data buffer"]
#[inline(always)]
pub fn r8_spi_buffer(&self) -> R8SpiBufferR {
R8SpiBufferR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RW, SPI data buffer"]
#[inline(always)]
pub fn r8_spi_buffer(&mut self) -> R8SpiBufferW<R8SpiBufferSpec> {
R8SpiBufferW::new(self, 0)
}
}
#[doc = "RW, SPI data buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_buffer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_buffer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiBufferSpec;
impl crate::RegisterSpec for R8SpiBufferSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_buffer::R`](R) reader structure"]
impl crate::Readable for R8SpiBufferSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_buffer::W`](W) writer structure"]
impl crate::Writable for R8SpiBufferSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_BUFFER to value 0"]
impl crate::Resettable for R8SpiBufferSpec {}
}
#[doc = "R8_SPI_RUN_FLAG (r) register accessor: RO, SPI work flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_run_flag::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_run_flag`] module"]
#[doc(alias = "R8_SPI_RUN_FLAG")]
pub type R8SpiRunFlag = crate::Reg<r8_spi_run_flag::R8SpiRunFlagSpec>;
#[doc = "RO, SPI work flag"]
pub mod r8_spi_run_flag {
#[doc = "Register `R8_SPI_RUN_FLAG` reader"]
pub type R = crate::R<R8SpiRunFlagSpec>;
#[doc = "Field `RB_SPI_SLV_CMD_ACT` reader - RO, SPI slave first byte or command flag"]
pub type RbSpiSlvCmdActR = crate::BitReader;
#[doc = "Field `RB_SPI_FIFO_READY` reader - RO, SPI FIFO ready status"]
pub type RbSpiFifoReadyR = crate::BitReader;
#[doc = "Field `RB_SPI_SLV_CS_LOAD` reader - RO, SPI slave chip-select loading status"]
pub type RbSpiSlvCsLoadR = crate::BitReader;
#[doc = "Field `RB_SPI_SLV_SELECT` reader - RO, SPI slave selection status"]
pub type RbSpiSlvSelectR = crate::BitReader;
impl R {
#[doc = "Bit 4 - RO, SPI slave first byte or command flag"]
#[inline(always)]
pub fn rb_spi_slv_cmd_act(&self) -> RbSpiSlvCmdActR {
RbSpiSlvCmdActR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, SPI FIFO ready status"]
#[inline(always)]
pub fn rb_spi_fifo_ready(&self) -> RbSpiFifoReadyR {
RbSpiFifoReadyR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, SPI slave chip-select loading status"]
#[inline(always)]
pub fn rb_spi_slv_cs_load(&self) -> RbSpiSlvCsLoadR {
RbSpiSlvCsLoadR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, SPI slave selection status"]
#[inline(always)]
pub fn rb_spi_slv_select(&self) -> RbSpiSlvSelectR {
RbSpiSlvSelectR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "RO, SPI work flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_run_flag::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiRunFlagSpec;
impl crate::RegisterSpec for R8SpiRunFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_run_flag::R`](R) reader structure"]
impl crate::Readable for R8SpiRunFlagSpec {}
#[doc = "`reset()` method sets R8_SPI_RUN_FLAG to value 0"]
impl crate::Resettable for R8SpiRunFlagSpec {}
}
#[doc = "R8_SPI_INT_FLAG (rw) register accessor: RW1, SPI interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_int_flag`] module"]
#[doc(alias = "R8_SPI_INT_FLAG")]
pub type R8SpiIntFlag = crate::Reg<r8_spi_int_flag::R8SpiIntFlagSpec>;
#[doc = "RW1, SPI interrupt flag"]
pub mod r8_spi_int_flag {
#[doc = "Register `R8_SPI_INT_FLAG` reader"]
pub type R = crate::R<R8SpiIntFlagSpec>;
#[doc = "Register `R8_SPI_INT_FLAG` writer"]
pub type W = crate::W<R8SpiIntFlagSpec>;
#[doc = "Field `RB_SPI_IF_CNT_END` reader - RW1, interrupt flag for SPI total byte count end"]
pub type RbSpiIfCntEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_CNT_END` writer - RW1, interrupt flag for SPI total byte count end"]
pub type RbSpiIfCntEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IF_BYTE_END` reader - RW1, interrupt flag for SPI byte exchanged"]
pub type RbSpiIfByteEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_BYTE_END` writer - RW1, interrupt flag for SPI byte exchanged"]
pub type RbSpiIfByteEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IF_FIFO_HF` reader - RW1, interrupt flag for SPI FIFO half"]
pub type RbSpiIfFifoHfR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_FIFO_HF` writer - RW1, interrupt flag for SPI FIFO half"]
pub type RbSpiIfFifoHfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IF_DMA_END` reader - RW1, interrupt flag for SPI DMA completion"]
pub type RbSpiIfDmaEndR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_DMA_END` writer - RW1, interrupt flag for SPI DMA completion"]
pub type RbSpiIfDmaEndW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IF_FIFO_OV` reader - RW1, interrupt flag for SPI FIFO overflow"]
pub type RbSpiIfFifoOvR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_FIFO_OV` writer - RW1, interrupt flag for SPI FIFO overflow"]
pub type RbSpiIfFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_FREE` reader - RO, current SPI free status"]
pub type RbSpiFreeR = crate::BitReader;
#[doc = "Field `RB_SPI_FREE` writer - RO, current SPI free status"]
pub type RbSpiFreeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IF_FST_BYTE` reader - RW1, interrupt flag for SPI slave mode first byte received"]
pub type RbSpiIfFstByteR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_FST_BYTE` writer - RW1, interrupt flag for SPI slave mode first byte received"]
pub type RbSpiIfFstByteW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
#[inline(always)]
pub fn rb_spi_if_cnt_end(&self) -> RbSpiIfCntEndR {
RbSpiIfCntEndR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
#[inline(always)]
pub fn rb_spi_if_byte_end(&self) -> RbSpiIfByteEndR {
RbSpiIfByteEndR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half"]
#[inline(always)]
pub fn rb_spi_if_fifo_hf(&self) -> RbSpiIfFifoHfR {
RbSpiIfFifoHfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW1, interrupt flag for SPI DMA completion"]
#[inline(always)]
pub fn rb_spi_if_dma_end(&self) -> RbSpiIfDmaEndR {
RbSpiIfDmaEndR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW1, interrupt flag for SPI FIFO overflow"]
#[inline(always)]
pub fn rb_spi_if_fifo_ov(&self) -> RbSpiIfFifoOvR {
RbSpiIfFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - RO, current SPI free status"]
#[inline(always)]
pub fn rb_spi_free(&self) -> RbSpiFreeR {
RbSpiFreeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RW1, interrupt flag for SPI slave mode first byte received"]
#[inline(always)]
pub fn rb_spi_if_fst_byte(&self) -> RbSpiIfFstByteR {
RbSpiIfFstByteR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
#[inline(always)]
pub fn rb_spi_if_cnt_end(&mut self) -> RbSpiIfCntEndW<R8SpiIntFlagSpec> {
RbSpiIfCntEndW::new(self, 0)
}
#[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
#[inline(always)]
pub fn rb_spi_if_byte_end(&mut self) -> RbSpiIfByteEndW<R8SpiIntFlagSpec> {
RbSpiIfByteEndW::new(self, 1)
}
#[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half"]
#[inline(always)]
pub fn rb_spi_if_fifo_hf(&mut self) -> RbSpiIfFifoHfW<R8SpiIntFlagSpec> {
RbSpiIfFifoHfW::new(self, 2)
}
#[doc = "Bit 3 - RW1, interrupt flag for SPI DMA completion"]
#[inline(always)]
pub fn rb_spi_if_dma_end(&mut self) -> RbSpiIfDmaEndW<R8SpiIntFlagSpec> {
RbSpiIfDmaEndW::new(self, 3)
}
#[doc = "Bit 4 - RW1, interrupt flag for SPI FIFO overflow"]
#[inline(always)]
pub fn rb_spi_if_fifo_ov(&mut self) -> RbSpiIfFifoOvW<R8SpiIntFlagSpec> {
RbSpiIfFifoOvW::new(self, 4)
}
#[doc = "Bit 6 - RO, current SPI free status"]
#[inline(always)]
pub fn rb_spi_free(&mut self) -> RbSpiFreeW<R8SpiIntFlagSpec> {
RbSpiFreeW::new(self, 6)
}
#[doc = "Bit 7 - RW1, interrupt flag for SPI slave mode first byte received"]
#[inline(always)]
pub fn rb_spi_if_fst_byte(&mut self) -> RbSpiIfFstByteW<R8SpiIntFlagSpec> {
RbSpiIfFstByteW::new(self, 7)
}
}
#[doc = "RW1, SPI interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiIntFlagSpec;
impl crate::RegisterSpec for R8SpiIntFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_int_flag::R`](R) reader structure"]
impl crate::Readable for R8SpiIntFlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_int_flag::W`](W) writer structure"]
impl crate::Writable for R8SpiIntFlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_INT_FLAG to value 0x40"]
impl crate::Resettable for R8SpiIntFlagSpec {
const RESET_VALUE: u8 = 0x40;
}
}
#[doc = "R8_SPI_FIFO_COUNT (rw) register accessor: RW, SPI FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_fifo_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_fifo_count`] module"]
#[doc(alias = "R8_SPI_FIFO_COUNT")]
pub type R8SpiFifoCount = crate::Reg<r8_spi_fifo_count::R8SpiFifoCountSpec>;
#[doc = "RW, SPI FIFO count status"]
pub mod r8_spi_fifo_count {
#[doc = "Register `R8_SPI_FIFO_COUNT` reader"]
pub type R = crate::R<R8SpiFifoCountSpec>;
#[doc = "Register `R8_SPI_FIFO_COUNT` writer"]
pub type W = crate::W<R8SpiFifoCountSpec>;
#[doc = "Field `R8_SPI_FIFO_COUNT` reader - RW, SPI FIFO count status"]
pub type R8SpiFifoCountR = crate::FieldReader;
#[doc = "Field `R8_SPI_FIFO_COUNT` writer - RW, SPI FIFO count status"]
pub type R8SpiFifoCountW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - RW, SPI FIFO count status"]
#[inline(always)]
pub fn r8_spi_fifo_count(&self) -> R8SpiFifoCountR {
R8SpiFifoCountR::new(self.bits & 0x0f)
}
}
impl W {
#[doc = "Bits 0:3 - RW, SPI FIFO count status"]
#[inline(always)]
pub fn r8_spi_fifo_count(&mut self) -> R8SpiFifoCountW<R8SpiFifoCountSpec> {
R8SpiFifoCountW::new(self, 0)
}
}
#[doc = "RW, SPI FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_fifo_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiFifoCountSpec;
impl crate::RegisterSpec for R8SpiFifoCountSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_fifo_count::R`](R) reader structure"]
impl crate::Readable for R8SpiFifoCountSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_fifo_count::W`](W) writer structure"]
impl crate::Writable for R8SpiFifoCountSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_FIFO_COUNT to value 0"]
impl crate::Resettable for R8SpiFifoCountSpec {}
}
#[doc = "R8_SPI_INT_TYPE (rw) register accessor: RW, SPI interrupt trigger mode selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_int_type`] module"]
#[doc(alias = "R8_SPI_INT_TYPE")]
pub type R8SpiIntType = crate::Reg<r8_spi_int_type::R8SpiIntTypeSpec>;
#[doc = "RW, SPI interrupt trigger mode selection register"]
pub mod r8_spi_int_type {
#[doc = "Register `R8_SPI_INT_TYPE` reader"]
pub type R = crate::R<R8SpiIntTypeSpec>;
#[doc = "Register `R8_SPI_INT_TYPE` writer"]
pub type W = crate::W<R8SpiIntTypeSpec>;
#[doc = "Field `RB_SPI_INT_TYPE` reader - RW, SPI interrupt trigger mode selection"]
pub type RbSpiIntTypeR = crate::FieldReader;
#[doc = "Field `RB_SPI_INT_TYPE` writer - RW, SPI interrupt trigger mode selection"]
pub type RbSpiIntTypeW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:4 - RW, SPI interrupt trigger mode selection"]
#[inline(always)]
pub fn rb_spi_int_type(&self) -> RbSpiIntTypeR {
RbSpiIntTypeR::new(self.bits & 0x1f)
}
}
impl W {
#[doc = "Bits 0:4 - RW, SPI interrupt trigger mode selection"]
#[inline(always)]
pub fn rb_spi_int_type(&mut self) -> RbSpiIntTypeW<R8SpiIntTypeSpec> {
RbSpiIntTypeW::new(self, 0)
}
}
#[doc = "RW, SPI interrupt trigger mode selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiIntTypeSpec;
impl crate::RegisterSpec for R8SpiIntTypeSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_int_type::R`](R) reader structure"]
impl crate::Readable for R8SpiIntTypeSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_int_type::W`](W) writer structure"]
impl crate::Writable for R8SpiIntTypeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_INT_TYPE to value 0"]
impl crate::Resettable for R8SpiIntTypeSpec {}
}
#[doc = "R8_SPI_INTER1_EN (rw) register accessor: RW, SPI Interrupt 1 Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_inter1_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_inter1_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_inter1_en`] module"]
#[doc(alias = "R8_SPI_INTER1_EN")]
pub type R8SpiInter1En = crate::Reg<r8_spi_inter1_en::R8SpiInter1EnSpec>;
#[doc = "RW, SPI Interrupt 1 Enable Register"]
pub mod r8_spi_inter1_en {
#[doc = "Register `R8_SPI_INTER1_EN` reader"]
pub type R = crate::R<R8SpiInter1EnSpec>;
#[doc = "Register `R8_SPI_INTER1_EN` writer"]
pub type W = crate::W<R8SpiInter1EnSpec>;
#[doc = "Field `RB_SPI_IE_FIFO_EMPTY` reader - RW, Current FIFO data air break enable"]
pub type RbSpiIeFifoEmptyR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FIFO_EMPTY` writer - RW, Current FIFO data air break enable"]
pub type RbSpiIeFifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_FIFO_FULL` reader - RW, Current FIFO data full interrupt enabled"]
pub type RbSpiIeFifoFullR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FIFO_FULL` writer - RW, Current FIFO data full interrupt enabled"]
pub type RbSpiIeFifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Current FIFO data air break enable"]
#[inline(always)]
pub fn rb_spi_ie_fifo_empty(&self) -> RbSpiIeFifoEmptyR {
RbSpiIeFifoEmptyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Current FIFO data full interrupt enabled"]
#[inline(always)]
pub fn rb_spi_ie_fifo_full(&self) -> RbSpiIeFifoFullR {
RbSpiIeFifoFullR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Current FIFO data air break enable"]
#[inline(always)]
pub fn rb_spi_ie_fifo_empty(&mut self) -> RbSpiIeFifoEmptyW<R8SpiInter1EnSpec> {
RbSpiIeFifoEmptyW::new(self, 0)
}
#[doc = "Bit 1 - RW, Current FIFO data full interrupt enabled"]
#[inline(always)]
pub fn rb_spi_ie_fifo_full(&mut self) -> RbSpiIeFifoFullW<R8SpiInter1EnSpec> {
RbSpiIeFifoFullW::new(self, 1)
}
}
#[doc = "RW, SPI Interrupt 1 Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_inter1_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_inter1_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiInter1EnSpec;
impl crate::RegisterSpec for R8SpiInter1EnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_inter1_en::R`](R) reader structure"]
impl crate::Readable for R8SpiInter1EnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_inter1_en::W`](W) writer structure"]
impl crate::Writable for R8SpiInter1EnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_INTER1_EN to value 0"]
impl crate::Resettable for R8SpiInter1EnSpec {}
}
#[doc = "R8_SPI_INT1_FLAG (rw) register accessor: RW1, SPI interrupt 1 flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int1_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int1_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_int1_flag`] module"]
#[doc(alias = "R8_SPI_INT1_FLAG")]
pub type R8SpiInt1Flag = crate::Reg<r8_spi_int1_flag::R8SpiInt1FlagSpec>;
#[doc = "RW1, SPI interrupt 1 flag register"]
pub mod r8_spi_int1_flag {
#[doc = "Register `R8_SPI_INT1_FLAG` reader"]
pub type R = crate::R<R8SpiInt1FlagSpec>;
#[doc = "Register `R8_SPI_INT1_FLAG` writer"]
pub type W = crate::W<R8SpiInt1FlagSpec>;
#[doc = "Field `RB_SPI_IF_FIFO_EMPTY` reader - RW1, Current FIFO data empty flag bit"]
pub type RbSpiIfFifoEmptyR = crate::BitReader;
#[doc = "Field `RB_SPI_IF_FIFO_EMPTY` writer - RW1, Current FIFO data empty flag bit"]
pub type RbSpiIfFifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_SPI_IE_FIFO_FULL` reader - RW1, Current FIFO data full flag"]
pub type RbSpiIeFifoFullR = crate::BitReader;
#[doc = "Field `RB_SPI_IE_FIFO_FULL` writer - RW1, Current FIFO data full flag"]
pub type RbSpiIeFifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW1, Current FIFO data empty flag bit"]
#[inline(always)]
pub fn rb_spi_if_fifo_empty(&self) -> RbSpiIfFifoEmptyR {
RbSpiIfFifoEmptyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW1, Current FIFO data full flag"]
#[inline(always)]
pub fn rb_spi_ie_fifo_full(&self) -> RbSpiIeFifoFullR {
RbSpiIeFifoFullR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW1, Current FIFO data empty flag bit"]
#[inline(always)]
pub fn rb_spi_if_fifo_empty(&mut self) -> RbSpiIfFifoEmptyW<R8SpiInt1FlagSpec> {
RbSpiIfFifoEmptyW::new(self, 0)
}
#[doc = "Bit 1 - RW1, Current FIFO data full flag"]
#[inline(always)]
pub fn rb_spi_ie_fifo_full(&mut self) -> RbSpiIeFifoFullW<R8SpiInt1FlagSpec> {
RbSpiIeFifoFullW::new(self, 1)
}
}
#[doc = "RW1, SPI interrupt 1 flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_int1_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_int1_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiInt1FlagSpec;
impl crate::RegisterSpec for R8SpiInt1FlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_int1_flag::R`](R) reader structure"]
impl crate::Readable for R8SpiInt1FlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_int1_flag::W`](W) writer structure"]
impl crate::Writable for R8SpiInt1FlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_INT1_FLAG to value 0"]
impl crate::Resettable for R8SpiInt1FlagSpec {}
}
#[doc = "R16_SPI_TOTAL_CNT (rw) register accessor: RW, SPI total byte count, only low 12 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_spi_total_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_spi_total_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_spi_total_cnt`] module"]
#[doc(alias = "R16_SPI_TOTAL_CNT")]
pub type R16SpiTotalCnt = crate::Reg<r16_spi_total_cnt::R16SpiTotalCntSpec>;
#[doc = "RW, SPI total byte count, only low 12 bit"]
pub mod r16_spi_total_cnt {
#[doc = "Register `R16_SPI_TOTAL_CNT` reader"]
pub type R = crate::R<R16SpiTotalCntSpec>;
#[doc = "Register `R16_SPI_TOTAL_CNT` writer"]
pub type W = crate::W<R16SpiTotalCntSpec>;
#[doc = "Field `R16_SPI_TOTAL_CNT` reader - RW, SPI total byte count, only low 12 bit"]
pub type R16SpiTotalCntR = crate::FieldReader<u16>;
#[doc = "Field `R16_SPI_TOTAL_CNT` writer - RW, SPI total byte count, only low 12 bit"]
pub type R16SpiTotalCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - RW, SPI total byte count, only low 12 bit"]
#[inline(always)]
pub fn r16_spi_total_cnt(&self) -> R16SpiTotalCntR {
R16SpiTotalCntR::new(self.bits & 0x0fff)
}
}
impl W {
#[doc = "Bits 0:11 - RW, SPI total byte count, only low 12 bit"]
#[inline(always)]
pub fn r16_spi_total_cnt(&mut self) -> R16SpiTotalCntW<R16SpiTotalCntSpec> {
R16SpiTotalCntW::new(self, 0)
}
}
#[doc = "RW, SPI total byte count, only low 12 bit\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_spi_total_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_spi_total_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16SpiTotalCntSpec;
impl crate::RegisterSpec for R16SpiTotalCntSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_spi_total_cnt::R`](R) reader structure"]
impl crate::Readable for R16SpiTotalCntSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_spi_total_cnt::W`](W) writer structure"]
impl crate::Writable for R16SpiTotalCntSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_SPI_TOTAL_CNT to value 0"]
impl crate::Resettable for R16SpiTotalCntSpec {}
}
#[doc = "R8_SPI_FIFO (rw) register accessor: RO/WO, SPI FIFO register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_fifo`] module"]
#[doc(alias = "R8_SPI_FIFO")]
pub type R8SpiFifo = crate::Reg<r8_spi_fifo::R8SpiFifoSpec>;
#[doc = "RO/WO, SPI FIFO register"]
pub mod r8_spi_fifo {
#[doc = "Register `R8_SPI_FIFO` reader"]
pub type R = crate::R<R8SpiFifoSpec>;
#[doc = "Register `R8_SPI_FIFO` writer"]
pub type W = crate::W<R8SpiFifoSpec>;
#[doc = "Field `R8_SPI_FIFO` reader - RO/WO, SPI FIFO register"]
pub type R8SpiFifoR = crate::FieldReader;
#[doc = "Field `R8_SPI_FIFO` writer - RO/WO, SPI FIFO register"]
pub type R8SpiFifoW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RO/WO, SPI FIFO register"]
#[inline(always)]
pub fn r8_spi_fifo(&self) -> R8SpiFifoR {
R8SpiFifoR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - RO/WO, SPI FIFO register"]
#[inline(always)]
pub fn r8_spi_fifo(&mut self) -> R8SpiFifoW<R8SpiFifoSpec> {
R8SpiFifoW::new(self, 0)
}
}
#[doc = "RO/WO, SPI FIFO register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_spi_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiFifoSpec;
impl crate::RegisterSpec for R8SpiFifoSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_fifo::R`](R) reader structure"]
impl crate::Readable for R8SpiFifoSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_spi_fifo::W`](W) writer structure"]
impl crate::Writable for R8SpiFifoSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_SPI_FIFO to value 0"]
impl crate::Resettable for R8SpiFifoSpec {}
}
#[doc = "R8_SPI_FIFO_COUNT1 (r) register accessor: RO, SPI FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo_count1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_spi_fifo_count1`] module"]
#[doc(alias = "R8_SPI_FIFO_COUNT1")]
pub type R8SpiFifoCount1 = crate::Reg<r8_spi_fifo_count1::R8SpiFifoCount1Spec>;
#[doc = "RO, SPI FIFO count status"]
pub mod r8_spi_fifo_count1 {
#[doc = "Register `R8_SPI_FIFO_COUNT1` reader"]
pub type R = crate::R<R8SpiFifoCount1Spec>;
#[doc = "Field `R8_SPI_FIFO_COUNT1` reader - RO, SPI FIFO count status"]
pub type R8SpiFifoCount1R = crate::FieldReader;
impl R {
#[doc = "Bits 0:3 - RO, SPI FIFO count status"]
#[inline(always)]
pub fn r8_spi_fifo_count1(&self) -> R8SpiFifoCount1R {
R8SpiFifoCount1R::new(self.bits & 0x0f)
}
}
#[doc = "RO, SPI FIFO count status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_spi_fifo_count1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8SpiFifoCount1Spec;
impl crate::RegisterSpec for R8SpiFifoCount1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_spi_fifo_count1::R`](R) reader structure"]
impl crate::Readable for R8SpiFifoCount1Spec {}
#[doc = "`reset()` method sets R8_SPI_FIFO_COUNT1 to value 0"]
impl crate::Resettable for R8SpiFifoCount1Spec {}
}
#[doc = "R32_SPI_DMA_NOW (rw) register accessor: RW, SPI DMA current address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_now::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_now::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_spi_dma_now`] module"]
#[doc(alias = "R32_SPI_DMA_NOW")]
pub type R32SpiDmaNow = crate::Reg<r32_spi_dma_now::R32SpiDmaNowSpec>;
#[doc = "RW, SPI DMA current address"]
pub mod r32_spi_dma_now {
#[doc = "Register `R32_SPI_DMA_NOW` reader"]
pub type R = crate::R<R32SpiDmaNowSpec>;
#[doc = "Register `R32_SPI_DMA_NOW` writer"]
pub type W = crate::W<R32SpiDmaNowSpec>;
#[doc = "Field `RB_SPI_DMA_NOW` reader - RW, SPI DMA current address"]
pub type RbSpiDmaNowR = crate::FieldReader<u16>;
#[doc = "Field `RB_SPI_DMA_NOW` writer - RW, SPI DMA current address"]
pub type RbSpiDmaNowW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:13 - RW, SPI DMA current address"]
#[inline(always)]
pub fn rb_spi_dma_now(&self) -> RbSpiDmaNowR {
RbSpiDmaNowR::new((self.bits & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bits 0:13 - RW, SPI DMA current address"]
#[inline(always)]
pub fn rb_spi_dma_now(&mut self) -> RbSpiDmaNowW<R32SpiDmaNowSpec> {
RbSpiDmaNowW::new(self, 0)
}
}
#[doc = "RW, SPI DMA current address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_now::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_now::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32SpiDmaNowSpec;
impl crate::RegisterSpec for R32SpiDmaNowSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_spi_dma_now::R`](R) reader structure"]
impl crate::Readable for R32SpiDmaNowSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_spi_dma_now::W`](W) writer structure"]
impl crate::Writable for R32SpiDmaNowSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_SPI_DMA_NOW to value 0"]
impl crate::Resettable for R32SpiDmaNowSpec {}
}
#[doc = "R32_SPI_DMA_BEG (rw) register accessor: RW, SPI DMA begin address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_beg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_beg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_spi_dma_beg`] module"]
#[doc(alias = "R32_SPI_DMA_BEG")]
pub type R32SpiDmaBeg = crate::Reg<r32_spi_dma_beg::R32SpiDmaBegSpec>;
#[doc = "RW, SPI DMA begin address"]
pub mod r32_spi_dma_beg {
#[doc = "Register `R32_SPI_DMA_BEG` reader"]
pub type R = crate::R<R32SpiDmaBegSpec>;
#[doc = "Register `R32_SPI_DMA_BEG` writer"]
pub type W = crate::W<R32SpiDmaBegSpec>;
#[doc = "Field `R32_SPI_DMA_BEG` reader - RW, SPI DMA begin address"]
pub type R32SpiDmaBegR = crate::FieldReader<u16>;
#[doc = "Field `R32_SPI_DMA_BEG` writer - RW, SPI DMA begin address"]
pub type R32SpiDmaBegW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:13 - RW, SPI DMA begin address"]
#[inline(always)]
pub fn r32_spi_dma_beg(&self) -> R32SpiDmaBegR {
R32SpiDmaBegR::new((self.bits & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bits 0:13 - RW, SPI DMA begin address"]
#[inline(always)]
pub fn r32_spi_dma_beg(&mut self) -> R32SpiDmaBegW<R32SpiDmaBegSpec> {
R32SpiDmaBegW::new(self, 0)
}
}
#[doc = "RW, SPI DMA begin address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_beg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_beg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32SpiDmaBegSpec;
impl crate::RegisterSpec for R32SpiDmaBegSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_spi_dma_beg::R`](R) reader structure"]
impl crate::Readable for R32SpiDmaBegSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_spi_dma_beg::W`](W) writer structure"]
impl crate::Writable for R32SpiDmaBegSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_SPI_DMA_BEG to value 0"]
impl crate::Resettable for R32SpiDmaBegSpec {}
}
#[doc = "R32_SPI_DMA_END (rw) register accessor: RW, SPI DMA end address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_spi_dma_end`] module"]
#[doc(alias = "R32_SPI_DMA_END")]
pub type R32SpiDmaEnd = crate::Reg<r32_spi_dma_end::R32SpiDmaEndSpec>;
#[doc = "RW, SPI DMA end address"]
pub mod r32_spi_dma_end {
#[doc = "Register `R32_SPI_DMA_END` reader"]
pub type R = crate::R<R32SpiDmaEndSpec>;
#[doc = "Register `R32_SPI_DMA_END` writer"]
pub type W = crate::W<R32SpiDmaEndSpec>;
#[doc = "Field `R32_SPI_DMA_END` reader - RW, SPI DMA end address"]
pub type R32SpiDmaEndR = crate::FieldReader<u16>;
#[doc = "Field `R32_SPI_DMA_END` writer - RW, SPI DMA end address"]
pub type R32SpiDmaEndW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:13 - RW, SPI DMA end address"]
#[inline(always)]
pub fn r32_spi_dma_end(&self) -> R32SpiDmaEndR {
R32SpiDmaEndR::new((self.bits & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bits 0:13 - RW, SPI DMA end address"]
#[inline(always)]
pub fn r32_spi_dma_end(&mut self) -> R32SpiDmaEndW<R32SpiDmaEndSpec> {
R32SpiDmaEndW::new(self, 0)
}
}
#[doc = "RW, SPI DMA end address\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_spi_dma_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_spi_dma_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32SpiDmaEndSpec;
impl crate::RegisterSpec for R32SpiDmaEndSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_spi_dma_end::R`](R) reader structure"]
impl crate::Readable for R32SpiDmaEndSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_spi_dma_end::W`](W) writer structure"]
impl crate::Writable for R32SpiDmaEndSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_SPI_DMA_END to value 0"]
impl crate::Resettable for R32SpiDmaEndSpec {}
}
}
#[doc = "I2C register"]
pub type I2c = crate::Periph<i2c::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for I2c {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c").finish()
}
}
#[doc = "I2C register"]
pub mod i2c {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r16_i2c_ctrl1: R16I2cCtrl1,
_reserved1: [u8; 0x02],
r16_i2c_ctrl2: R16I2cCtrl2,
_reserved2: [u8; 0x02],
r16_i2c_oaddr1: R16I2cOaddr1,
_reserved3: [u8; 0x02],
r16_i2c_oaddr2: R16I2cOaddr2,
_reserved4: [u8; 0x02],
r16_i2c_datar: R16I2cDatar,
_reserved5: [u8; 0x02],
r16_i2c_star1: R16I2cStar1,
_reserved6: [u8; 0x02],
r16_i2c_star2: R16I2cStar2,
_reserved7: [u8; 0x02],
r16_i2c_ckcfgr: R16I2cCkcfgr,
_reserved8: [u8; 0x02],
r16_i2c_rtr: R16I2cRtr,
}
impl RegisterBlock {
#[doc = "0x00 - RW, I2C control 1"]
#[inline(always)]
pub const fn r16_i2c_ctrl1(&self) -> &R16I2cCtrl1 {
&self.r16_i2c_ctrl1
}
#[doc = "0x04 - RW, I2C control 2"]
#[inline(always)]
pub const fn r16_i2c_ctrl2(&self) -> &R16I2cCtrl2 {
&self.r16_i2c_ctrl2
}
#[doc = "0x08 - RW, I2C own address register 1"]
#[inline(always)]
pub const fn r16_i2c_oaddr1(&self) -> &R16I2cOaddr1 {
&self.r16_i2c_oaddr1
}
#[doc = "0x0c - RW, I2C own address register 2"]
#[inline(always)]
pub const fn r16_i2c_oaddr2(&self) -> &R16I2cOaddr2 {
&self.r16_i2c_oaddr2
}
#[doc = "0x10 - RW, I2C data register"]
#[inline(always)]
pub const fn r16_i2c_datar(&self) -> &R16I2cDatar {
&self.r16_i2c_datar
}
#[doc = "0x14 - RO, I2C stauts register 1"]
#[inline(always)]
pub const fn r16_i2c_star1(&self) -> &R16I2cStar1 {
&self.r16_i2c_star1
}
#[doc = "0x18 - RO, I2C status register 2"]
#[inline(always)]
pub const fn r16_i2c_star2(&self) -> &R16I2cStar2 {
&self.r16_i2c_star2
}
#[doc = "0x1c - RW, I2C clock control register"]
#[inline(always)]
pub const fn r16_i2c_ckcfgr(&self) -> &R16I2cCkcfgr {
&self.r16_i2c_ckcfgr
}
#[doc = "0x20 - RW, I2C trise register"]
#[inline(always)]
pub const fn r16_i2c_rtr(&self) -> &R16I2cRtr {
&self.r16_i2c_rtr
}
}
#[doc = "R16_I2C_CTRL1 (rw) register accessor: RW, I2C control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_ctrl1`] module"]
#[doc(alias = "R16_I2C_CTRL1")]
pub type R16I2cCtrl1 = crate::Reg<r16_i2c_ctrl1::R16I2cCtrl1Spec>;
#[doc = "RW, I2C control 1"]
pub mod r16_i2c_ctrl1 {
#[doc = "Register `R16_I2C_CTRL1` reader"]
pub type R = crate::R<R16I2cCtrl1Spec>;
#[doc = "Register `R16_I2C_CTRL1` writer"]
pub type W = crate::W<R16I2cCtrl1Spec>;
#[doc = "Field `RB_I2C_PE` reader - RW, Peripheral enable"]
pub type RbI2cPeR = crate::BitReader;
#[doc = "Field `RB_I2C_PE` writer - RW, Peripheral enable"]
pub type RbI2cPeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_SMBUS` reader - RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode"]
pub type RbI2cSmbusR = crate::BitReader;
#[doc = "Field `RB_I2C_SMBUS` writer - RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode"]
pub type RbI2cSmbusW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_SMBTYPE` reader - RW, SMBus type: 0=Device, 1=Host"]
pub type RbI2cSmbtypeR = crate::BitReader;
#[doc = "Field `RB_I2C_SMBTYPE` writer - RW, SMBus type: 0=Device, 1=Host"]
pub type RbI2cSmbtypeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_EBARP` reader - RW, ARP enable"]
pub type RbI2cEbarpR = crate::BitReader;
#[doc = "Field `RB_I2C_EBARP` writer - RW, ARP enable"]
pub type RbI2cEbarpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ENPEC` reader - RW, PEC ebable"]
pub type RbI2cEnpecR = crate::BitReader;
#[doc = "Field `RB_I2C_ENPEC` writer - RW, PEC ebable"]
pub type RbI2cEnpecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ENGC` reader - RW, General call enable"]
pub type RbI2cEngcR = crate::BitReader;
#[doc = "Field `RB_I2C_ENGC` writer - RW, General call enable"]
pub type RbI2cEngcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_NOSTRETCH` reader - RW, Clock stretching disable (Slave mode)"]
pub type RbI2cNostretchR = crate::BitReader;
#[doc = "Field `RB_I2C_NOSTRETCH` writer - RW, Clock stretching disable (Slave mode)"]
pub type RbI2cNostretchW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_START` reader - RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free"]
pub type RbI2cStartR = crate::BitReader;
#[doc = "Field `RB_I2C_START` writer - RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free"]
pub type RbI2cStartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_STOP` reader - RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer"]
pub type RbI2cStopR = crate::BitReader;
#[doc = "Field `RB_I2C_STOP` writer - RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer"]
pub type RbI2cStopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ACK` reader - RW, Acknowledge enable"]
pub type RbI2cAckR = crate::BitReader;
#[doc = "Field `RB_I2C_ACK` writer - RW, Acknowledge enable"]
pub type RbI2cAckW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_POS` reader - RW, Acknowledge/PEC Position (for data reception)"]
pub type RbI2cPosR = crate::BitReader;
#[doc = "Field `RB_I2C_POS` writer - RW, Acknowledge/PEC Position (for data reception)"]
pub type RbI2cPosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_PEC` reader - RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode)"]
pub type RbI2cPecR = crate::BitReader;
#[doc = "Field `RB_I2C_PEC` writer - RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode)"]
pub type RbI2cPecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ALERT` reader - RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low."]
pub type RbI2cAlertR = crate::BitReader;
#[doc = "Field `RB_I2C_ALERT` writer - RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low."]
pub type RbI2cAlertW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_SWRST` reader - RW, Software reset"]
pub type RbI2cSwrstR = crate::BitReader;
#[doc = "Field `RB_I2C_SWRST` writer - RW, Software reset"]
pub type RbI2cSwrstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, Peripheral enable"]
#[inline(always)]
pub fn rb_i2c_pe(&self) -> RbI2cPeR {
RbI2cPeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode"]
#[inline(always)]
pub fn rb_i2c_smbus(&self) -> RbI2cSmbusR {
RbI2cSmbusR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - RW, SMBus type: 0=Device, 1=Host"]
#[inline(always)]
pub fn rb_i2c_smbtype(&self) -> RbI2cSmbtypeR {
RbI2cSmbtypeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, ARP enable"]
#[inline(always)]
pub fn rb_i2c_ebarp(&self) -> RbI2cEbarpR {
RbI2cEbarpR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RW, PEC ebable"]
#[inline(always)]
pub fn rb_i2c_enpec(&self) -> RbI2cEnpecR {
RbI2cEnpecR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RW, General call enable"]
#[inline(always)]
pub fn rb_i2c_engc(&self) -> RbI2cEngcR {
RbI2cEngcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RW, Clock stretching disable (Slave mode)"]
#[inline(always)]
pub fn rb_i2c_nostretch(&self) -> RbI2cNostretchR {
RbI2cNostretchR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free"]
#[inline(always)]
pub fn rb_i2c_start(&self) -> RbI2cStartR {
RbI2cStartR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer"]
#[inline(always)]
pub fn rb_i2c_stop(&self) -> RbI2cStopR {
RbI2cStopR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - RW, Acknowledge enable"]
#[inline(always)]
pub fn rb_i2c_ack(&self) -> RbI2cAckR {
RbI2cAckR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - RW, Acknowledge/PEC Position (for data reception)"]
#[inline(always)]
pub fn rb_i2c_pos(&self) -> RbI2cPosR {
RbI2cPosR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode)"]
#[inline(always)]
pub fn rb_i2c_pec(&self) -> RbI2cPecR {
RbI2cPecR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low."]
#[inline(always)]
pub fn rb_i2c_alert(&self) -> RbI2cAlertR {
RbI2cAlertR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15 - RW, Software reset"]
#[inline(always)]
pub fn rb_i2c_swrst(&self) -> RbI2cSwrstR {
RbI2cSwrstR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, Peripheral enable"]
#[inline(always)]
pub fn rb_i2c_pe(&mut self) -> RbI2cPeW<R16I2cCtrl1Spec> {
RbI2cPeW::new(self, 0)
}
#[doc = "Bit 1 - RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode"]
#[inline(always)]
pub fn rb_i2c_smbus(&mut self) -> RbI2cSmbusW<R16I2cCtrl1Spec> {
RbI2cSmbusW::new(self, 1)
}
#[doc = "Bit 3 - RW, SMBus type: 0=Device, 1=Host"]
#[inline(always)]
pub fn rb_i2c_smbtype(&mut self) -> RbI2cSmbtypeW<R16I2cCtrl1Spec> {
RbI2cSmbtypeW::new(self, 3)
}
#[doc = "Bit 4 - RW, ARP enable"]
#[inline(always)]
pub fn rb_i2c_ebarp(&mut self) -> RbI2cEbarpW<R16I2cCtrl1Spec> {
RbI2cEbarpW::new(self, 4)
}
#[doc = "Bit 5 - RW, PEC ebable"]
#[inline(always)]
pub fn rb_i2c_enpec(&mut self) -> RbI2cEnpecW<R16I2cCtrl1Spec> {
RbI2cEnpecW::new(self, 5)
}
#[doc = "Bit 6 - RW, General call enable"]
#[inline(always)]
pub fn rb_i2c_engc(&mut self) -> RbI2cEngcW<R16I2cCtrl1Spec> {
RbI2cEngcW::new(self, 6)
}
#[doc = "Bit 7 - RW, Clock stretching disable (Slave mode)"]
#[inline(always)]
pub fn rb_i2c_nostretch(&mut self) -> RbI2cNostretchW<R16I2cCtrl1Spec> {
RbI2cNostretchW::new(self, 7)
}
#[doc = "Bit 8 - RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free"]
#[inline(always)]
pub fn rb_i2c_start(&mut self) -> RbI2cStartW<R16I2cCtrl1Spec> {
RbI2cStartW::new(self, 8)
}
#[doc = "Bit 9 - RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer"]
#[inline(always)]
pub fn rb_i2c_stop(&mut self) -> RbI2cStopW<R16I2cCtrl1Spec> {
RbI2cStopW::new(self, 9)
}
#[doc = "Bit 10 - RW, Acknowledge enable"]
#[inline(always)]
pub fn rb_i2c_ack(&mut self) -> RbI2cAckW<R16I2cCtrl1Spec> {
RbI2cAckW::new(self, 10)
}
#[doc = "Bit 11 - RW, Acknowledge/PEC Position (for data reception)"]
#[inline(always)]
pub fn rb_i2c_pos(&mut self) -> RbI2cPosW<R16I2cCtrl1Spec> {
RbI2cPosW::new(self, 11)
}
#[doc = "Bit 12 - RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode)"]
#[inline(always)]
pub fn rb_i2c_pec(&mut self) -> RbI2cPecW<R16I2cCtrl1Spec> {
RbI2cPecW::new(self, 12)
}
#[doc = "Bit 13 - RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low."]
#[inline(always)]
pub fn rb_i2c_alert(&mut self) -> RbI2cAlertW<R16I2cCtrl1Spec> {
RbI2cAlertW::new(self, 13)
}
#[doc = "Bit 15 - RW, Software reset"]
#[inline(always)]
pub fn rb_i2c_swrst(&mut self) -> RbI2cSwrstW<R16I2cCtrl1Spec> {
RbI2cSwrstW::new(self, 15)
}
}
#[doc = "RW, I2C control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cCtrl1Spec;
impl crate::RegisterSpec for R16I2cCtrl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_ctrl1::R`](R) reader structure"]
impl crate::Readable for R16I2cCtrl1Spec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_ctrl1::W`](W) writer structure"]
impl crate::Writable for R16I2cCtrl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_CTRL1 to value 0"]
impl crate::Resettable for R16I2cCtrl1Spec {}
}
#[doc = "R16_I2C_CTRL2 (rw) register accessor: RW, I2C control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_ctrl2`] module"]
#[doc(alias = "R16_I2C_CTRL2")]
pub type R16I2cCtrl2 = crate::Reg<r16_i2c_ctrl2::R16I2cCtrl2Spec>;
#[doc = "RW, I2C control 2"]
pub mod r16_i2c_ctrl2 {
#[doc = "Register `R16_I2C_CTRL2` reader"]
pub type R = crate::R<R16I2cCtrl2Spec>;
#[doc = "Register `R16_I2C_CTRL2` writer"]
pub type W = crate::W<R16I2cCtrl2Spec>;
#[doc = "Field `RB_I2C_FREQ` reader - RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz"]
pub type RbI2cFreqR = crate::FieldReader;
#[doc = "Field `RB_I2C_FREQ` writer - RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz"]
pub type RbI2cFreqW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RB_I2C_ITERREN` reader - RW, Error interrupt enable"]
pub type RbI2cIterrenR = crate::BitReader;
#[doc = "Field `RB_I2C_ITERREN` writer - RW, Error interrupt enable"]
pub type RbI2cIterrenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ITEVTEN` reader - RW, Event interrupt enable"]
pub type RbI2cItevtenR = crate::BitReader;
#[doc = "Field `RB_I2C_ITEVTEN` writer - RW, Event interrupt enable"]
pub type RbI2cItevtenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ITBUFEN` reader - RW, Buffer interrupt enable"]
pub type RbI2cItbufenR = crate::BitReader;
#[doc = "Field `RB_I2C_ITBUFEN` writer - RW, Buffer interrupt enable"]
pub type RbI2cItbufenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:5 - RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz"]
#[inline(always)]
pub fn rb_i2c_freq(&self) -> RbI2cFreqR {
RbI2cFreqR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bit 8 - RW, Error interrupt enable"]
#[inline(always)]
pub fn rb_i2c_iterren(&self) -> RbI2cIterrenR {
RbI2cIterrenR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - RW, Event interrupt enable"]
#[inline(always)]
pub fn rb_i2c_itevten(&self) -> RbI2cItevtenR {
RbI2cItevtenR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - RW, Buffer interrupt enable"]
#[inline(always)]
pub fn rb_i2c_itbufen(&self) -> RbI2cItbufenR {
RbI2cItbufenR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:5 - RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz"]
#[inline(always)]
pub fn rb_i2c_freq(&mut self) -> RbI2cFreqW<R16I2cCtrl2Spec> {
RbI2cFreqW::new(self, 0)
}
#[doc = "Bit 8 - RW, Error interrupt enable"]
#[inline(always)]
pub fn rb_i2c_iterren(&mut self) -> RbI2cIterrenW<R16I2cCtrl2Spec> {
RbI2cIterrenW::new(self, 8)
}
#[doc = "Bit 9 - RW, Event interrupt enable"]
#[inline(always)]
pub fn rb_i2c_itevten(&mut self) -> RbI2cItevtenW<R16I2cCtrl2Spec> {
RbI2cItevtenW::new(self, 9)
}
#[doc = "Bit 10 - RW, Buffer interrupt enable"]
#[inline(always)]
pub fn rb_i2c_itbufen(&mut self) -> RbI2cItbufenW<R16I2cCtrl2Spec> {
RbI2cItbufenW::new(self, 10)
}
}
#[doc = "RW, I2C control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cCtrl2Spec;
impl crate::RegisterSpec for R16I2cCtrl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_ctrl2::R`](R) reader structure"]
impl crate::Readable for R16I2cCtrl2Spec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_ctrl2::W`](W) writer structure"]
impl crate::Writable for R16I2cCtrl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_CTRL2 to value 0"]
impl crate::Resettable for R16I2cCtrl2Spec {}
}
#[doc = "R16_I2C_OADDR1 (rw) register accessor: RW, I2C own address register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_oaddr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_oaddr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_oaddr1`] module"]
#[doc(alias = "R16_I2C_OADDR1")]
pub type R16I2cOaddr1 = crate::Reg<r16_i2c_oaddr1::R16I2cOaddr1Spec>;
#[doc = "RW, I2C own address register 1"]
pub mod r16_i2c_oaddr1 {
#[doc = "Register `R16_I2C_OADDR1` reader"]
pub type R = crate::R<R16I2cOaddr1Spec>;
#[doc = "Register `R16_I2C_OADDR1` writer"]
pub type W = crate::W<R16I2cOaddr1Spec>;
#[doc = "Field `RB_I2C_ADD0` reader - RW, bit0 of address in 10-bit addressing mode"]
pub type RbI2cAdd0R = crate::BitReader;
#[doc = "Field `RB_I2C_ADD0` writer - RW, bit0 of address in 10-bit addressing mode"]
pub type RbI2cAdd0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ADD7_1` reader - RW, bit\\[7:1\\] of address"]
pub type RbI2cAdd7_1R = crate::FieldReader;
#[doc = "Field `RB_I2C_ADD7_1` writer - RW, bit\\[7:1\\] of address"]
pub type RbI2cAdd7_1W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RB_I2C_ADD9_8` reader - RW, bit\\[9:8\\] of address in 10-bit addressing mode"]
pub type RbI2cAdd9_8R = crate::FieldReader;
#[doc = "Field `RB_I2C_ADD9_8` writer - RW, bit\\[9:8\\] of address in 10-bit addressing mode"]
pub type RbI2cAdd9_8W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_I2C_ADDMODE` reader - RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address"]
pub type RbI2cAddmodeR = crate::BitReader;
#[doc = "Field `RB_I2C_ADDMODE` writer - RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address"]
pub type RbI2cAddmodeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, bit0 of address in 10-bit addressing mode"]
#[inline(always)]
pub fn rb_i2c_add0(&self) -> RbI2cAdd0R {
RbI2cAdd0R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7 - RW, bit\\[7:1\\] of address"]
#[inline(always)]
pub fn rb_i2c_add7_1(&self) -> RbI2cAdd7_1R {
RbI2cAdd7_1R::new(((self.bits >> 1) & 0x7f) as u8)
}
#[doc = "Bits 8:9 - RW, bit\\[9:8\\] of address in 10-bit addressing mode"]
#[inline(always)]
pub fn rb_i2c_add9_8(&self) -> RbI2cAdd9_8R {
RbI2cAdd9_8R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 15 - RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address"]
#[inline(always)]
pub fn rb_i2c_addmode(&self) -> RbI2cAddmodeR {
RbI2cAddmodeR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, bit0 of address in 10-bit addressing mode"]
#[inline(always)]
pub fn rb_i2c_add0(&mut self) -> RbI2cAdd0W<R16I2cOaddr1Spec> {
RbI2cAdd0W::new(self, 0)
}
#[doc = "Bits 1:7 - RW, bit\\[7:1\\] of address"]
#[inline(always)]
pub fn rb_i2c_add7_1(&mut self) -> RbI2cAdd7_1W<R16I2cOaddr1Spec> {
RbI2cAdd7_1W::new(self, 1)
}
#[doc = "Bits 8:9 - RW, bit\\[9:8\\] of address in 10-bit addressing mode"]
#[inline(always)]
pub fn rb_i2c_add9_8(&mut self) -> RbI2cAdd9_8W<R16I2cOaddr1Spec> {
RbI2cAdd9_8W::new(self, 8)
}
#[doc = "Bit 15 - RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address"]
#[inline(always)]
pub fn rb_i2c_addmode(&mut self) -> RbI2cAddmodeW<R16I2cOaddr1Spec> {
RbI2cAddmodeW::new(self, 15)
}
}
#[doc = "RW, I2C own address register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_oaddr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_oaddr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cOaddr1Spec;
impl crate::RegisterSpec for R16I2cOaddr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_oaddr1::R`](R) reader structure"]
impl crate::Readable for R16I2cOaddr1Spec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_oaddr1::W`](W) writer structure"]
impl crate::Writable for R16I2cOaddr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_OADDR1 to value 0"]
impl crate::Resettable for R16I2cOaddr1Spec {}
}
#[doc = "R16_I2C_OADDR2 (rw) register accessor: RW, I2C own address register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_oaddr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_oaddr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_oaddr2`] module"]
#[doc(alias = "R16_I2C_OADDR2")]
pub type R16I2cOaddr2 = crate::Reg<r16_i2c_oaddr2::R16I2cOaddr2Spec>;
#[doc = "RW, I2C own address register 2"]
pub mod r16_i2c_oaddr2 {
#[doc = "Register `R16_I2C_OADDR2` reader"]
pub type R = crate::R<R16I2cOaddr2Spec>;
#[doc = "Register `R16_I2C_OADDR2` writer"]
pub type W = crate::W<R16I2cOaddr2Spec>;
#[doc = "Field `RB_I2C_ENDUAL` reader - RW, Dual addressing mode enable"]
pub type RbI2cEndualR = crate::BitReader;
#[doc = "Field `RB_I2C_ENDUAL` writer - RW, Dual addressing mode enable"]
pub type RbI2cEndualW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_ADD2` reader - RW, bit\\[7:1\\] of address2"]
pub type RbI2cAdd2R = crate::FieldReader;
#[doc = "Field `RB_I2C_ADD2` writer - RW, bit\\[7:1\\] of address2"]
pub type RbI2cAdd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bit 0 - RW, Dual addressing mode enable"]
#[inline(always)]
pub fn rb_i2c_endual(&self) -> RbI2cEndualR {
RbI2cEndualR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7 - RW, bit\\[7:1\\] of address2"]
#[inline(always)]
pub fn rb_i2c_add2(&self) -> RbI2cAdd2R {
RbI2cAdd2R::new(((self.bits >> 1) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bit 0 - RW, Dual addressing mode enable"]
#[inline(always)]
pub fn rb_i2c_endual(&mut self) -> RbI2cEndualW<R16I2cOaddr2Spec> {
RbI2cEndualW::new(self, 0)
}
#[doc = "Bits 1:7 - RW, bit\\[7:1\\] of address2"]
#[inline(always)]
pub fn rb_i2c_add2(&mut self) -> RbI2cAdd2W<R16I2cOaddr2Spec> {
RbI2cAdd2W::new(self, 1)
}
}
#[doc = "RW, I2C own address register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_oaddr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_oaddr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cOaddr2Spec;
impl crate::RegisterSpec for R16I2cOaddr2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_oaddr2::R`](R) reader structure"]
impl crate::Readable for R16I2cOaddr2Spec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_oaddr2::W`](W) writer structure"]
impl crate::Writable for R16I2cOaddr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_OADDR2 to value 0"]
impl crate::Resettable for R16I2cOaddr2Spec {}
}
#[doc = "R16_I2C_DATAR (rw) register accessor: RW, I2C data register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_datar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_datar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_datar`] module"]
#[doc(alias = "R16_I2C_DATAR")]
pub type R16I2cDatar = crate::Reg<r16_i2c_datar::R16I2cDatarSpec>;
#[doc = "RW, I2C data register"]
pub mod r16_i2c_datar {
#[doc = "Register `R16_I2C_DATAR` reader"]
pub type R = crate::R<R16I2cDatarSpec>;
#[doc = "Register `R16_I2C_DATAR` writer"]
pub type W = crate::W<R16I2cDatarSpec>;
#[doc = "Field `R16_I2C_DATAR` reader - RW, I2C data register"]
pub type R16I2cDatarR = crate::FieldReader;
#[doc = "Field `R16_I2C_DATAR` writer - RW, I2C data register"]
pub type R16I2cDatarW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, I2C data register"]
#[inline(always)]
pub fn r16_i2c_datar(&self) -> R16I2cDatarR {
R16I2cDatarR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - RW, I2C data register"]
#[inline(always)]
pub fn r16_i2c_datar(&mut self) -> R16I2cDatarW<R16I2cDatarSpec> {
R16I2cDatarW::new(self, 0)
}
}
#[doc = "RW, I2C data register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_datar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_datar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cDatarSpec;
impl crate::RegisterSpec for R16I2cDatarSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_datar::R`](R) reader structure"]
impl crate::Readable for R16I2cDatarSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_datar::W`](W) writer structure"]
impl crate::Writable for R16I2cDatarSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_DATAR to value 0"]
impl crate::Resettable for R16I2cDatarSpec {}
}
#[doc = "R16_I2C_STAR1 (r) register accessor: RO, I2C stauts register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_star1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_star1`] module"]
#[doc(alias = "R16_I2C_STAR1")]
pub type R16I2cStar1 = crate::Reg<r16_i2c_star1::R16I2cStar1Spec>;
#[doc = "RO, I2C stauts register 1"]
pub mod r16_i2c_star1 {
#[doc = "Register `R16_I2C_STAR1` reader"]
pub type R = crate::R<R16I2cStar1Spec>;
#[doc = "Field `RB_I2C_SB` reader - RW0, Start bit flag (Master mode)"]
pub type RbI2cSbR = crate::BitReader;
#[doc = "Field `RB_I2C_ADDR` reader - RW0, Address sent (master mode)/matched (slave mode) flag"]
pub type RbI2cAddrR = crate::BitReader;
#[doc = "Field `RB_I2C_BTF` reader - RO, Byte transfer finished flag"]
pub type RbI2cBtfR = crate::BitReader;
#[doc = "Field `RB_I2C_ADD10` reader - RO, 10-bit header sent flag (Master mode)"]
pub type RbI2cAdd10R = crate::BitReader;
#[doc = "Field `RB_I2C_STOPF` reader - RO, Stop detection flag (slave mode)"]
pub type RbI2cStopfR = crate::BitReader;
#[doc = "Field `RB_I2C_RxNE` reader - RO, Data register not empty flag (receivers)"]
pub type RbI2cRxNeR = crate::BitReader;
#[doc = "Field `RB_I2C_TxE` reader - RO, Data register empty flag (transmitters)"]
pub type RbI2cTxER = crate::BitReader;
#[doc = "Field `RB_I2C_BERR` reader - RW0, Bus error flag"]
pub type RbI2cBerrR = crate::BitReader;
#[doc = "Field `RB_I2C_ARLO` reader - RW0, Arbitration lost flag (master mode)"]
pub type RbI2cArloR = crate::BitReader;
#[doc = "Field `RB_I2C_AF` reader - RW0, Acknowledge failure flag"]
pub type RbI2cAfR = crate::BitReader;
#[doc = "Field `RB_I2C_OVR` reader - RW0, Overrun/Underrun flag"]
pub type RbI2cOvrR = crate::BitReader;
#[doc = "Field `RB_I2C_PECERR` reader - RW0, PEC Error flag in reception"]
pub type RbI2cPecerrR = crate::BitReader;
#[doc = "Field `RB_I2C_TIMEOUT` reader - RW0, Timeout or Tlow error flag"]
pub type RbI2cTimeoutR = crate::BitReader;
#[doc = "Field `RB_I2C_SMBALERT` reader - RW0, SMBus alert flag"]
pub type RbI2cSmbalertR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RW0, Start bit flag (Master mode)"]
#[inline(always)]
pub fn rb_i2c_sb(&self) -> RbI2cSbR {
RbI2cSbR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW0, Address sent (master mode)/matched (slave mode) flag"]
#[inline(always)]
pub fn rb_i2c_addr(&self) -> RbI2cAddrR {
RbI2cAddrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RO, Byte transfer finished flag"]
#[inline(always)]
pub fn rb_i2c_btf(&self) -> RbI2cBtfR {
RbI2cBtfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RO, 10-bit header sent flag (Master mode)"]
#[inline(always)]
pub fn rb_i2c_add10(&self) -> RbI2cAdd10R {
RbI2cAdd10R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RO, Stop detection flag (slave mode)"]
#[inline(always)]
pub fn rb_i2c_stopf(&self) -> RbI2cStopfR {
RbI2cStopfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - RO, Data register not empty flag (receivers)"]
#[inline(always)]
pub fn rb_i2c_rx_ne(&self) -> RbI2cRxNeR {
RbI2cRxNeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, Data register empty flag (transmitters)"]
#[inline(always)]
pub fn rb_i2c_tx_e(&self) -> RbI2cTxER {
RbI2cTxER::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - RW0, Bus error flag"]
#[inline(always)]
pub fn rb_i2c_berr(&self) -> RbI2cBerrR {
RbI2cBerrR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - RW0, Arbitration lost flag (master mode)"]
#[inline(always)]
pub fn rb_i2c_arlo(&self) -> RbI2cArloR {
RbI2cArloR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - RW0, Acknowledge failure flag"]
#[inline(always)]
pub fn rb_i2c_af(&self) -> RbI2cAfR {
RbI2cAfR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - RW0, Overrun/Underrun flag"]
#[inline(always)]
pub fn rb_i2c_ovr(&self) -> RbI2cOvrR {
RbI2cOvrR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - RW0, PEC Error flag in reception"]
#[inline(always)]
pub fn rb_i2c_pecerr(&self) -> RbI2cPecerrR {
RbI2cPecerrR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - RW0, Timeout or Tlow error flag"]
#[inline(always)]
pub fn rb_i2c_timeout(&self) -> RbI2cTimeoutR {
RbI2cTimeoutR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15 - RW0, SMBus alert flag"]
#[inline(always)]
pub fn rb_i2c_smbalert(&self) -> RbI2cSmbalertR {
RbI2cSmbalertR::new(((self.bits >> 15) & 1) != 0)
}
}
#[doc = "RO, I2C stauts register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_star1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cStar1Spec;
impl crate::RegisterSpec for R16I2cStar1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_star1::R`](R) reader structure"]
impl crate::Readable for R16I2cStar1Spec {}
#[doc = "`reset()` method sets R16_I2C_STAR1 to value 0"]
impl crate::Resettable for R16I2cStar1Spec {}
}
#[doc = "R16_I2C_STAR2 (r) register accessor: RO, I2C status register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_star2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_star2`] module"]
#[doc(alias = "R16_I2C_STAR2")]
pub type R16I2cStar2 = crate::Reg<r16_i2c_star2::R16I2cStar2Spec>;
#[doc = "RO, I2C status register 2"]
pub mod r16_i2c_star2 {
#[doc = "Register `R16_I2C_STAR2` reader"]
pub type R = crate::R<R16I2cStar2Spec>;
#[doc = "Field `RB_I2C_MSL` reader - RO, Mode statu: 0=Slave mode, 1=Master mode"]
pub type RbI2cMslR = crate::BitReader;
#[doc = "Field `RB_I2C_BUSY` reader - RO, Bus busy flag"]
pub type RbI2cBusyR = crate::BitReader;
#[doc = "Field `RB_I2C_TRA` reader - RO, Trans flag: 0=data bytes received, 1=data bytes transmitted"]
pub type RbI2cTraR = crate::BitReader;
#[doc = "Field `RB_I2C_GENCALL` reader - RO, General call address (Slave mode) received flag"]
pub type RbI2cGencallR = crate::BitReader;
#[doc = "Field `RB_I2C_SMBDEFAULT` reader - RO, SMBus device default address (Slave mode) received flag"]
pub type RbI2cSmbdefaultR = crate::BitReader;
#[doc = "Field `RB_I2C_SMBHOST` reader - RO, SMBus host header (Slave mode) received flag"]
pub type RbI2cSmbhostR = crate::BitReader;
#[doc = "Field `RB_I2C_DUALF` reader - RO, Dual flag (Slave mode): 0=Received address matched with OAR1, 1=Received address matched with OAR2"]
pub type RbI2cDualfR = crate::BitReader;
#[doc = "Field `RB_I2C_PECX` reader - RO, Packet error checking register"]
pub type RbI2cPecxR = crate::FieldReader;
impl R {
#[doc = "Bit 0 - RO, Mode statu: 0=Slave mode, 1=Master mode"]
#[inline(always)]
pub fn rb_i2c_msl(&self) -> RbI2cMslR {
RbI2cMslR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RO, Bus busy flag"]
#[inline(always)]
pub fn rb_i2c_busy(&self) -> RbI2cBusyR {
RbI2cBusyR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RO, Trans flag: 0=data bytes received, 1=data bytes transmitted"]
#[inline(always)]
pub fn rb_i2c_tra(&self) -> RbI2cTraR {
RbI2cTraR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - RO, General call address (Slave mode) received flag"]
#[inline(always)]
pub fn rb_i2c_gencall(&self) -> RbI2cGencallR {
RbI2cGencallR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, SMBus device default address (Slave mode) received flag"]
#[inline(always)]
pub fn rb_i2c_smbdefault(&self) -> RbI2cSmbdefaultR {
RbI2cSmbdefaultR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, SMBus host header (Slave mode) received flag"]
#[inline(always)]
pub fn rb_i2c_smbhost(&self) -> RbI2cSmbhostR {
RbI2cSmbhostR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, Dual flag (Slave mode): 0=Received address matched with OAR1, 1=Received address matched with OAR2"]
#[inline(always)]
pub fn rb_i2c_dualf(&self) -> RbI2cDualfR {
RbI2cDualfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15 - RO, Packet error checking register"]
#[inline(always)]
pub fn rb_i2c_pecx(&self) -> RbI2cPecxR {
RbI2cPecxR::new(((self.bits >> 8) & 0xff) as u8)
}
}
#[doc = "RO, I2C status register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_star2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cStar2Spec;
impl crate::RegisterSpec for R16I2cStar2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_star2::R`](R) reader structure"]
impl crate::Readable for R16I2cStar2Spec {}
#[doc = "`reset()` method sets R16_I2C_STAR2 to value 0"]
impl crate::Resettable for R16I2cStar2Spec {}
}
#[doc = "R16_I2C_CKCFGR (rw) register accessor: RW, I2C clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ckcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ckcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_ckcfgr`] module"]
#[doc(alias = "R16_I2C_CKCFGR")]
pub type R16I2cCkcfgr = crate::Reg<r16_i2c_ckcfgr::R16I2cCkcfgrSpec>;
#[doc = "RW, I2C clock control register"]
pub mod r16_i2c_ckcfgr {
#[doc = "Register `R16_I2C_CKCFGR` reader"]
pub type R = crate::R<R16I2cCkcfgrSpec>;
#[doc = "Register `R16_I2C_CKCFGR` writer"]
pub type W = crate::W<R16I2cCkcfgrSpec>;
#[doc = "Field `RB_I2C_CCR` reader - RW, Controls the SCL clock in Fm/Sm mode (Master mode)"]
pub type RbI2cCcrR = crate::FieldReader<u16>;
#[doc = "Field `RB_I2C_CCR` writer - RW, Controls the SCL clock in Fm/Sm mode (Master mode)"]
pub type RbI2cCcrW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RB_I2C_DUTY` reader - RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9"]
pub type RbI2cDutyR = crate::BitReader;
#[doc = "Field `RB_I2C_DUTY` writer - RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9"]
pub type RbI2cDutyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_I2C_F/S` reader - RW, I2C master mode selection: 0=standard mode, 1=fast mode"]
pub type RbI2cFsR = crate::BitReader;
#[doc = "Field `RB_I2C_F/S` writer - RW, I2C master mode selection: 0=standard mode, 1=fast mode"]
pub type RbI2cFsW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:11 - RW, Controls the SCL clock in Fm/Sm mode (Master mode)"]
#[inline(always)]
pub fn rb_i2c_ccr(&self) -> RbI2cCcrR {
RbI2cCcrR::new(self.bits & 0x0fff)
}
#[doc = "Bit 14 - RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9"]
#[inline(always)]
pub fn rb_i2c_duty(&self) -> RbI2cDutyR {
RbI2cDutyR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - RW, I2C master mode selection: 0=standard mode, 1=fast mode"]
#[inline(always)]
pub fn rb_i2c_fs(&self) -> RbI2cFsR {
RbI2cFsR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:11 - RW, Controls the SCL clock in Fm/Sm mode (Master mode)"]
#[inline(always)]
pub fn rb_i2c_ccr(&mut self) -> RbI2cCcrW<R16I2cCkcfgrSpec> {
RbI2cCcrW::new(self, 0)
}
#[doc = "Bit 14 - RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9"]
#[inline(always)]
pub fn rb_i2c_duty(&mut self) -> RbI2cDutyW<R16I2cCkcfgrSpec> {
RbI2cDutyW::new(self, 14)
}
#[doc = "Bit 15 - RW, I2C master mode selection: 0=standard mode, 1=fast mode"]
#[inline(always)]
pub fn rb_i2c_fs(&mut self) -> RbI2cFsW<R16I2cCkcfgrSpec> {
RbI2cFsW::new(self, 15)
}
}
#[doc = "RW, I2C clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_ckcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_ckcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cCkcfgrSpec;
impl crate::RegisterSpec for R16I2cCkcfgrSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_ckcfgr::R`](R) reader structure"]
impl crate::Readable for R16I2cCkcfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_ckcfgr::W`](W) writer structure"]
impl crate::Writable for R16I2cCkcfgrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_CKCFGR to value 0"]
impl crate::Resettable for R16I2cCkcfgrSpec {}
}
#[doc = "R16_I2C_RTR (rw) register accessor: RW, I2C trise register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_rtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_rtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_i2c_rtr`] module"]
#[doc(alias = "R16_I2C_RTR")]
pub type R16I2cRtr = crate::Reg<r16_i2c_rtr::R16I2cRtrSpec>;
#[doc = "RW, I2C trise register"]
pub mod r16_i2c_rtr {
#[doc = "Register `R16_I2C_RTR` reader"]
pub type R = crate::R<R16I2cRtrSpec>;
#[doc = "Register `R16_I2C_RTR` writer"]
pub type W = crate::W<R16I2cRtrSpec>;
#[doc = "Field `RB_I2C_TRISE` reader - RW, Maximum rise time in Fm/Sm mode (Master mode)"]
pub type RbI2cTriseR = crate::FieldReader;
#[doc = "Field `RB_I2C_TRISE` writer - RW, Maximum rise time in Fm/Sm mode (Master mode)"]
pub type RbI2cTriseW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bits 0:5 - RW, Maximum rise time in Fm/Sm mode (Master mode)"]
#[inline(always)]
pub fn rb_i2c_trise(&self) -> RbI2cTriseR {
RbI2cTriseR::new((self.bits & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - RW, Maximum rise time in Fm/Sm mode (Master mode)"]
#[inline(always)]
pub fn rb_i2c_trise(&mut self) -> RbI2cTriseW<R16I2cRtrSpec> {
RbI2cTriseW::new(self, 0)
}
}
#[doc = "RW, I2C trise register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_i2c_rtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_i2c_rtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16I2cRtrSpec;
impl crate::RegisterSpec for R16I2cRtrSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_i2c_rtr::R`](R) reader structure"]
impl crate::Readable for R16I2cRtrSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_i2c_rtr::W`](W) writer structure"]
impl crate::Writable for R16I2cRtrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_I2C_RTR to value 0x02"]
impl crate::Resettable for R16I2cRtrSpec {
const RESET_VALUE: u16 = 0x02;
}
}
}
#[doc = "PWMx register"]
pub type Pwmx = crate::Periph<pwmx::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for Pwmx {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pwmx").finish()
}
}
#[doc = "PWMx register"]
pub mod pwmx {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r8_pwm_out_en: R8PwmOutEn,
r8_pwm_polar: R8PwmPolar,
r8_pwm_config: R8PwmConfig,
r8_pwm_dma_ctrl: R8PwmDmaCtrl,
r32_pwm1_3_data: R32Pwm1_3Data,
r16_pwm3_data: R16Pwm3Data,
_reserved6: [u8; 0x02],
r8_pwm_int_en: R8PwmIntEn,
r8_pwm_int_flag: R8PwmIntFlag,
_reserved8: [u8; 0x02],
r32_pwm4_5_data: R32Pwm4_5Data,
r16_pwm_cyc_value: R16PwmCycValue,
_reserved10: [u8; 0x02],
r16_pwm_clock_div: R16PwmClockDiv,
_reserved11: [u8; 0x02],
r32_pwm_dma_now: R32PwmDmaNow,
r32_pwm_dma_beg: R32PwmDmaBeg,
r32_pwm_dma_end: R32PwmDmaEnd,
}
impl RegisterBlock {
#[doc = "0x00 - RW, PWM output enable control"]
#[inline(always)]
pub const fn r8_pwm_out_en(&self) -> &R8PwmOutEn {
&self.r8_pwm_out_en
}
#[doc = "0x01 - RW, PWM output polarity control"]
#[inline(always)]
pub const fn r8_pwm_polar(&self) -> &R8PwmPolar {
&self.r8_pwm_polar
}
#[doc = "0x02 - RW, PWM configuration"]
#[inline(always)]
pub const fn r8_pwm_config(&self) -> &R8PwmConfig {
&self.r8_pwm_config
}
#[doc = "0x03 - RW, PWMx DMA control register"]
#[inline(always)]
pub const fn r8_pwm_dma_ctrl(&self) -> &R8PwmDmaCtrl {
&self.r8_pwm_dma_ctrl
}
#[doc = "0x04 - RW, PWM data retention register group 1"]
#[inline(always)]
pub const fn r32_pwm1_3_data(&self) -> &R32Pwm1_3Data {
&self.r32_pwm1_3_data
}
#[doc = "0x08 - RW, PWM data retention register group 2"]
#[inline(always)]
pub const fn r16_pwm3_data(&self) -> &R16Pwm3Data {
&self.r16_pwm3_data
}
#[doc = "0x0c - RW, PWMx interrupt enable register"]
#[inline(always)]
pub const fn r8_pwm_int_en(&self) -> &R8PwmIntEn {
&self.r8_pwm_int_en
}
#[doc = "0x0d - RW1, PWMx interrupt flag register"]
#[inline(always)]
pub const fn r8_pwm_int_flag(&self) -> &R8PwmIntFlag {
&self.r8_pwm_int_flag
}
#[doc = "0x10 - RW, PWM data retention register group 3"]
#[inline(always)]
pub const fn r32_pwm4_5_data(&self) -> &R32Pwm4_5Data {
&self.r32_pwm4_5_data
}
#[doc = "0x14 - RW, PWM1/2/3 cycles end register"]
#[inline(always)]
pub const fn r16_pwm_cyc_value(&self) -> &R16PwmCycValue {
&self.r16_pwm_cyc_value
}
#[doc = "0x18 - RW, PWM reference clock frequency division coefficient"]
#[inline(always)]
pub const fn r16_pwm_clock_div(&self) -> &R16PwmClockDiv {
&self.r16_pwm_clock_div
}
#[doc = "0x1c - RW, Current address of PWMx DMA buffer"]
#[inline(always)]
pub const fn r32_pwm_dma_now(&self) -> &R32PwmDmaNow {
&self.r32_pwm_dma_now
}
#[doc = "0x20 - RW, Starting address of PWMx DMA buffer"]
#[inline(always)]
pub const fn r32_pwm_dma_beg(&self) -> &R32PwmDmaBeg {
&self.r32_pwm_dma_beg
}
#[doc = "0x24 - RW, End of PWMx DMA buffer"]
#[inline(always)]
pub const fn r32_pwm_dma_end(&self) -> &R32PwmDmaEnd {
&self.r32_pwm_dma_end
}
}
#[doc = "R8_PWM_OUT_EN (rw) register accessor: RW, PWM output enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_out_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_out_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_out_en`] module"]
#[doc(alias = "R8_PWM_OUT_EN")]
pub type R8PwmOutEn = crate::Reg<r8_pwm_out_en::R8PwmOutEnSpec>;
#[doc = "RW, PWM output enable control"]
pub mod r8_pwm_out_en {
#[doc = "Register `R8_PWM_OUT_EN` reader"]
pub type R = crate::R<R8PwmOutEnSpec>;
#[doc = "Register `R8_PWM_OUT_EN` writer"]
pub type W = crate::W<R8PwmOutEnSpec>;
#[doc = "Field `RB_PWM1_OUT_EN` reader - RW, PWM1 output enable"]
pub type RbPwm1OutEnR = crate::BitReader;
#[doc = "Field `RB_PWM1_OUT_EN` writer - RW, PWM1 output enable"]
pub type RbPwm1OutEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM2_OUT_EN` reader - RW, PWM2 output enable"]
pub type RbPwm2OutEnR = crate::BitReader;
#[doc = "Field `RB_PWM2_OUT_EN` writer - RW, PWM2 output enable"]
pub type RbPwm2OutEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM3_OUT_EN` reader - RW, PWM3 output enable"]
pub type RbPwm3OutEnR = crate::BitReader;
#[doc = "Field `RB_PWM3_OUT_EN` writer - RW, PWM3 output enable"]
pub type RbPwm3OutEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM4_OUT_EN` reader - RW, PWM4 output enable"]
pub type RbPwm4OutEnR = crate::BitReader;
#[doc = "Field `RB_PWM4_OUT_EN` writer - RW, PWM4 output enable"]
pub type RbPwm4OutEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM5_OUT_EN` reader - RW, PWM5 output enable"]
pub type RbPwm5OutEnR = crate::BitReader;
#[doc = "Field `RB_PWM5_OUT_EN` writer - RW, PWM5 output enable"]
pub type RbPwm5OutEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, PWM1 output enable"]
#[inline(always)]
pub fn rb_pwm1_out_en(&self) -> RbPwm1OutEnR {
RbPwm1OutEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, PWM2 output enable"]
#[inline(always)]
pub fn rb_pwm2_out_en(&self) -> RbPwm2OutEnR {
RbPwm2OutEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, PWM3 output enable"]
#[inline(always)]
pub fn rb_pwm3_out_en(&self) -> RbPwm3OutEnR {
RbPwm3OutEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, PWM4 output enable"]
#[inline(always)]
pub fn rb_pwm4_out_en(&self) -> RbPwm4OutEnR {
RbPwm4OutEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, PWM5 output enable"]
#[inline(always)]
pub fn rb_pwm5_out_en(&self) -> RbPwm5OutEnR {
RbPwm5OutEnR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, PWM1 output enable"]
#[inline(always)]
pub fn rb_pwm1_out_en(&mut self) -> RbPwm1OutEnW<R8PwmOutEnSpec> {
RbPwm1OutEnW::new(self, 0)
}
#[doc = "Bit 1 - RW, PWM2 output enable"]
#[inline(always)]
pub fn rb_pwm2_out_en(&mut self) -> RbPwm2OutEnW<R8PwmOutEnSpec> {
RbPwm2OutEnW::new(self, 1)
}
#[doc = "Bit 2 - RW, PWM3 output enable"]
#[inline(always)]
pub fn rb_pwm3_out_en(&mut self) -> RbPwm3OutEnW<R8PwmOutEnSpec> {
RbPwm3OutEnW::new(self, 2)
}
#[doc = "Bit 3 - RW, PWM4 output enable"]
#[inline(always)]
pub fn rb_pwm4_out_en(&mut self) -> RbPwm4OutEnW<R8PwmOutEnSpec> {
RbPwm4OutEnW::new(self, 3)
}
#[doc = "Bit 4 - RW, PWM5 output enable"]
#[inline(always)]
pub fn rb_pwm5_out_en(&mut self) -> RbPwm5OutEnW<R8PwmOutEnSpec> {
RbPwm5OutEnW::new(self, 4)
}
}
#[doc = "RW, PWM output enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_out_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_out_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmOutEnSpec;
impl crate::RegisterSpec for R8PwmOutEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_out_en::R`](R) reader structure"]
impl crate::Readable for R8PwmOutEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_out_en::W`](W) writer structure"]
impl crate::Writable for R8PwmOutEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_OUT_EN to value 0"]
impl crate::Resettable for R8PwmOutEnSpec {}
}
#[doc = "R8_PWM_POLAR (rw) register accessor: RW, PWM output polarity control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_polar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_polar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_polar`] module"]
#[doc(alias = "R8_PWM_POLAR")]
pub type R8PwmPolar = crate::Reg<r8_pwm_polar::R8PwmPolarSpec>;
#[doc = "RW, PWM output polarity control"]
pub mod r8_pwm_polar {
#[doc = "Register `R8_PWM_POLAR` reader"]
pub type R = crate::R<R8PwmPolarSpec>;
#[doc = "Register `R8_PWM_POLAR` writer"]
pub type W = crate::W<R8PwmPolarSpec>;
#[doc = "Field `RB_PWM1_POLAR` reader - RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm1PolarR = crate::BitReader;
#[doc = "Field `RB_PWM1_POLAR` writer - RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm1PolarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM2_POLAR` reader - RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm2PolarR = crate::BitReader;
#[doc = "Field `RB_PWM2_POLAR` writer - RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm2PolarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM3_POLAR` reader - RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm3PolarR = crate::BitReader;
#[doc = "Field `RB_PWM3_POLAR` writer - RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm3PolarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM4_POLAR` reader - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm4PolarR = crate::BitReader;
#[doc = "Field `RB_PWM4_POLAR` writer - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm4PolarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM5_POLAR` reader - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm5PolarR = crate::BitReader;
#[doc = "Field `RB_PWM5_POLAR` writer - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
pub type RbPwm5PolarW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm1_polar(&self) -> RbPwm1PolarR {
RbPwm1PolarR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm2_polar(&self) -> RbPwm2PolarR {
RbPwm2PolarR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm3_polar(&self) -> RbPwm3PolarR {
RbPwm3PolarR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm4_polar(&self) -> RbPwm4PolarR {
RbPwm4PolarR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm5_polar(&self) -> RbPwm5PolarR {
RbPwm5PolarR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm1_polar(&mut self) -> RbPwm1PolarW<R8PwmPolarSpec> {
RbPwm1PolarW::new(self, 0)
}
#[doc = "Bit 1 - RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm2_polar(&mut self) -> RbPwm2PolarW<R8PwmPolarSpec> {
RbPwm2PolarW::new(self, 1)
}
#[doc = "Bit 2 - RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm3_polar(&mut self) -> RbPwm3PolarW<R8PwmPolarSpec> {
RbPwm3PolarW::new(self, 2)
}
#[doc = "Bit 3 - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm4_polar(&mut self) -> RbPwm4PolarW<R8PwmPolarSpec> {
RbPwm4PolarW::new(self, 3)
}
#[doc = "Bit 4 - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
#[inline(always)]
pub fn rb_pwm5_polar(&mut self) -> RbPwm5PolarW<R8PwmPolarSpec> {
RbPwm5PolarW::new(self, 4)
}
}
#[doc = "RW, PWM output polarity control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_polar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_polar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmPolarSpec;
impl crate::RegisterSpec for R8PwmPolarSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_polar::R`](R) reader structure"]
impl crate::Readable for R8PwmPolarSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_polar::W`](W) writer structure"]
impl crate::Writable for R8PwmPolarSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_POLAR to value 0"]
impl crate::Resettable for R8PwmPolarSpec {}
}
#[doc = "R8_PWM_CONFIG (rw) register accessor: RW, PWM configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_config`] module"]
#[doc(alias = "R8_PWM_CONFIG")]
pub type R8PwmConfig = crate::Reg<r8_pwm_config::R8PwmConfigSpec>;
#[doc = "RW, PWM configuration"]
pub mod r8_pwm_config {
#[doc = "Register `R8_PWM_CONFIG` reader"]
pub type R = crate::R<R8PwmConfigSpec>;
#[doc = "Register `R8_PWM_CONFIG` writer"]
pub type W = crate::W<R8PwmConfigSpec>;
#[doc = "Field `RB_PWM_CYCLE_SEL` reader - RW, PWM cycle selection: 0=256;128;64;32 clocks, 1=255;127;63;31 clocks"]
pub type RbPwmCycleSelR = crate::BitReader;
#[doc = "Field `RB_PWM_CYCLE_SEL` writer - RW, PWM cycle selection: 0=256;128;64;32 clocks, 1=255;127;63;31 clocks"]
pub type RbPwmCycleSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_CYC_MOD` reader - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
pub type RbPwmCycModR = crate::FieldReader;
#[doc = "Field `RB_PWM_CYC_MOD` writer - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
pub type RbPwmCycModW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_PWM4_5_STAG_EN` reader - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
pub type RbPwm4_5StagEnR = crate::BitReader;
#[doc = "Field `RB_PWM4_5_STAG_EN` writer - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
pub type RbPwm4_5StagEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM4_5_CH` reader - RW, PWM4/5 channel output status"]
pub type RbPwm4_5ChR = crate::BitReader;
#[doc = "Field `RB_PWM4_5_CH` writer - RW, PWM4/5 channel output status"]
pub type RbPwm4_5ChW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_SYNC_START` reader - RW, Sync Start"]
pub type RbPwmSyncStartR = crate::BitReader;
#[doc = "Field `RB_PWM_SYNC_START` writer - RW, Sync Start"]
pub type RbPwmSyncStartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_SYNC_EN` reader - RW, Synchronization enablement allows"]
pub type RbPwmSyncEnR = crate::BitReader;
#[doc = "Field `RB_PWM_SYNC_EN` writer - RW, Synchronization enablement allows"]
pub type RbPwmSyncEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, PWM cycle selection: 0=256;128;64;32 clocks, 1=255;127;63;31 clocks"]
#[inline(always)]
pub fn rb_pwm_cycle_sel(&self) -> RbPwmCycleSelR {
RbPwmCycleSelR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
#[inline(always)]
pub fn rb_pwm_cyc_mod(&self) -> RbPwmCycModR {
RbPwmCycModR::new((self.bits >> 1) & 3)
}
#[doc = "Bit 3 - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
#[inline(always)]
pub fn rb_pwm4_5_stag_en(&self) -> RbPwm4_5StagEnR {
RbPwm4_5StagEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW, PWM4/5 channel output status"]
#[inline(always)]
pub fn rb_pwm4_5_ch(&self) -> RbPwm4_5ChR {
RbPwm4_5ChR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - RW, Sync Start"]
#[inline(always)]
pub fn rb_pwm_sync_start(&self) -> RbPwmSyncStartR {
RbPwmSyncStartR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RW, Synchronization enablement allows"]
#[inline(always)]
pub fn rb_pwm_sync_en(&self) -> RbPwmSyncEnR {
RbPwmSyncEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, PWM cycle selection: 0=256;128;64;32 clocks, 1=255;127;63;31 clocks"]
#[inline(always)]
pub fn rb_pwm_cycle_sel(&mut self) -> RbPwmCycleSelW<R8PwmConfigSpec> {
RbPwmCycleSelW::new(self, 0)
}
#[doc = "Bits 1:2 - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
#[inline(always)]
pub fn rb_pwm_cyc_mod(&mut self) -> RbPwmCycModW<R8PwmConfigSpec> {
RbPwmCycModW::new(self, 1)
}
#[doc = "Bit 3 - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
#[inline(always)]
pub fn rb_pwm4_5_stag_en(&mut self) -> RbPwm4_5StagEnW<R8PwmConfigSpec> {
RbPwm4_5StagEnW::new(self, 3)
}
#[doc = "Bit 4 - RW, PWM4/5 channel output status"]
#[inline(always)]
pub fn rb_pwm4_5_ch(&mut self) -> RbPwm4_5ChW<R8PwmConfigSpec> {
RbPwm4_5ChW::new(self, 4)
}
#[doc = "Bit 6 - RW, Sync Start"]
#[inline(always)]
pub fn rb_pwm_sync_start(&mut self) -> RbPwmSyncStartW<R8PwmConfigSpec> {
RbPwmSyncStartW::new(self, 6)
}
#[doc = "Bit 7 - RW, Synchronization enablement allows"]
#[inline(always)]
pub fn rb_pwm_sync_en(&mut self) -> RbPwmSyncEnW<R8PwmConfigSpec> {
RbPwmSyncEnW::new(self, 7)
}
}
#[doc = "RW, PWM configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmConfigSpec;
impl crate::RegisterSpec for R8PwmConfigSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_config::R`](R) reader structure"]
impl crate::Readable for R8PwmConfigSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_config::W`](W) writer structure"]
impl crate::Writable for R8PwmConfigSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_CONFIG to value 0"]
impl crate::Resettable for R8PwmConfigSpec {}
}
#[doc = "R8_PWM_DMA_CTRL (rw) register accessor: RW, PWMx DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_dma_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_dma_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_dma_ctrl`] module"]
#[doc(alias = "R8_PWM_DMA_CTRL")]
pub type R8PwmDmaCtrl = crate::Reg<r8_pwm_dma_ctrl::R8PwmDmaCtrlSpec>;
#[doc = "RW, PWMx DMA control register"]
pub mod r8_pwm_dma_ctrl {
#[doc = "Register `R8_PWM_DMA_CTRL` reader"]
pub type R = crate::R<R8PwmDmaCtrlSpec>;
#[doc = "Register `R8_PWM_DMA_CTRL` writer"]
pub type W = crate::W<R8PwmDmaCtrlSpec>;
#[doc = "Field `RB_DMA_ENABLE` reader - RW, DMA enabled (only valid when the data width is 16)"]
pub type RbDmaEnableR = crate::BitReader;
#[doc = "Field `RB_DMA_ENABLE` writer - RW, DMA enabled (only valid when the data width is 16)"]
pub type RbDmaEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_DMA_ADDR_LOOP` reader - RW, DMA Loop Output Enable"]
pub type RbDmaAddrLoopR = crate::BitReader;
#[doc = "Field `RB_DMA_ADDR_LOOP` writer - RW, DMA Loop Output Enable"]
pub type RbDmaAddrLoopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_DMA_SEL` reader - RW, DMA output channel selection when RB_PWM_SYNC_EN=0"]
pub type RbDmaSelR = crate::BitReader;
#[doc = "Field `RB_DMA_SEL` writer - RW, DMA output channel selection when RB_PWM_SYNC_EN=0"]
pub type RbDmaSelW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, DMA enabled (only valid when the data width is 16)"]
#[inline(always)]
pub fn rb_dma_enable(&self) -> RbDmaEnableR {
RbDmaEnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, DMA Loop Output Enable"]
#[inline(always)]
pub fn rb_dma_addr_loop(&self) -> RbDmaAddrLoopR {
RbDmaAddrLoopR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, DMA output channel selection when RB_PWM_SYNC_EN=0"]
#[inline(always)]
pub fn rb_dma_sel(&self) -> RbDmaSelR {
RbDmaSelR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, DMA enabled (only valid when the data width is 16)"]
#[inline(always)]
pub fn rb_dma_enable(&mut self) -> RbDmaEnableW<R8PwmDmaCtrlSpec> {
RbDmaEnableW::new(self, 0)
}
#[doc = "Bit 1 - RW, DMA Loop Output Enable"]
#[inline(always)]
pub fn rb_dma_addr_loop(&mut self) -> RbDmaAddrLoopW<R8PwmDmaCtrlSpec> {
RbDmaAddrLoopW::new(self, 1)
}
#[doc = "Bit 2 - RW, DMA output channel selection when RB_PWM_SYNC_EN=0"]
#[inline(always)]
pub fn rb_dma_sel(&mut self) -> RbDmaSelW<R8PwmDmaCtrlSpec> {
RbDmaSelW::new(self, 2)
}
}
#[doc = "RW, PWMx DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmDmaCtrlSpec;
impl crate::RegisterSpec for R8PwmDmaCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_dma_ctrl::R`](R) reader structure"]
impl crate::Readable for R8PwmDmaCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_dma_ctrl::W`](W) writer structure"]
impl crate::Writable for R8PwmDmaCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_DMA_CTRL to value 0"]
impl crate::Resettable for R8PwmDmaCtrlSpec {}
}
#[doc = "R32_PWM1_3_DATA (rw) register accessor: RW, PWM data retention register group 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm1_3_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm1_3_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pwm1_3_data`] module"]
#[doc(alias = "R32_PWM1_3_DATA")]
pub type R32Pwm1_3Data = crate::Reg<r32_pwm1_3_data::R32Pwm1_3DataSpec>;
#[doc = "RW, PWM data retention register group 1"]
pub mod r32_pwm1_3_data {
#[doc = "Register `R32_PWM1_3_DATA` reader"]
pub type R = crate::R<R32Pwm1_3DataSpec>;
#[doc = "Register `R32_PWM1_3_DATA` writer"]
pub type W = crate::W<R32Pwm1_3DataSpec>;
#[doc = "Field `R8_PWM1_DATA/R16_PWM1_DATA` reader - RW, PWM1 data holding or PWM1 data holding(16bits wide)"]
pub type R8Pwm1Datar16Pwm1DataR = crate::FieldReader;
#[doc = "Field `R8_PWM1_DATA/R16_PWM1_DATA` writer - RW, PWM1 data holding or PWM1 data holding(16bits wide)"]
pub type R8Pwm1Datar16Pwm1DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PWM2_DATA/R16_PWM1_DATA` reader - RW, PWM2 data holding or PWM1 data holding(16bits wide)"]
pub type R8Pwm2Datar16Pwm1DataR = crate::FieldReader;
#[doc = "Field `R8_PWM2_DATA/R16_PWM1_DATA` writer - RW, PWM2 data holding or PWM1 data holding(16bits wide)"]
pub type R8Pwm2Datar16Pwm1DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PWM3_DATA/R16_PWM2_DATA` reader - RW, PWM3 data holding or PWM2 data holding(16bits wide)"]
pub type R8Pwm3Datar16Pwm2DataR = crate::FieldReader;
#[doc = "Field `R8_PWM3_DATA/R16_PWM2_DATA` writer - RW, PWM3 data holding or PWM2 data holding(16bits wide)"]
pub type R8Pwm3Datar16Pwm2DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R16_PWM2_DATA` reader - RW, PWM2 data holding(16bits wide)"]
pub type R16Pwm2DataR = crate::FieldReader;
#[doc = "Field `R16_PWM2_DATA` writer - RW, PWM2 data holding(16bits wide)"]
pub type R16Pwm2DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW, PWM1 data holding or PWM1 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm1_datar16_pwm1_data(&self) -> R8Pwm1Datar16Pwm1DataR {
R8Pwm1Datar16Pwm1DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - RW, PWM2 data holding or PWM1 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm2_datar16_pwm1_data(&self) -> R8Pwm2Datar16Pwm1DataR {
R8Pwm2Datar16Pwm1DataR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - RW, PWM3 data holding or PWM2 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm3_datar16_pwm2_data(&self) -> R8Pwm3Datar16Pwm2DataR {
R8Pwm3Datar16Pwm2DataR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - RW, PWM2 data holding(16bits wide)"]
#[inline(always)]
pub fn r16_pwm2_data(&self) -> R16Pwm2DataR {
R16Pwm2DataR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - RW, PWM1 data holding or PWM1 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm1_datar16_pwm1_data(
&mut self,
) -> R8Pwm1Datar16Pwm1DataW<R32Pwm1_3DataSpec> {
R8Pwm1Datar16Pwm1DataW::new(self, 0)
}
#[doc = "Bits 8:15 - RW, PWM2 data holding or PWM1 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm2_datar16_pwm1_data(
&mut self,
) -> R8Pwm2Datar16Pwm1DataW<R32Pwm1_3DataSpec> {
R8Pwm2Datar16Pwm1DataW::new(self, 8)
}
#[doc = "Bits 16:23 - RW, PWM3 data holding or PWM2 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm3_datar16_pwm2_data(
&mut self,
) -> R8Pwm3Datar16Pwm2DataW<R32Pwm1_3DataSpec> {
R8Pwm3Datar16Pwm2DataW::new(self, 16)
}
#[doc = "Bits 24:31 - RW, PWM2 data holding(16bits wide)"]
#[inline(always)]
pub fn r16_pwm2_data(&mut self) -> R16Pwm2DataW<R32Pwm1_3DataSpec> {
R16Pwm2DataW::new(self, 24)
}
}
#[doc = "RW, PWM data retention register group 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm1_3_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm1_3_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32Pwm1_3DataSpec;
impl crate::RegisterSpec for R32Pwm1_3DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pwm1_3_data::R`](R) reader structure"]
impl crate::Readable for R32Pwm1_3DataSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pwm1_3_data::W`](W) writer structure"]
impl crate::Writable for R32Pwm1_3DataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PWM1_3_DATA to value 0"]
impl crate::Resettable for R32Pwm1_3DataSpec {}
}
#[doc = "R16_PWM3_DATA (rw) register accessor: RW, PWM data retention register group 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm3_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm3_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pwm3_data`] module"]
#[doc(alias = "R16_PWM3_DATA")]
pub type R16Pwm3Data = crate::Reg<r16_pwm3_data::R16Pwm3DataSpec>;
#[doc = "RW, PWM data retention register group 2"]
pub mod r16_pwm3_data {
#[doc = "Register `R16_PWM3_DATA` reader"]
pub type R = crate::R<R16Pwm3DataSpec>;
#[doc = "Register `R16_PWM3_DATA` writer"]
pub type W = crate::W<R16Pwm3DataSpec>;
#[doc = "Field `R16_PWM3_DATA` reader - RW, PWM3 data retention register"]
pub type R16Pwm3DataR = crate::FieldReader<u16>;
#[doc = "Field `R16_PWM3_DATA` writer - RW, PWM3 data retention register"]
pub type R16Pwm3DataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW, PWM3 data retention register"]
#[inline(always)]
pub fn r16_pwm3_data(&self) -> R16Pwm3DataR {
R16Pwm3DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW, PWM3 data retention register"]
#[inline(always)]
pub fn r16_pwm3_data(&mut self) -> R16Pwm3DataW<R16Pwm3DataSpec> {
R16Pwm3DataW::new(self, 0)
}
}
#[doc = "RW, PWM data retention register group 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm3_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm3_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Pwm3DataSpec;
impl crate::RegisterSpec for R16Pwm3DataSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pwm3_data::R`](R) reader structure"]
impl crate::Readable for R16Pwm3DataSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pwm3_data::W`](W) writer structure"]
impl crate::Writable for R16Pwm3DataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PWM3_DATA to value 0"]
impl crate::Resettable for R16Pwm3DataSpec {}
}
#[doc = "R32_PWM4_5_DATA (rw) register accessor: RW, PWM data retention register group 3\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm4_5_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm4_5_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pwm4_5_data`] module"]
#[doc(alias = "R32_PWM4_5_DATA")]
pub type R32Pwm4_5Data = crate::Reg<r32_pwm4_5_data::R32Pwm4_5DataSpec>;
#[doc = "RW, PWM data retention register group 3"]
pub mod r32_pwm4_5_data {
#[doc = "Register `R32_PWM4_5_DATA` reader"]
pub type R = crate::R<R32Pwm4_5DataSpec>;
#[doc = "Register `R32_PWM4_5_DATA` writer"]
pub type W = crate::W<R32Pwm4_5DataSpec>;
#[doc = "Field `R8_PWM4_DATA/R16_PWM4_DATA` reader - RW, PWM4 data holding or PWM4 data holding(16bits wide)"]
pub type R8Pwm4Datar16Pwm4DataR = crate::FieldReader;
#[doc = "Field `R8_PWM4_DATA/R16_PWM4_DATA` writer - RW, PWM4 data holding or PWM4 data holding(16bits wide)"]
pub type R8Pwm4Datar16Pwm4DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R8_PWM5_DATA/R16_PWM4_DATA` reader - RW, PWM5 data holding or PWM4 data holding(16bits wide)"]
pub type R8Pwm5Datar16Pwm4DataR = crate::FieldReader;
#[doc = "Field `R8_PWM5_DATA/R16_PWM4_DATA` writer - RW, PWM5 data holding or PWM4 data holding(16bits wide)"]
pub type R8Pwm5Datar16Pwm4DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `R16_PWM5_DATA` reader - RW, PWM5 data holding(16bits wide)"]
pub type R16Pwm5DataR = crate::FieldReader<u32>;
#[doc = "Field `R16_PWM5_DATA` writer - RW, PWM5 data holding(16bits wide)"]
pub type R16Pwm5DataW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bits 0:7 - RW, PWM4 data holding or PWM4 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm4_datar16_pwm4_data(&self) -> R8Pwm4Datar16Pwm4DataR {
R8Pwm4Datar16Pwm4DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - RW, PWM5 data holding or PWM4 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm5_datar16_pwm4_data(&self) -> R8Pwm5Datar16Pwm4DataR {
R8Pwm5Datar16Pwm4DataR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:32 - RW, PWM5 data holding(16bits wide)"]
#[inline(always)]
pub fn r16_pwm5_data(&self) -> R16Pwm5DataR {
R16Pwm5DataR::new((self.bits >> 16) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - RW, PWM4 data holding or PWM4 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm4_datar16_pwm4_data(
&mut self,
) -> R8Pwm4Datar16Pwm4DataW<R32Pwm4_5DataSpec> {
R8Pwm4Datar16Pwm4DataW::new(self, 0)
}
#[doc = "Bits 8:15 - RW, PWM5 data holding or PWM4 data holding(16bits wide)"]
#[inline(always)]
pub fn r8_pwm5_datar16_pwm4_data(
&mut self,
) -> R8Pwm5Datar16Pwm4DataW<R32Pwm4_5DataSpec> {
R8Pwm5Datar16Pwm4DataW::new(self, 8)
}
#[doc = "Bits 16:32 - RW, PWM5 data holding(16bits wide)"]
#[inline(always)]
pub fn r16_pwm5_data(&mut self) -> R16Pwm5DataW<R32Pwm4_5DataSpec> {
R16Pwm5DataW::new(self, 16)
}
}
#[doc = "RW, PWM data retention register group 3\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm4_5_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm4_5_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32Pwm4_5DataSpec;
impl crate::RegisterSpec for R32Pwm4_5DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pwm4_5_data::R`](R) reader structure"]
impl crate::Readable for R32Pwm4_5DataSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pwm4_5_data::W`](W) writer structure"]
impl crate::Writable for R32Pwm4_5DataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PWM4_5_DATA to value 0"]
impl crate::Resettable for R32Pwm4_5DataSpec {}
}
#[doc = "R8_PWM_INT_EN (rw) register accessor: RW, PWMx interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_int_en`] module"]
#[doc(alias = "R8_PWM_INT_EN")]
pub type R8PwmIntEn = crate::Reg<r8_pwm_int_en::R8PwmIntEnSpec>;
#[doc = "RW, PWMx interrupt enable register"]
pub mod r8_pwm_int_en {
#[doc = "Register `R8_PWM_INT_EN` reader"]
pub type R = crate::R<R8PwmIntEnSpec>;
#[doc = "Register `R8_PWM_INT_EN` writer"]
pub type W = crate::W<R8PwmIntEnSpec>;
#[doc = "Field `RB_PWM_IE_CYC` reader - RW, End of PWM1/2/3 cycle interrupt enable bit"]
pub type RbPwmIeCycR = crate::BitReader;
#[doc = "Field `RB_PWM_IE_CYC` writer - RW, End of PWM1/2/3 cycle interrupt enable bit"]
pub type RbPwmIeCycW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_CYC_PRE` reader - RW, Select the interrupt time point at the end of the PWM cycle"]
pub type RbPwmCycPreR = crate::BitReader;
#[doc = "Field `RB_PWM_CYC_PRE` writer - RW, Select the interrupt time point at the end of the PWM cycle"]
pub type RbPwmCycPreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM1_IE_CYC` reader - RW, End of PWM4/5 cycle interrupt enable bit"]
pub type RbPwm1IeCycR = crate::BitReader;
#[doc = "Field `RB_PWM1_IE_CYC` writer - RW, End of PWM4/5 cycle interrupt enable bit"]
pub type RbPwm1IeCycW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IE_FIFO` reader - RW, FIFO data less than 4 interrupt enable bits"]
pub type RbPwmIeFifoR = crate::BitReader;
#[doc = "Field `RB_PWM_IE_FIFO` writer - RW, FIFO data less than 4 interrupt enable bits"]
pub type RbPwmIeFifoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IE_DMA` reader - RW, DMA transfer end interrupt enable bit"]
pub type RbPwmIeDmaR = crate::BitReader;
#[doc = "Field `RB_PWM_IE_DMA` writer - RW, DMA transfer end interrupt enable bit"]
pub type RbPwmIeDmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IE_OVER` reader - RW, FIFO read air interrupt enable bit"]
pub type RbPwmIeOverR = crate::BitReader;
#[doc = "Field `RB_PWM_IE_OVER` writer - RW, FIFO read air interrupt enable bit"]
pub type RbPwmIeOverW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, End of PWM1/2/3 cycle interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_cyc(&self) -> RbPwmIeCycR {
RbPwmIeCycR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW, Select the interrupt time point at the end of the PWM cycle"]
#[inline(always)]
pub fn rb_pwm_cyc_pre(&self) -> RbPwmCycPreR {
RbPwmCycPreR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW, End of PWM4/5 cycle interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm1_ie_cyc(&self) -> RbPwm1IeCycR {
RbPwm1IeCycR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - RW, FIFO data less than 4 interrupt enable bits"]
#[inline(always)]
pub fn rb_pwm_ie_fifo(&self) -> RbPwmIeFifoR {
RbPwmIeFifoR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RW, DMA transfer end interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_dma(&self) -> RbPwmIeDmaR {
RbPwmIeDmaR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RW, FIFO read air interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_over(&self) -> RbPwmIeOverR {
RbPwmIeOverR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, End of PWM1/2/3 cycle interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_cyc(&mut self) -> RbPwmIeCycW<R8PwmIntEnSpec> {
RbPwmIeCycW::new(self, 0)
}
#[doc = "Bit 1 - RW, Select the interrupt time point at the end of the PWM cycle"]
#[inline(always)]
pub fn rb_pwm_cyc_pre(&mut self) -> RbPwmCycPreW<R8PwmIntEnSpec> {
RbPwmCycPreW::new(self, 1)
}
#[doc = "Bit 2 - RW, End of PWM4/5 cycle interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm1_ie_cyc(&mut self) -> RbPwm1IeCycW<R8PwmIntEnSpec> {
RbPwm1IeCycW::new(self, 2)
}
#[doc = "Bit 4 - RW, FIFO data less than 4 interrupt enable bits"]
#[inline(always)]
pub fn rb_pwm_ie_fifo(&mut self) -> RbPwmIeFifoW<R8PwmIntEnSpec> {
RbPwmIeFifoW::new(self, 4)
}
#[doc = "Bit 5 - RW, DMA transfer end interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_dma(&mut self) -> RbPwmIeDmaW<R8PwmIntEnSpec> {
RbPwmIeDmaW::new(self, 5)
}
#[doc = "Bit 6 - RW, FIFO read air interrupt enable bit"]
#[inline(always)]
pub fn rb_pwm_ie_over(&mut self) -> RbPwmIeOverW<R8PwmIntEnSpec> {
RbPwmIeOverW::new(self, 6)
}
}
#[doc = "RW, PWMx interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmIntEnSpec;
impl crate::RegisterSpec for R8PwmIntEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_int_en::R`](R) reader structure"]
impl crate::Readable for R8PwmIntEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_int_en::W`](W) writer structure"]
impl crate::Writable for R8PwmIntEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_INT_EN to value 0"]
impl crate::Resettable for R8PwmIntEnSpec {}
}
#[doc = "R8_PWM_INT_FLAG (rw) register accessor: RW1, PWMx interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_int_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_int_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_pwm_int_flag`] module"]
#[doc(alias = "R8_PWM_INT_FLAG")]
pub type R8PwmIntFlag = crate::Reg<r8_pwm_int_flag::R8PwmIntFlagSpec>;
#[doc = "RW1, PWMx interrupt flag register"]
pub mod r8_pwm_int_flag {
#[doc = "Register `R8_PWM_INT_FLAG` reader"]
pub type R = crate::R<R8PwmIntFlagSpec>;
#[doc = "Register `R8_PWM_INT_FLAG` writer"]
pub type W = crate::W<R8PwmIntFlagSpec>;
#[doc = "Field `RB_PWM_IF_CYC` reader - RW1, PWM1/2/3 cycle end flag"]
pub type RbPwmIfCycR = crate::BitReader;
#[doc = "Field `RB_PWM_IF_CYC` writer - RW1, PWM1/2/3 cycle end flag"]
pub type RbPwmIfCycW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM1_IF_CYC` reader - RW1, PWM4/5 cycle end flag"]
pub type RbPwm1IfCycR = crate::BitReader;
#[doc = "Field `RB_PWM1_IF_CYC` writer - RW1, PWM4/5 cycle end flag"]
pub type RbPwm1IfCycW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IF_FIFO` reader - RW1, FIFO data less than 4 interrupt flag bits"]
pub type RbPwmIfFifoR = crate::BitReader;
#[doc = "Field `RB_PWM_IF_FIFO` writer - RW1, FIFO data less than 4 interrupt flag bits"]
pub type RbPwmIfFifoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IF_DMA` reader - RW1, DMA transfer end interrupt flag bit"]
pub type RbPwmIfDmaR = crate::BitReader;
#[doc = "Field `RB_PWM_IF_DMA` writer - RW1, DMA transfer end interrupt flag bit"]
pub type RbPwmIfDmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_PWM_IF_OVER` reader - RW1, FIFO overflow interrupt flag bit"]
pub type RbPwmIfOverR = crate::BitReader;
#[doc = "Field `RB_PWM_IF_OVER` writer - RW1, FIFO overflow interrupt flag bit"]
pub type RbPwmIfOverW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW1, PWM1/2/3 cycle end flag"]
#[inline(always)]
pub fn rb_pwm_if_cyc(&self) -> RbPwmIfCycR {
RbPwmIfCycR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW1, PWM4/5 cycle end flag"]
#[inline(always)]
pub fn rb_pwm1_if_cyc(&self) -> RbPwm1IfCycR {
RbPwm1IfCycR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW1, FIFO data less than 4 interrupt flag bits"]
#[inline(always)]
pub fn rb_pwm_if_fifo(&self) -> RbPwmIfFifoR {
RbPwmIfFifoR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW1, DMA transfer end interrupt flag bit"]
#[inline(always)]
pub fn rb_pwm_if_dma(&self) -> RbPwmIfDmaR {
RbPwmIfDmaR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW1, FIFO overflow interrupt flag bit"]
#[inline(always)]
pub fn rb_pwm_if_over(&self) -> RbPwmIfOverR {
RbPwmIfOverR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW1, PWM1/2/3 cycle end flag"]
#[inline(always)]
pub fn rb_pwm_if_cyc(&mut self) -> RbPwmIfCycW<R8PwmIntFlagSpec> {
RbPwmIfCycW::new(self, 0)
}
#[doc = "Bit 1 - RW1, PWM4/5 cycle end flag"]
#[inline(always)]
pub fn rb_pwm1_if_cyc(&mut self) -> RbPwm1IfCycW<R8PwmIntFlagSpec> {
RbPwm1IfCycW::new(self, 1)
}
#[doc = "Bit 2 - RW1, FIFO data less than 4 interrupt flag bits"]
#[inline(always)]
pub fn rb_pwm_if_fifo(&mut self) -> RbPwmIfFifoW<R8PwmIntFlagSpec> {
RbPwmIfFifoW::new(self, 2)
}
#[doc = "Bit 3 - RW1, DMA transfer end interrupt flag bit"]
#[inline(always)]
pub fn rb_pwm_if_dma(&mut self) -> RbPwmIfDmaW<R8PwmIntFlagSpec> {
RbPwmIfDmaW::new(self, 3)
}
#[doc = "Bit 4 - RW1, FIFO overflow interrupt flag bit"]
#[inline(always)]
pub fn rb_pwm_if_over(&mut self) -> RbPwmIfOverW<R8PwmIntFlagSpec> {
RbPwmIfOverW::new(self, 4)
}
}
#[doc = "RW1, PWMx interrupt flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_pwm_int_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_pwm_int_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8PwmIntFlagSpec;
impl crate::RegisterSpec for R8PwmIntFlagSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_pwm_int_flag::R`](R) reader structure"]
impl crate::Readable for R8PwmIntFlagSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_pwm_int_flag::W`](W) writer structure"]
impl crate::Writable for R8PwmIntFlagSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_PWM_INT_FLAG to value 0"]
impl crate::Resettable for R8PwmIntFlagSpec {}
}
#[doc = "R16_PWM_CYC_VALUE (rw) register accessor: RW, PWM1/2/3 cycles end register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm_cyc_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm_cyc_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pwm_cyc_value`] module"]
#[doc(alias = "R16_PWM_CYC_VALUE")]
pub type R16PwmCycValue = crate::Reg<r16_pwm_cyc_value::R16PwmCycValueSpec>;
#[doc = "RW, PWM1/2/3 cycles end register"]
pub mod r16_pwm_cyc_value {
#[doc = "Register `R16_PWM_CYC_VALUE` reader"]
pub type R = crate::R<R16PwmCycValueSpec>;
#[doc = "Register `R16_PWM_CYC_VALUE` writer"]
pub type W = crate::W<R16PwmCycValueSpec>;
#[doc = "Field `R16_PWM_CYC_VALUE` reader - RW, PWM1/2/3 clock cycle at 16 data widths"]
pub type R16PwmCycValueR = crate::FieldReader<u16>;
#[doc = "Field `R16_PWM_CYC_VALUE` writer - RW, PWM1/2/3 clock cycle at 16 data widths"]
pub type R16PwmCycValueW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW, PWM1/2/3 clock cycle at 16 data widths"]
#[inline(always)]
pub fn r16_pwm_cyc_value(&self) -> R16PwmCycValueR {
R16PwmCycValueR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW, PWM1/2/3 clock cycle at 16 data widths"]
#[inline(always)]
pub fn r16_pwm_cyc_value(&mut self) -> R16PwmCycValueW<R16PwmCycValueSpec> {
R16PwmCycValueW::new(self, 0)
}
}
#[doc = "RW, PWM1/2/3 cycles end register\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm_cyc_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm_cyc_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PwmCycValueSpec;
impl crate::RegisterSpec for R16PwmCycValueSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pwm_cyc_value::R`](R) reader structure"]
impl crate::Readable for R16PwmCycValueSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pwm_cyc_value::W`](W) writer structure"]
impl crate::Writable for R16PwmCycValueSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PWM_CYC_VALUE to value 0"]
impl crate::Resettable for R16PwmCycValueSpec {}
}
#[doc = "R16_PWM_CLOCK_DIV (rw) register accessor: RW, PWM reference clock frequency division coefficient\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm_clock_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm_clock_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_pwm_clock_div`] module"]
#[doc(alias = "R16_PWM_CLOCK_DIV")]
pub type R16PwmClockDiv = crate::Reg<r16_pwm_clock_div::R16PwmClockDivSpec>;
#[doc = "RW, PWM reference clock frequency division coefficient"]
pub mod r16_pwm_clock_div {
#[doc = "Register `R16_PWM_CLOCK_DIV` reader"]
pub type R = crate::R<R16PwmClockDivSpec>;
#[doc = "Register `R16_PWM_CLOCK_DIV` writer"]
pub type W = crate::W<R16PwmClockDivSpec>;
#[doc = "Field `R16_PWM_CLOCK_DIV` reader - RW, DMA data buffer current address"]
pub type R16PwmClockDivR = crate::FieldReader<u16>;
#[doc = "Field `R16_PWM_CLOCK_DIV` writer - RW, DMA data buffer current address"]
pub type R16PwmClockDivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW, DMA data buffer current address"]
#[inline(always)]
pub fn r16_pwm_clock_div(&self) -> R16PwmClockDivR {
R16PwmClockDivR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW, DMA data buffer current address"]
#[inline(always)]
pub fn r16_pwm_clock_div(&mut self) -> R16PwmClockDivW<R16PwmClockDivSpec> {
R16PwmClockDivW::new(self, 0)
}
}
#[doc = "RW, PWM reference clock frequency division coefficient\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_pwm_clock_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_pwm_clock_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16PwmClockDivSpec;
impl crate::RegisterSpec for R16PwmClockDivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_pwm_clock_div::R`](R) reader structure"]
impl crate::Readable for R16PwmClockDivSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_pwm_clock_div::W`](W) writer structure"]
impl crate::Writable for R16PwmClockDivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_PWM_CLOCK_DIV to value 0"]
impl crate::Resettable for R16PwmClockDivSpec {}
}
#[doc = "R32_PWM_DMA_NOW (rw) register accessor: RW, Current address of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_now::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_now::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pwm_dma_now`] module"]
#[doc(alias = "R32_PWM_DMA_NOW")]
pub type R32PwmDmaNow = crate::Reg<r32_pwm_dma_now::R32PwmDmaNowSpec>;
#[doc = "RW, Current address of PWMx DMA buffer"]
pub mod r32_pwm_dma_now {
#[doc = "Register `R32_PWM_DMA_NOW` reader"]
pub type R = crate::R<R32PwmDmaNowSpec>;
#[doc = "Register `R32_PWM_DMA_NOW` writer"]
pub type W = crate::W<R32PwmDmaNowSpec>;
#[doc = "Field `R32_PWM_DMA_NOW` reader - RW, Current address of PWMx DMA buffer"]
pub type R32PwmDmaNowR = crate::FieldReader<u32>;
#[doc = "Field `R32_PWM_DMA_NOW` writer - RW, Current address of PWMx DMA buffer"]
pub type R32PwmDmaNowW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, Current address of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_now(&self) -> R32PwmDmaNowR {
R32PwmDmaNowR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, Current address of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_now(&mut self) -> R32PwmDmaNowW<R32PwmDmaNowSpec> {
R32PwmDmaNowW::new(self, 0)
}
}
#[doc = "RW, Current address of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_now::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_now::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PwmDmaNowSpec;
impl crate::RegisterSpec for R32PwmDmaNowSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pwm_dma_now::R`](R) reader structure"]
impl crate::Readable for R32PwmDmaNowSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pwm_dma_now::W`](W) writer structure"]
impl crate::Writable for R32PwmDmaNowSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PWM_DMA_NOW to value 0"]
impl crate::Resettable for R32PwmDmaNowSpec {}
}
#[doc = "R32_PWM_DMA_BEG (rw) register accessor: RW, Starting address of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_beg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_beg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pwm_dma_beg`] module"]
#[doc(alias = "R32_PWM_DMA_BEG")]
pub type R32PwmDmaBeg = crate::Reg<r32_pwm_dma_beg::R32PwmDmaBegSpec>;
#[doc = "RW, Starting address of PWMx DMA buffer"]
pub mod r32_pwm_dma_beg {
#[doc = "Register `R32_PWM_DMA_BEG` reader"]
pub type R = crate::R<R32PwmDmaBegSpec>;
#[doc = "Register `R32_PWM_DMA_BEG` writer"]
pub type W = crate::W<R32PwmDmaBegSpec>;
#[doc = "Field `R32_PWM_DMA_BEG` reader - RW, Starting address of PWMx DMA buffer"]
pub type R32PwmDmaBegR = crate::FieldReader<u32>;
#[doc = "Field `R32_PWM_DMA_BEG` writer - RW, Starting address of PWMx DMA buffer"]
pub type R32PwmDmaBegW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, Starting address of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_beg(&self) -> R32PwmDmaBegR {
R32PwmDmaBegR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, Starting address of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_beg(&mut self) -> R32PwmDmaBegW<R32PwmDmaBegSpec> {
R32PwmDmaBegW::new(self, 0)
}
}
#[doc = "RW, Starting address of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_beg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_beg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PwmDmaBegSpec;
impl crate::RegisterSpec for R32PwmDmaBegSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pwm_dma_beg::R`](R) reader structure"]
impl crate::Readable for R32PwmDmaBegSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pwm_dma_beg::W`](W) writer structure"]
impl crate::Writable for R32PwmDmaBegSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PWM_DMA_BEG to value 0"]
impl crate::Resettable for R32PwmDmaBegSpec {}
}
#[doc = "R32_PWM_DMA_END (rw) register accessor: RW, End of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pwm_dma_end`] module"]
#[doc(alias = "R32_PWM_DMA_END")]
pub type R32PwmDmaEnd = crate::Reg<r32_pwm_dma_end::R32PwmDmaEndSpec>;
#[doc = "RW, End of PWMx DMA buffer"]
pub mod r32_pwm_dma_end {
#[doc = "Register `R32_PWM_DMA_END` reader"]
pub type R = crate::R<R32PwmDmaEndSpec>;
#[doc = "Register `R32_PWM_DMA_END` writer"]
pub type W = crate::W<R32PwmDmaEndSpec>;
#[doc = "Field `R32_PWM_DMA_END` reader - RW, End of PWMx DMA buffer"]
pub type R32PwmDmaEndR = crate::FieldReader<u32>;
#[doc = "Field `R32_PWM_DMA_END` writer - RW, End of PWMx DMA buffer"]
pub type R32PwmDmaEndW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, End of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_end(&self) -> R32PwmDmaEndR {
R32PwmDmaEndR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, End of PWMx DMA buffer"]
#[inline(always)]
pub fn r32_pwm_dma_end(&mut self) -> R32PwmDmaEndW<R32PwmDmaEndSpec> {
R32PwmDmaEndW::new(self, 0)
}
}
#[doc = "RW, End of PWMx DMA buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pwm_dma_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pwm_dma_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PwmDmaEndSpec;
impl crate::RegisterSpec for R32PwmDmaEndSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pwm_dma_end::R`](R) reader structure"]
impl crate::Readable for R32PwmDmaEndSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pwm_dma_end::W`](W) writer structure"]
impl crate::Writable for R32PwmDmaEndSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PWM_DMA_END to value 0"]
impl crate::Resettable for R32PwmDmaEndSpec {}
}
}
#[doc = "USBFS register"]
pub type Usbfs = crate::Periph<usbfs::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for Usbfs {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usbfs").finish()
}
}
#[doc = "USBFS register"]
pub mod usbfs {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r8_usb_ctrl: R8UsbCtrl,
_reserved_1_r8: [u8; 0x01],
r8_usb_int_en: R8UsbIntEn,
r8_usb_dev_ad: R8UsbDevAd,
_reserved4: [u8; 0x01],
r8_usb_mis_st: R8UsbMisSt,
r8_usb_int_fg: R8UsbIntFg,
r8_usb_int_st: R8UsbIntSt,
r8_usb_rx_len: R8UsbRxLen,
_reserved8: [u8; 0x03],
r8_uep4_1_mod: R8Uep4_1Mod,
_reserved_9_r8: [u8; 0x01],
r8_uep567_mod: R8Uep567Mod,
_reserved11: [u8; 0x01],
r16_uep0_dma: R16Uep0Dma,
_reserved12: [u8; 0x02],
r16_uep1_dma: R16Uep1Dma,
_reserved13: [u8; 0x02],
_reserved_13_r16: [u8; 0x02],
_reserved14: [u8; 0x02],
_reserved_14_r16: [u8; 0x02],
_reserved15: [u8; 0x02],
r8_uep0_t_len: R8Uep0TLen,
_reserved16: [u8; 0x01],
r8_uep0_ctrl: R8Uep0Ctrl,
_reserved17: [u8; 0x01],
r8_uep1_t_len: R8Uep1TLen,
_reserved18: [u8; 0x01],
_reserved_18_r8: [u8; 0x01],
_reserved19: [u8; 0x01],
_reserved_19_r8: [u8; 0x01],
_reserved20: [u8; 0x01],
_reserved_20_r8: [u8; 0x01],
_reserved21: [u8; 0x01],
_reserved_21_r8: [u8; 0x01],
_reserved22: [u8; 0x01],
_reserved_22_r8: [u8; 0x01],
_reserved23: [u8; 0x01],
r8_uep4_t_len: R8Uep4TLen,
_reserved24: [u8; 0x01],
r8_uep4_ctrl: R8Uep4Ctrl,
_reserved25: [u8; 0x21],
r16_uep5_dma: R16Uep5Dma,
_reserved26: [u8; 0x02],
r16_uep6_dma: R16Uep6Dma,
_reserved27: [u8; 0x02],
r16_uep7_dma: R16Uep7Dma,
_reserved28: [u8; 0x06],
r8_uep5_t_len: R8Uep5TLen,
_reserved29: [u8; 0x01],
r8_uep5_ctrl: R8Uep5Ctrl,
_reserved30: [u8; 0x01],
r8_uep6_t_len: R8Uep6TLen,
_reserved31: [u8; 0x01],
r8_uep6_ctrl: R8Uep6Ctrl,
_reserved32: [u8; 0x01],
r8_uep7_t_len: R8Uep7TLen,
_reserved33: [u8; 0x01],
r8_uep7_ctrl: R8Uep7Ctrl,
_reserved34: [u8; 0x01],
r32_epn_mode: R32EpnMode,
}
impl RegisterBlock {
#[doc = "0x00 - USB base control"]
#[inline(always)]
pub const fn r8_usb_ctrl(&self) -> &R8UsbCtrl {
&self.r8_usb_ctrl
}
#[doc = "0x01 - USB host physical port control register"]
#[inline(always)]
pub const fn r8_uhost_ctrl(&self) -> &R8UhostCtrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(1).cast() }
}
#[doc = "0x01 - USB device physical prot control"]
#[inline(always)]
pub const fn r8_udev_ctrl(&self) -> &R8UdevCtrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(1).cast() }
}
#[doc = "0x02 - USB interrupt enable"]
#[inline(always)]
pub const fn r8_usb_int_en(&self) -> &R8UsbIntEn {
&self.r8_usb_int_en
}
#[doc = "0x03 - USB device address"]
#[inline(always)]
pub const fn r8_usb_dev_ad(&self) -> &R8UsbDevAd {
&self.r8_usb_dev_ad
}
#[doc = "0x05 - USB miscellaneous status"]
#[inline(always)]
pub const fn r8_usb_mis_st(&self) -> &R8UsbMisSt {
&self.r8_usb_mis_st
}
#[doc = "0x06 - USB interrupt flag"]
#[inline(always)]
pub const fn r8_usb_int_fg(&self) -> &R8UsbIntFg {
&self.r8_usb_int_fg
}
#[doc = "0x07 - USB interrupt status"]
#[inline(always)]
pub const fn r8_usb_int_st(&self) -> &R8UsbIntSt {
&self.r8_usb_int_st
}
#[doc = "0x08 - USB receiving length"]
#[inline(always)]
pub const fn r8_usb_rx_len(&self) -> &R8UsbRxLen {
&self.r8_usb_rx_len
}
#[doc = "0x0c - endpoint 1/4 mode"]
#[inline(always)]
pub const fn r8_uep4_1_mod(&self) -> &R8Uep4_1Mod {
&self.r8_uep4_1_mod
}
#[doc = "0x0d - USB host endpoint mode control register"]
#[inline(always)]
pub const fn r8_uh_ep_mod(&self) -> &R8UhEpMod {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(13).cast() }
}
#[doc = "0x0d - endpoint 2/3 mode;host endpoint mode"]
#[inline(always)]
pub const fn r8_uep2_3_mod(&self) -> &R8Uep2_3Mod {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(13).cast() }
}
#[doc = "0x0e - endpoint 5/6/7 mode"]
#[inline(always)]
pub const fn r8_uep567_mod(&self) -> &R8Uep567Mod {
&self.r8_uep567_mod
}
#[doc = "0x10 - endpoint 0 DMA buffer address"]
#[inline(always)]
pub const fn r16_uep0_dma(&self) -> &R16Uep0Dma {
&self.r16_uep0_dma
}
#[doc = "0x14 - endpoint 1 DMA buffer address"]
#[inline(always)]
pub const fn r16_uep1_dma(&self) -> &R16Uep1Dma {
&self.r16_uep1_dma
}
#[doc = "0x18 - USB host receiving buffer starting address"]
#[inline(always)]
pub const fn r16_uh_rx_dma(&self) -> &R16UhRxDma {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
}
#[doc = "0x18 - endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub const fn r16_uep2_dma(&self) -> &R16Uep2Dma {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
}
#[doc = "0x1c - USB host sends buffer starting address"]
#[inline(always)]
pub const fn r16_uh_tx_dma(&self) -> &R16UhTxDma {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
}
#[doc = "0x1c - endpoint 3 DMA buffer address;host tx endpoint buffer high address"]
#[inline(always)]
pub const fn r16_uep3_dma(&self) -> &R16Uep3Dma {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
}
#[doc = "0x20 - endpoint 0 transmittal length"]
#[inline(always)]
pub const fn r8_uep0_t_len(&self) -> &R8Uep0TLen {
&self.r8_uep0_t_len
}
#[doc = "0x22 - endpoint 0 control"]
#[inline(always)]
pub const fn r8_uep0_ctrl(&self) -> &R8Uep0Ctrl {
&self.r8_uep0_ctrl
}
#[doc = "0x24 - endpoint 1 transmittal length"]
#[inline(always)]
pub const fn r8_uep1_t_len(&self) -> &R8Uep1TLen {
&self.r8_uep1_t_len
}
#[doc = "0x26 - USB Host Auxiliary Settings Register"]
#[inline(always)]
pub const fn r8_uh_setup(&self) -> &R8UhSetup {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(38).cast() }
}
#[doc = "0x26 - endpoint 1 control;host aux setup"]
#[inline(always)]
pub const fn r8_uep1_ctrl(&self) -> &R8Uep1Ctrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(38).cast() }
}
#[doc = "0x28 - USB host token setting register"]
#[inline(always)]
pub const fn r8_uh_ep_pid(&self) -> &R8UhEpPid {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
}
#[doc = "0x28 - endpoint 2 transmittal length;host endpoint and PID"]
#[inline(always)]
pub const fn r8_uep2_t_len(&self) -> &R8Uep2TLen {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
}
#[doc = "0x2a - USB host receiving endpoint control register"]
#[inline(always)]
pub const fn r8_uh_rx_ctrl(&self) -> &R8UhRxCtrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(42).cast() }
}
#[doc = "0x2a - endpoint 2 control;host receiver endpoint control"]
#[inline(always)]
pub const fn r8_uep2_ctrl(&self) -> &R8Uep2Ctrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(42).cast() }
}
#[doc = "0x2c - USB host sends length register"]
#[inline(always)]
pub const fn r8_uh_tx_len(&self) -> &R8UhTxLen {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
}
#[doc = "0x2c - endpoint 3 transmittal length;host transmittal endpoint transmittal length"]
#[inline(always)]
pub const fn r8_uep3_t_len(&self) -> &R8Uep3TLen {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
}
#[doc = "0x2e - USB host sends endpoint control register"]
#[inline(always)]
pub const fn r8_uh_tx_ctrl(&self) -> &R8UhTxCtrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(46).cast() }
}
#[doc = "0x2e - endpoint 3 control;host transmittal endpoint control"]
#[inline(always)]
pub const fn r8_uep3_ctrl(&self) -> &R8Uep3Ctrl {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(46).cast() }
}
#[doc = "0x30 - endpoint 4 transmittal length"]
#[inline(always)]
pub const fn r8_uep4_t_len(&self) -> &R8Uep4TLen {
&self.r8_uep4_t_len
}
#[doc = "0x32 - endpoint 4 control"]
#[inline(always)]
pub const fn r8_uep4_ctrl(&self) -> &R8Uep4Ctrl {
&self.r8_uep4_ctrl
}
#[doc = "0x54 - endpoint 5 DMA buffer address"]
#[inline(always)]
pub const fn r16_uep5_dma(&self) -> &R16Uep5Dma {
&self.r16_uep5_dma
}
#[doc = "0x58 - endpoint 6 DMA buffer address"]
#[inline(always)]
pub const fn r16_uep6_dma(&self) -> &R16Uep6Dma {
&self.r16_uep6_dma
}
#[doc = "0x5c - endpoint 7 DMA buffer address"]
#[inline(always)]
pub const fn r16_uep7_dma(&self) -> &R16Uep7Dma {
&self.r16_uep7_dma
}
#[doc = "0x64 - endpoint 5 transmittal length"]
#[inline(always)]
pub const fn r8_uep5_t_len(&self) -> &R8Uep5TLen {
&self.r8_uep5_t_len
}
#[doc = "0x66 - endpoint 5 control"]
#[inline(always)]
pub const fn r8_uep5_ctrl(&self) -> &R8Uep5Ctrl {
&self.r8_uep5_ctrl
}
#[doc = "0x68 - endpoint 6 transmittal length"]
#[inline(always)]
pub const fn r8_uep6_t_len(&self) -> &R8Uep6TLen {
&self.r8_uep6_t_len
}
#[doc = "0x6a - endpoint 6 control"]
#[inline(always)]
pub const fn r8_uep6_ctrl(&self) -> &R8Uep6Ctrl {
&self.r8_uep6_ctrl
}
#[doc = "0x6c - endpoint 7 transmittal length"]
#[inline(always)]
pub const fn r8_uep7_t_len(&self) -> &R8Uep7TLen {
&self.r8_uep7_t_len
}
#[doc = "0x6e - endpoint 7 control"]
#[inline(always)]
pub const fn r8_uep7_ctrl(&self) -> &R8Uep7Ctrl {
&self.r8_uep7_ctrl
}
#[doc = "0x70 - endpoint n control,（n=8/10/11/12/13/14/15）"]
#[inline(always)]
pub const fn r32_epn_mode(&self) -> &R32EpnMode {
&self.r32_epn_mode
}
}
#[doc = "R8_USB_CTRL (rw) register accessor: USB base control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_ctrl`] module"]
#[doc(alias = "R8_USB_CTRL")]
pub type R8UsbCtrl = crate::Reg<r8_usb_ctrl::R8UsbCtrlSpec>;
#[doc = "USB base control"]
pub mod r8_usb_ctrl {
#[doc = "Register `R8_USB_CTRL` reader"]
pub type R = crate::R<R8UsbCtrlSpec>;
#[doc = "Register `R8_USB_CTRL` writer"]
pub type W = crate::W<R8UsbCtrlSpec>;
#[doc = "Field `RB_UC_DMA_EN` reader - DMA enable and DMA interrupt enable for USB"]
pub type RbUcDmaEnR = crate::BitReader;
#[doc = "Field `RB_UC_DMA_EN` writer - DMA enable and DMA interrupt enable for USB"]
pub type RbUcDmaEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UC_CLR_ALL` reader - force clear FIFO and count of USB"]
pub type RbUcClrAllR = crate::BitReader;
#[doc = "Field `RB_UC_CLR_ALL` writer - force clear FIFO and count of USB"]
pub type RbUcClrAllW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UC_RESET_SIE` reader - force reset USB SIE, need software clear"]
pub type RbUcResetSieR = crate::BitReader;
#[doc = "Field `RB_UC_RESET_SIE` writer - force reset USB SIE, need software clear"]
pub type RbUcResetSieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UC_INT_BUSY` reader - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
pub type RbUcIntBusyR = crate::BitReader;
#[doc = "Field `RB_UC_INT_BUSY` writer - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
pub type RbUcIntBusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK_UC_SYS_CTRL` reader - bit mask of USB system control"]
pub type MaskUcSysCtrlR = crate::FieldReader;
#[doc = "Field `MASK_UC_SYS_CTRL` writer - bit mask of USB system control"]
pub type MaskUcSysCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UC_DEV_PU_EN` reader - USB device enable and internal pullup resistance enable"]
pub type RbUcDevPuEnR = crate::BitReader;
#[doc = "Field `RB_UC_DEV_PU_EN` writer - USB device enable and internal pullup resistance enable"]
pub type RbUcDevPuEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UC_LOW_SPEED` reader - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
pub type RbUcLowSpeedR = crate::BitReader;
#[doc = "Field `RB_UC_LOW_SPEED` writer - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
pub type RbUcLowSpeedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UC_HOST_MODE` reader - enable USB host mode: 0=device mode, 1=host mode"]
pub type RbUcHostModeR = crate::BitReader;
#[doc = "Field `RB_UC_HOST_MODE` writer - enable USB host mode: 0=device mode, 1=host mode"]
pub type RbUcHostModeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - DMA enable and DMA interrupt enable for USB"]
#[inline(always)]
pub fn rb_uc_dma_en(&self) -> RbUcDmaEnR {
RbUcDmaEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - force clear FIFO and count of USB"]
#[inline(always)]
pub fn rb_uc_clr_all(&self) -> RbUcClrAllR {
RbUcClrAllR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - force reset USB SIE, need software clear"]
#[inline(always)]
pub fn rb_uc_reset_sie(&self) -> RbUcResetSieR {
RbUcResetSieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
#[inline(always)]
pub fn rb_uc_int_busy(&self) -> RbUcIntBusyR {
RbUcIntBusyR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - bit mask of USB system control"]
#[inline(always)]
pub fn mask_uc_sys_ctrl(&self) -> MaskUcSysCtrlR {
MaskUcSysCtrlR::new((self.bits >> 4) & 3)
}
#[doc = "Bit 5 - USB device enable and internal pullup resistance enable"]
#[inline(always)]
pub fn rb_uc_dev_pu_en(&self) -> RbUcDevPuEnR {
RbUcDevPuEnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
#[inline(always)]
pub fn rb_uc_low_speed(&self) -> RbUcLowSpeedR {
RbUcLowSpeedR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - enable USB host mode: 0=device mode, 1=host mode"]
#[inline(always)]
pub fn rb_uc_host_mode(&self) -> RbUcHostModeR {
RbUcHostModeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - DMA enable and DMA interrupt enable for USB"]
#[inline(always)]
pub fn rb_uc_dma_en(&mut self) -> RbUcDmaEnW<R8UsbCtrlSpec> {
RbUcDmaEnW::new(self, 0)
}
#[doc = "Bit 1 - force clear FIFO and count of USB"]
#[inline(always)]
pub fn rb_uc_clr_all(&mut self) -> RbUcClrAllW<R8UsbCtrlSpec> {
RbUcClrAllW::new(self, 1)
}
#[doc = "Bit 2 - force reset USB SIE, need software clear"]
#[inline(always)]
pub fn rb_uc_reset_sie(&mut self) -> RbUcResetSieW<R8UsbCtrlSpec> {
RbUcResetSieW::new(self, 2)
}
#[doc = "Bit 3 - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
#[inline(always)]
pub fn rb_uc_int_busy(&mut self) -> RbUcIntBusyW<R8UsbCtrlSpec> {
RbUcIntBusyW::new(self, 3)
}
#[doc = "Bits 4:5 - bit mask of USB system control"]
#[inline(always)]
pub fn mask_uc_sys_ctrl(&mut self) -> MaskUcSysCtrlW<R8UsbCtrlSpec> {
MaskUcSysCtrlW::new(self, 4)
}
#[doc = "Bit 5 - USB device enable and internal pullup resistance enable"]
#[inline(always)]
pub fn rb_uc_dev_pu_en(&mut self) -> RbUcDevPuEnW<R8UsbCtrlSpec> {
RbUcDevPuEnW::new(self, 5)
}
#[doc = "Bit 6 - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
#[inline(always)]
pub fn rb_uc_low_speed(&mut self) -> RbUcLowSpeedW<R8UsbCtrlSpec> {
RbUcLowSpeedW::new(self, 6)
}
#[doc = "Bit 7 - enable USB host mode: 0=device mode, 1=host mode"]
#[inline(always)]
pub fn rb_uc_host_mode(&mut self) -> RbUcHostModeW<R8UsbCtrlSpec> {
RbUcHostModeW::new(self, 7)
}
}
#[doc = "USB base control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbCtrlSpec;
impl crate::RegisterSpec for R8UsbCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_ctrl::R`](R) reader structure"]
impl crate::Readable for R8UsbCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_usb_ctrl::W`](W) writer structure"]
impl crate::Writable for R8UsbCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_USB_CTRL to value 0x06"]
impl crate::Resettable for R8UsbCtrlSpec {
const RESET_VALUE: u8 = 0x06;
}
}
#[doc = "R8_UDEV_CTRL (rw) register accessor: USB device physical prot control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_udev_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_udev_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_udev_ctrl`] module"]
#[doc(alias = "R8_UDEV_CTRL")]
pub type R8UdevCtrl = crate::Reg<r8_udev_ctrl::R8UdevCtrlSpec>;
#[doc = "USB device physical prot control"]
pub mod r8_udev_ctrl {
#[doc = "Register `R8_UDEV_CTRL` reader"]
pub type R = crate::R<R8UdevCtrlSpec>;
#[doc = "Register `R8_UDEV_CTRL` writer"]
pub type W = crate::W<R8UdevCtrlSpec>;
#[doc = "Field `RB_UD_PORT_EN` reader - enable USB physical port I-O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
pub type RbUdPortEnR = crate::BitReader;
#[doc = "Field `RB_UD_PORT_EN` writer - enable USB physical port I-O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
pub type RbUdPortEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UD_HUB0_RESET` reader - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
pub type RbUdHub0ResetR = crate::BitReader;
#[doc = "Field `RB_UD_HUB0_RESET` writer - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
pub type RbUdHub0ResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UD_LOW_SPEED` reader - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
pub type RbUdLowSpeedR = crate::BitReader;
#[doc = "Field `RB_UD_LOW_SPEED` writer - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
pub type RbUdLowSpeedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UD_DM_PIN` reader - ReadOnly: indicate current UDM pin level"]
pub type RbUdDmPinR = crate::BitReader;
#[doc = "Field `RB_UD_DP_PIN` reader - ReadOnly: indicate current UDP pin level"]
pub type RbUdDpPinR = crate::BitReader;
#[doc = "Field `RB_UD_PD_DIS` reader - disable USB UDP-UDM pulldown resistance: 0=enable pulldown, 1=disable"]
pub type RbUdPdDisR = crate::BitReader;
impl R {
#[doc = "Bit 0 - enable USB physical port I-O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
#[inline(always)]
pub fn rb_ud_port_en(&self) -> RbUdPortEnR {
RbUdPortEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
#[inline(always)]
pub fn rb_ud_hub0_reset(&self) -> RbUdHub0ResetR {
RbUdHub0ResetR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
#[inline(always)]
pub fn rb_ud_low_speed(&self) -> RbUdLowSpeedR {
RbUdLowSpeedR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - ReadOnly: indicate current UDM pin level"]
#[inline(always)]
pub fn rb_ud_dm_pin(&self) -> RbUdDmPinR {
RbUdDmPinR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ReadOnly: indicate current UDP pin level"]
#[inline(always)]
pub fn rb_ud_dp_pin(&self) -> RbUdDpPinR {
RbUdDpPinR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - disable USB UDP-UDM pulldown resistance: 0=enable pulldown, 1=disable"]
#[inline(always)]
pub fn rb_ud_pd_dis(&self) -> RbUdPdDisR {
RbUdPdDisR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - enable USB physical port I-O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
#[inline(always)]
pub fn rb_ud_port_en(&mut self) -> RbUdPortEnW<R8UdevCtrlSpec> {
RbUdPortEnW::new(self, 0)
}
#[doc = "Bit 1 - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
#[inline(always)]
pub fn rb_ud_hub0_reset(&mut self) -> RbUdHub0ResetW<R8UdevCtrlSpec> {
RbUdHub0ResetW::new(self, 1)
}
#[doc = "Bit 2 - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
#[inline(always)]
pub fn rb_ud_low_speed(&mut self) -> RbUdLowSpeedW<R8UdevCtrlSpec> {
RbUdLowSpeedW::new(self, 2)
}
}
#[doc = "USB device physical prot control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_udev_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_udev_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UdevCtrlSpec;
impl crate::RegisterSpec for R8UdevCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_udev_ctrl::R`](R) reader structure"]
impl crate::Readable for R8UdevCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_udev_ctrl::W`](W) writer structure"]
impl crate::Writable for R8UdevCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UDEV_CTRL to value 0"]
impl crate::Resettable for R8UdevCtrlSpec {}
}
#[doc = "R8_USB_INT_EN (rw) register accessor: USB interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_en`] module"]
#[doc(alias = "R8_USB_INT_EN")]
pub type R8UsbIntEn = crate::Reg<r8_usb_int_en::R8UsbIntEnSpec>;
#[doc = "USB interrupt enable"]
pub mod r8_usb_int_en {
#[doc = "Register `R8_USB_INT_EN` reader"]
pub type R = crate::R<R8UsbIntEnSpec>;
#[doc = "Register `R8_USB_INT_EN` writer"]
pub type W = crate::W<R8UsbIntEnSpec>;
#[doc = "Field `RB_UIE_BUS_RST__RB_UIE_DETECT` reader - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
pub type RbUieBusRst_RbUieDetectR = crate::BitReader;
#[doc = "Field `RB_UIE_BUS_RST__RB_UIE_DETECT` writer - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
pub type RbUieBusRst_RbUieDetectW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIE_TRANSFER` reader - enable interrupt for USB transfer completion"]
pub type RbUieTransferR = crate::BitReader;
#[doc = "Field `RB_UIE_TRANSFER` writer - enable interrupt for USB transfer completion"]
pub type RbUieTransferW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIE_SUSPEND` reader - enable interrupt for USB suspend or resume event"]
pub type RbUieSuspendR = crate::BitReader;
#[doc = "Field `RB_UIE_SUSPEND` writer - enable interrupt for USB suspend or resume event"]
pub type RbUieSuspendW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIE_HST_SOF` reader - enable interrupt for host SOF timer action for USB host mode"]
pub type RbUieHstSofR = crate::BitReader;
#[doc = "Field `RB_UIE_HST_SOF` writer - enable interrupt for host SOF timer action for USB host mode"]
pub type RbUieHstSofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIE_FIFO_OV` reader - enable interrupt for FIFO overflow"]
pub type RbUieFifoOvR = crate::BitReader;
#[doc = "Field `RB_UIE_FIFO_OV` writer - enable interrupt for FIFO overflow"]
pub type RbUieFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_MOD_1_WIRE` reader - enable USB single line mode"]
pub type RbMod1WireR = crate::BitReader;
#[doc = "Field `RB_MOD_1_WIRE` writer - enable USB single line mode"]
pub type RbMod1WireW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIE_DEV_NAK` reader - enable interrupt for NAK responded for USB device mode"]
pub type RbUieDevNakR = crate::BitReader;
#[doc = "Field `RB_UIE_DEV_NAK` writer - enable interrupt for NAK responded for USB device mode"]
pub type RbUieDevNakW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
#[inline(always)]
pub fn rb_uie_bus_rst__rb_uie_detect(&self) -> RbUieBusRst_RbUieDetectR {
RbUieBusRst_RbUieDetectR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - enable interrupt for USB transfer completion"]
#[inline(always)]
pub fn rb_uie_transfer(&self) -> RbUieTransferR {
RbUieTransferR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - enable interrupt for USB suspend or resume event"]
#[inline(always)]
pub fn rb_uie_suspend(&self) -> RbUieSuspendR {
RbUieSuspendR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - enable interrupt for host SOF timer action for USB host mode"]
#[inline(always)]
pub fn rb_uie_hst_sof(&self) -> RbUieHstSofR {
RbUieHstSofR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - enable interrupt for FIFO overflow"]
#[inline(always)]
pub fn rb_uie_fifo_ov(&self) -> RbUieFifoOvR {
RbUieFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - enable USB single line mode"]
#[inline(always)]
pub fn rb_mod_1_wire(&self) -> RbMod1WireR {
RbMod1WireR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - enable interrupt for NAK responded for USB device mode"]
#[inline(always)]
pub fn rb_uie_dev_nak(&self) -> RbUieDevNakR {
RbUieDevNakR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
#[inline(always)]
pub fn rb_uie_bus_rst__rb_uie_detect(
&mut self,
) -> RbUieBusRst_RbUieDetectW<R8UsbIntEnSpec> {
RbUieBusRst_RbUieDetectW::new(self, 0)
}
#[doc = "Bit 1 - enable interrupt for USB transfer completion"]
#[inline(always)]
pub fn rb_uie_transfer(&mut self) -> RbUieTransferW<R8UsbIntEnSpec> {
RbUieTransferW::new(self, 1)
}
#[doc = "Bit 2 - enable interrupt for USB suspend or resume event"]
#[inline(always)]
pub fn rb_uie_suspend(&mut self) -> RbUieSuspendW<R8UsbIntEnSpec> {
RbUieSuspendW::new(self, 2)
}
#[doc = "Bit 3 - enable interrupt for host SOF timer action for USB host mode"]
#[inline(always)]
pub fn rb_uie_hst_sof(&mut self) -> RbUieHstSofW<R8UsbIntEnSpec> {
RbUieHstSofW::new(self, 3)
}
#[doc = "Bit 4 - enable interrupt for FIFO overflow"]
#[inline(always)]
pub fn rb_uie_fifo_ov(&mut self) -> RbUieFifoOvW<R8UsbIntEnSpec> {
RbUieFifoOvW::new(self, 4)
}
#[doc = "Bit 5 - enable USB single line mode"]
#[inline(always)]
pub fn rb_mod_1_wire(&mut self) -> RbMod1WireW<R8UsbIntEnSpec> {
RbMod1WireW::new(self, 5)
}
#[doc = "Bit 6 - enable interrupt for NAK responded for USB device mode"]
#[inline(always)]
pub fn rb_uie_dev_nak(&mut self) -> RbUieDevNakW<R8UsbIntEnSpec> {
RbUieDevNakW::new(self, 6)
}
}
#[doc = "USB interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbIntEnSpec;
impl crate::RegisterSpec for R8UsbIntEnSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_int_en::R`](R) reader structure"]
impl crate::Readable for R8UsbIntEnSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_usb_int_en::W`](W) writer structure"]
impl crate::Writable for R8UsbIntEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_USB_INT_EN to value 0"]
impl crate::Resettable for R8UsbIntEnSpec {}
}
#[doc = "R8_USB_DEV_AD (rw) register accessor: USB device address\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_dev_ad::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_dev_ad::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_dev_ad`] module"]
#[doc(alias = "R8_USB_DEV_AD")]
pub type R8UsbDevAd = crate::Reg<r8_usb_dev_ad::R8UsbDevAdSpec>;
#[doc = "USB device address"]
pub mod r8_usb_dev_ad {
#[doc = "Register `R8_USB_DEV_AD` reader"]
pub type R = crate::R<R8UsbDevAdSpec>;
#[doc = "Register `R8_USB_DEV_AD` writer"]
pub type W = crate::W<R8UsbDevAdSpec>;
#[doc = "Field `MASK_USB_ADDR` reader - bit mask for USB device address"]
pub type MaskUsbAddrR = crate::FieldReader;
#[doc = "Field `MASK_USB_ADDR` writer - bit mask for USB device address"]
pub type MaskUsbAddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RB_UDA_GP_BIT` reader - general purpose bit"]
pub type RbUdaGpBitR = crate::BitReader;
#[doc = "Field `RB_UDA_GP_BIT` writer - general purpose bit"]
pub type RbUdaGpBitW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:6 - bit mask for USB device address"]
#[inline(always)]
pub fn mask_usb_addr(&self) -> MaskUsbAddrR {
MaskUsbAddrR::new(self.bits & 0x7f)
}
#[doc = "Bit 7 - general purpose bit"]
#[inline(always)]
pub fn rb_uda_gp_bit(&self) -> RbUdaGpBitR {
RbUdaGpBitR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6 - bit mask for USB device address"]
#[inline(always)]
pub fn mask_usb_addr(&mut self) -> MaskUsbAddrW<R8UsbDevAdSpec> {
MaskUsbAddrW::new(self, 0)
}
#[doc = "Bit 7 - general purpose bit"]
#[inline(always)]
pub fn rb_uda_gp_bit(&mut self) -> RbUdaGpBitW<R8UsbDevAdSpec> {
RbUdaGpBitW::new(self, 7)
}
}
#[doc = "USB device address\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_dev_ad::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_dev_ad::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbDevAdSpec;
impl crate::RegisterSpec for R8UsbDevAdSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_dev_ad::R`](R) reader structure"]
impl crate::Readable for R8UsbDevAdSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_usb_dev_ad::W`](W) writer structure"]
impl crate::Writable for R8UsbDevAdSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_USB_DEV_AD to value 0"]
impl crate::Resettable for R8UsbDevAdSpec {}
}
#[doc = "R8_USB_MIS_ST (r) register accessor: USB miscellaneous status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_mis_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_mis_st`] module"]
#[doc(alias = "R8_USB_MIS_ST")]
pub type R8UsbMisSt = crate::Reg<r8_usb_mis_st::R8UsbMisStSpec>;
#[doc = "USB miscellaneous status"]
pub mod r8_usb_mis_st {
#[doc = "Register `R8_USB_MIS_ST` reader"]
pub type R = crate::R<R8UsbMisStSpec>;
#[doc = "Field `RB_UMS_DEV_ATTACH` reader - RO, indicate device attached status on USB host"]
pub type RbUmsDevAttachR = crate::BitReader;
#[doc = "Field `RB_UMS_DM_LEVEL` reader - RO, indicate UDM level saved at device attached to USB host"]
pub type RbUmsDmLevelR = crate::BitReader;
#[doc = "Field `RB_UMS_SUSPEND` reader - RO, indicate USB suspend status"]
pub type RbUmsSuspendR = crate::BitReader;
#[doc = "Field `RB_UMS_BUS_RESET` reader - RO, indicate USB bus reset status"]
pub type RbUmsBusResetR = crate::BitReader;
#[doc = "Field `RB_UMS_R_FIFO_RDY` reader - RO, indicate USB receiving FIFO ready status (not empty)"]
pub type RbUmsRFifoRdyR = crate::BitReader;
#[doc = "Field `RB_UMS_SIE_FREE` reader - RO, indicate USB SIE free status"]
pub type RbUmsSieFreeR = crate::BitReader;
#[doc = "Field `RB_UMS_SOF_ACT` reader - RO, indicate host SOF timer action status for USB host"]
pub type RbUmsSofActR = crate::BitReader;
#[doc = "Field `RB_UMS_SOF_PRES` reader - RO, indicate host SOF timer presage status"]
pub type RbUmsSofPresR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RO, indicate device attached status on USB host"]
#[inline(always)]
pub fn rb_ums_dev_attach(&self) -> RbUmsDevAttachR {
RbUmsDevAttachR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RO, indicate UDM level saved at device attached to USB host"]
#[inline(always)]
pub fn rb_ums_dm_level(&self) -> RbUmsDmLevelR {
RbUmsDmLevelR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RO, indicate USB suspend status"]
#[inline(always)]
pub fn rb_ums_suspend(&self) -> RbUmsSuspendR {
RbUmsSuspendR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RO, indicate USB bus reset status"]
#[inline(always)]
pub fn rb_ums_bus_reset(&self) -> RbUmsBusResetR {
RbUmsBusResetR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RO, indicate USB receiving FIFO ready status (not empty)"]
#[inline(always)]
pub fn rb_ums_r_fifo_rdy(&self) -> RbUmsRFifoRdyR {
RbUmsRFifoRdyR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, indicate USB SIE free status"]
#[inline(always)]
pub fn rb_ums_sie_free(&self) -> RbUmsSieFreeR {
RbUmsSieFreeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, indicate host SOF timer action status for USB host"]
#[inline(always)]
pub fn rb_ums_sof_act(&self) -> RbUmsSofActR {
RbUmsSofActR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, indicate host SOF timer presage status"]
#[inline(always)]
pub fn rb_ums_sof_pres(&self) -> RbUmsSofPresR {
RbUmsSofPresR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "USB miscellaneous status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_mis_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbMisStSpec;
impl crate::RegisterSpec for R8UsbMisStSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_mis_st::R`](R) reader structure"]
impl crate::Readable for R8UsbMisStSpec {}
#[doc = "`reset()` method sets R8_USB_MIS_ST to value 0"]
impl crate::Resettable for R8UsbMisStSpec {}
}
#[doc = "R8_USB_INT_FG (rw) register accessor: USB interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_fg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_int_fg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_fg`] module"]
#[doc(alias = "R8_USB_INT_FG")]
pub type R8UsbIntFg = crate::Reg<r8_usb_int_fg::R8UsbIntFgSpec>;
#[doc = "USB interrupt flag"]
pub mod r8_usb_int_fg {
#[doc = "Register `R8_USB_INT_FG` reader"]
pub type R = crate::R<R8UsbIntFgSpec>;
#[doc = "Register `R8_USB_INT_FG` writer"]
pub type W = crate::W<R8UsbIntFgSpec>;
#[doc = "Field `RB_UIF_BUS_RST/RB_UIF_DETECT` reader - RW,bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
pub type RbUifBusRstrbUifDetectR = crate::BitReader;
#[doc = "Field `RB_UIF_BUS_RST/RB_UIF_DETECT` writer - RW,bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
pub type RbUifBusRstrbUifDetectW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIF_TRANSFER` reader - RW,USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
pub type RbUifTransferR = crate::BitReader;
#[doc = "Field `RB_UIF_TRANSFER` writer - RW,USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
pub type RbUifTransferW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIF_SUSPEND` reader - RW,USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
pub type RbUifSuspendR = crate::BitReader;
#[doc = "Field `RB_UIF_SUSPEND` writer - RW,USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
pub type RbUifSuspendW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIF_HST_SOF` reader - RW,host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
pub type RbUifHstSofR = crate::BitReader;
#[doc = "Field `RB_UIF_HST_SOF` writer - RW,host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
pub type RbUifHstSofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UIF_FIFO_OV` reader - RW,FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
pub type RbUifFifoOvR = crate::BitReader;
#[doc = "Field `RB_UIF_FIFO_OV` writer - RW,FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
pub type RbUifFifoOvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_U_SIE_FREE` reader - RO, indicate USB SIE free status"]
pub type RbUSieFreeR = crate::BitReader;
#[doc = "Field `RB_U_TOG_OK` reader - RO, indicate current USB transfer toggle is OK"]
pub type RbUTogOkR = crate::BitReader;
#[doc = "Field `RB_U_IS_NAK` reader - RO, indicate current USB transfer is NAK received"]
pub type RbUIsNakR = crate::BitReader;
impl R {
#[doc = "Bit 0 - RW,bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_bus_rstrb_uif_detect(&self) -> RbUifBusRstrbUifDetectR {
RbUifBusRstrbUifDetectR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RW,USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_transfer(&self) -> RbUifTransferR {
RbUifTransferR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW,USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_suspend(&self) -> RbUifSuspendR {
RbUifSuspendR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW,host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_hst_sof(&self) -> RbUifHstSofR {
RbUifHstSofR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW,FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_fifo_ov(&self) -> RbUifFifoOvR {
RbUifFifoOvR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RO, indicate USB SIE free status"]
#[inline(always)]
pub fn rb_u_sie_free(&self) -> RbUSieFreeR {
RbUSieFreeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RO, indicate current USB transfer toggle is OK"]
#[inline(always)]
pub fn rb_u_tog_ok(&self) -> RbUTogOkR {
RbUTogOkR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, indicate current USB transfer is NAK received"]
#[inline(always)]
pub fn rb_u_is_nak(&self) -> RbUIsNakR {
RbUIsNakR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW,bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_bus_rstrb_uif_detect(
&mut self,
) -> RbUifBusRstrbUifDetectW<R8UsbIntFgSpec> {
RbUifBusRstrbUifDetectW::new(self, 0)
}
#[doc = "Bit 1 - RW,USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_transfer(&mut self) -> RbUifTransferW<R8UsbIntFgSpec> {
RbUifTransferW::new(self, 1)
}
#[doc = "Bit 2 - RW,USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_suspend(&mut self) -> RbUifSuspendW<R8UsbIntFgSpec> {
RbUifSuspendW::new(self, 2)
}
#[doc = "Bit 3 - RW,host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_hst_sof(&mut self) -> RbUifHstSofW<R8UsbIntFgSpec> {
RbUifHstSofW::new(self, 3)
}
#[doc = "Bit 4 - RW,FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
#[inline(always)]
pub fn rb_uif_fifo_ov(&mut self) -> RbUifFifoOvW<R8UsbIntFgSpec> {
RbUifFifoOvW::new(self, 4)
}
}
#[doc = "USB interrupt flag\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_fg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_usb_int_fg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbIntFgSpec;
impl crate::RegisterSpec for R8UsbIntFgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_int_fg::R`](R) reader structure"]
impl crate::Readable for R8UsbIntFgSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_usb_int_fg::W`](W) writer structure"]
impl crate::Writable for R8UsbIntFgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_USB_INT_FG to value 0x20"]
impl crate::Resettable for R8UsbIntFgSpec {
const RESET_VALUE: u8 = 0x20;
}
}
#[doc = "R8_USB_INT_ST (r) register accessor: USB interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_st`] module"]
#[doc(alias = "R8_USB_INT_ST")]
pub type R8UsbIntSt = crate::Reg<r8_usb_int_st::R8UsbIntStSpec>;
#[doc = "USB interrupt status"]
pub mod r8_usb_int_st {
#[doc = "Register `R8_USB_INT_ST` reader"]
pub type R = crate::R<R8UsbIntStSpec>;
#[doc = "Field `MASK_UIS_H_RES__MASK_UIS_ENDP` reader - RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode"]
pub type MaskUisHRes_MaskUisEndpR = crate::FieldReader;
#[doc = "Field `MASK_UIS_TOKEN` reader - RO, bit mask of current token PID code received for USB device mode"]
pub type MaskUisTokenR = crate::FieldReader;
#[doc = "Field `RB_UIS_TOG_OK` reader - RO, indicate current USB transfer toggle is OK"]
pub type RbUisTogOkR = crate::BitReader;
#[doc = "Field `RB_UIS_SETUP_ACT` reader - RO, indicate current USB transfer is NAK received for USB device mode"]
pub type RbUisSetupActR = crate::BitReader;
impl R {
#[doc = "Bits 0:3 - RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode"]
#[inline(always)]
pub fn mask_uis_h_res__mask_uis_endp(&self) -> MaskUisHRes_MaskUisEndpR {
MaskUisHRes_MaskUisEndpR::new(self.bits & 0x0f)
}
#[doc = "Bits 4:5 - RO, bit mask of current token PID code received for USB device mode"]
#[inline(always)]
pub fn mask_uis_token(&self) -> MaskUisTokenR {
MaskUisTokenR::new((self.bits >> 4) & 3)
}
#[doc = "Bit 6 - RO, indicate current USB transfer toggle is OK"]
#[inline(always)]
pub fn rb_uis_tog_ok(&self) -> RbUisTogOkR {
RbUisTogOkR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RO, indicate current USB transfer is NAK received for USB device mode"]
#[inline(always)]
pub fn rb_uis_setup_act(&self) -> RbUisSetupActR {
RbUisSetupActR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "USB interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbIntStSpec;
impl crate::RegisterSpec for R8UsbIntStSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_int_st::R`](R) reader structure"]
impl crate::Readable for R8UsbIntStSpec {}
#[doc = "`reset()` method sets R8_USB_INT_ST to value 0"]
impl crate::Resettable for R8UsbIntStSpec {}
}
#[doc = "R8_USB_RX_LEN (r) register accessor: USB receiving length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_rx_len::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_rx_len`] module"]
#[doc(alias = "R8_USB_RX_LEN")]
pub type R8UsbRxLen = crate::Reg<r8_usb_rx_len::R8UsbRxLenSpec>;
#[doc = "USB receiving length"]
pub mod r8_usb_rx_len {
#[doc = "Register `R8_USB_RX_LEN` reader"]
pub type R = crate::R<R8UsbRxLenSpec>;
#[doc = "Field `R8_USB_RX_LEN` reader - RO,USB receiving length"]
pub type R8UsbRxLenR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - RO,USB receiving length"]
#[inline(always)]
pub fn r8_usb_rx_len(&self) -> R8UsbRxLenR {
R8UsbRxLenR::new(self.bits)
}
}
#[doc = "USB receiving length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_usb_rx_len::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UsbRxLenSpec;
impl crate::RegisterSpec for R8UsbRxLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_usb_rx_len::R`](R) reader structure"]
impl crate::Readable for R8UsbRxLenSpec {}
#[doc = "`reset()` method sets R8_USB_RX_LEN to value 0"]
impl crate::Resettable for R8UsbRxLenSpec {}
}
#[doc = "R8_UEP4_1_MOD (rw) register accessor: endpoint 1/4 mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_1_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_1_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_1_mod`] module"]
#[doc(alias = "R8_UEP4_1_MOD")]
pub type R8Uep4_1Mod = crate::Reg<r8_uep4_1_mod::R8Uep4_1ModSpec>;
#[doc = "endpoint 1/4 mode"]
pub mod r8_uep4_1_mod {
#[doc = "Register `R8_UEP4_1_MOD` reader"]
pub type R = crate::R<R8Uep4_1ModSpec>;
#[doc = "Register `R8_UEP4_1_MOD` writer"]
pub type W = crate::W<R8Uep4_1ModSpec>;
#[doc = "Field `RB_UEP4_TX_EN` reader - enable USB endpoint 4 transmittal (IN)"]
pub type RbUep4TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP4_TX_EN` writer - enable USB endpoint 4 transmittal (IN)"]
pub type RbUep4TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP4_RX_EN` reader - enable USB endpoint 4 receiving (OUT)"]
pub type RbUep4RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP4_RX_EN` writer - enable USB endpoint 4 receiving (OUT)"]
pub type RbUep4RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP1_BUF_MOD` reader - buffer mode of USB endpoint 1"]
pub type RbUep1BufModR = crate::BitReader;
#[doc = "Field `RB_UEP1_BUF_MOD` writer - buffer mode of USB endpoint 1"]
pub type RbUep1BufModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP1_TX_EN` reader - enable USB endpoint 1 transmittal (IN)"]
pub type RbUep1TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP1_TX_EN` writer - enable USB endpoint 1 transmittal (IN)"]
pub type RbUep1TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP1_RX_EN` reader - enable USB endpoint 1 receiving (OUT)"]
pub type RbUep1RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP1_RX_EN` writer - enable USB endpoint 1 receiving (OUT)"]
pub type RbUep1RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - enable USB endpoint 4 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep4_tx_en(&self) -> RbUep4TxEnR {
RbUep4TxEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - enable USB endpoint 4 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep4_rx_en(&self) -> RbUep4RxEnR {
RbUep4RxEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - buffer mode of USB endpoint 1"]
#[inline(always)]
pub fn rb_uep1_buf_mod(&self) -> RbUep1BufModR {
RbUep1BufModR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - enable USB endpoint 1 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep1_tx_en(&self) -> RbUep1TxEnR {
RbUep1TxEnR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - enable USB endpoint 1 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep1_rx_en(&self) -> RbUep1RxEnR {
RbUep1RxEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - enable USB endpoint 4 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep4_tx_en(&mut self) -> RbUep4TxEnW<R8Uep4_1ModSpec> {
RbUep4TxEnW::new(self, 2)
}
#[doc = "Bit 3 - enable USB endpoint 4 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep4_rx_en(&mut self) -> RbUep4RxEnW<R8Uep4_1ModSpec> {
RbUep4RxEnW::new(self, 3)
}
#[doc = "Bit 4 - buffer mode of USB endpoint 1"]
#[inline(always)]
pub fn rb_uep1_buf_mod(&mut self) -> RbUep1BufModW<R8Uep4_1ModSpec> {
RbUep1BufModW::new(self, 4)
}
#[doc = "Bit 6 - enable USB endpoint 1 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep1_tx_en(&mut self) -> RbUep1TxEnW<R8Uep4_1ModSpec> {
RbUep1TxEnW::new(self, 6)
}
#[doc = "Bit 7 - enable USB endpoint 1 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep1_rx_en(&mut self) -> RbUep1RxEnW<R8Uep4_1ModSpec> {
RbUep1RxEnW::new(self, 7)
}
}
#[doc = "endpoint 1/4 mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_1_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_1_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep4_1ModSpec;
impl crate::RegisterSpec for R8Uep4_1ModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep4_1_mod::R`](R) reader structure"]
impl crate::Readable for R8Uep4_1ModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep4_1_mod::W`](W) writer structure"]
impl crate::Writable for R8Uep4_1ModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP4_1_MOD to value 0"]
impl crate::Resettable for R8Uep4_1ModSpec {}
}
#[doc = "R8_UEP2_3_MOD (rw) register accessor: endpoint 2/3 mode;host endpoint mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_3_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_3_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_3_mod`] module"]
#[doc(alias = "R8_UEP2_3_MOD")]
pub type R8Uep2_3Mod = crate::Reg<r8_uep2_3_mod::R8Uep2_3ModSpec>;
#[doc = "endpoint 2/3 mode;host endpoint mode"]
pub mod r8_uep2_3_mod {
#[doc = "Register `R8_UEP2_3_MOD` reader"]
pub type R = crate::R<R8Uep2_3ModSpec>;
#[doc = "Register `R8_UEP2_3_MOD` writer"]
pub type W = crate::W<R8Uep2_3ModSpec>;
#[doc = "Field `RB_UEP2_BUF_MOD` reader - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
pub type RbUep2BufModR = crate::BitReader;
#[doc = "Field `RB_UEP2_BUF_MOD` writer - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
pub type RbUep2BufModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP2_TX_EN` reader - enable USB endpoint 2 transmittal (IN)"]
pub type RbUep2TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP2_TX_EN` writer - enable USB endpoint 2 transmittal (IN)"]
pub type RbUep2TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP2_RX_EN` reader - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
pub type RbUep2RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP2_RX_EN` writer - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
pub type RbUep2RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP3_BUF_MOD` reader - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
pub type RbUep3BufModR = crate::BitReader;
#[doc = "Field `RB_UEP3_BUF_MOD` writer - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
pub type RbUep3BufModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP3_TX_EN` reader - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
pub type RbUep3TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP3_TX_EN` writer - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
pub type RbUep3TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP3_RX_EN` reader - enable USB endpoint 3 receiving (OUT)"]
pub type RbUep3RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP3_RX_EN` writer - enable USB endpoint 3 receiving (OUT)"]
pub type RbUep3RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
#[inline(always)]
pub fn rb_uep2_buf_mod(&self) -> RbUep2BufModR {
RbUep2BufModR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - enable USB endpoint 2 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep2_tx_en(&self) -> RbUep2TxEnR {
RbUep2TxEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
#[inline(always)]
pub fn rb_uep2_rx_en(&self) -> RbUep2RxEnR {
RbUep2RxEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
#[inline(always)]
pub fn rb_uep3_buf_mod(&self) -> RbUep3BufModR {
RbUep3BufModR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
#[inline(always)]
pub fn rb_uep3_tx_en(&self) -> RbUep3TxEnR {
RbUep3TxEnR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - enable USB endpoint 3 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep3_rx_en(&self) -> RbUep3RxEnR {
RbUep3RxEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
#[inline(always)]
pub fn rb_uep2_buf_mod(&mut self) -> RbUep2BufModW<R8Uep2_3ModSpec> {
RbUep2BufModW::new(self, 0)
}
#[doc = "Bit 2 - enable USB endpoint 2 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep2_tx_en(&mut self) -> RbUep2TxEnW<R8Uep2_3ModSpec> {
RbUep2TxEnW::new(self, 2)
}
#[doc = "Bit 3 - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
#[inline(always)]
pub fn rb_uep2_rx_en(&mut self) -> RbUep2RxEnW<R8Uep2_3ModSpec> {
RbUep2RxEnW::new(self, 3)
}
#[doc = "Bit 4 - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
#[inline(always)]
pub fn rb_uep3_buf_mod(&mut self) -> RbUep3BufModW<R8Uep2_3ModSpec> {
RbUep3BufModW::new(self, 4)
}
#[doc = "Bit 6 - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
#[inline(always)]
pub fn rb_uep3_tx_en(&mut self) -> RbUep3TxEnW<R8Uep2_3ModSpec> {
RbUep3TxEnW::new(self, 6)
}
#[doc = "Bit 7 - enable USB endpoint 3 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep3_rx_en(&mut self) -> RbUep3RxEnW<R8Uep2_3ModSpec> {
RbUep3RxEnW::new(self, 7)
}
}
#[doc = "endpoint 2/3 mode;host endpoint mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_3_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_3_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep2_3ModSpec;
impl crate::RegisterSpec for R8Uep2_3ModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep2_3_mod::R`](R) reader structure"]
impl crate::Readable for R8Uep2_3ModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep2_3_mod::W`](W) writer structure"]
impl crate::Writable for R8Uep2_3ModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP2_3_MOD to value 0"]
impl crate::Resettable for R8Uep2_3ModSpec {}
}
#[doc = "R8_UEP567_MOD (rw) register accessor: endpoint 5/6/7 mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep567_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep567_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep567_mod`] module"]
#[doc(alias = "R8_UEP567_MOD")]
pub type R8Uep567Mod = crate::Reg<r8_uep567_mod::R8Uep567ModSpec>;
#[doc = "endpoint 5/6/7 mode"]
pub mod r8_uep567_mod {
#[doc = "Register `R8_UEP567_MOD` reader"]
pub type R = crate::R<R8Uep567ModSpec>;
#[doc = "Register `R8_UEP567_MOD` writer"]
pub type W = crate::W<R8Uep567ModSpec>;
#[doc = "Field `RB_UEP5_TX_EN` reader - enable USB endpoint 5 transmittal (IN)"]
pub type RbUep5TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP5_TX_EN` writer - enable USB endpoint 5 transmittal (IN)"]
pub type RbUep5TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP5_RX_EN` reader - enable USB endpoint 5 receiving (OUT)"]
pub type RbUep5RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP5_RX_EN` writer - enable USB endpoint 5 receiving (OUT)"]
pub type RbUep5RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP6_TX_EN` reader - enable USB endpoint 6 transmittal (IN)"]
pub type RbUep6TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP6_TX_EN` writer - enable USB endpoint 6 transmittal (IN)"]
pub type RbUep6TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP6_RX_EN` reader - enable USB endpoint 6 receiving (OUT)"]
pub type RbUep6RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP6_RX_EN` writer - enable USB endpoint 6 receiving (OUT)"]
pub type RbUep6RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP7_TX_EN` reader - enable USB endpoint 7 transmittal (IN)"]
pub type RbUep7TxEnR = crate::BitReader;
#[doc = "Field `RB_UEP7_TX_EN` writer - enable USB endpoint 7 transmittal (IN)"]
pub type RbUep7TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP7_RX_EN` reader - enable USB endpoint 7 receiving (OUT)"]
pub type RbUep7RxEnR = crate::BitReader;
#[doc = "Field `RB_UEP7_RX_EN` writer - enable USB endpoint 7 receiving (OUT)"]
pub type RbUep7RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - enable USB endpoint 5 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep5_tx_en(&self) -> RbUep5TxEnR {
RbUep5TxEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - enable USB endpoint 5 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep5_rx_en(&self) -> RbUep5RxEnR {
RbUep5RxEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - enable USB endpoint 6 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep6_tx_en(&self) -> RbUep6TxEnR {
RbUep6TxEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - enable USB endpoint 6 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep6_rx_en(&self) -> RbUep6RxEnR {
RbUep6RxEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - enable USB endpoint 7 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep7_tx_en(&self) -> RbUep7TxEnR {
RbUep7TxEnR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - enable USB endpoint 7 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep7_rx_en(&self) -> RbUep7RxEnR {
RbUep7RxEnR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - enable USB endpoint 5 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep5_tx_en(&mut self) -> RbUep5TxEnW<R8Uep567ModSpec> {
RbUep5TxEnW::new(self, 0)
}
#[doc = "Bit 1 - enable USB endpoint 5 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep5_rx_en(&mut self) -> RbUep5RxEnW<R8Uep567ModSpec> {
RbUep5RxEnW::new(self, 1)
}
#[doc = "Bit 2 - enable USB endpoint 6 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep6_tx_en(&mut self) -> RbUep6TxEnW<R8Uep567ModSpec> {
RbUep6TxEnW::new(self, 2)
}
#[doc = "Bit 3 - enable USB endpoint 6 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep6_rx_en(&mut self) -> RbUep6RxEnW<R8Uep567ModSpec> {
RbUep6RxEnW::new(self, 3)
}
#[doc = "Bit 4 - enable USB endpoint 7 transmittal (IN)"]
#[inline(always)]
pub fn rb_uep7_tx_en(&mut self) -> RbUep7TxEnW<R8Uep567ModSpec> {
RbUep7TxEnW::new(self, 4)
}
#[doc = "Bit 5 - enable USB endpoint 7 receiving (OUT)"]
#[inline(always)]
pub fn rb_uep7_rx_en(&mut self) -> RbUep7RxEnW<R8Uep567ModSpec> {
RbUep7RxEnW::new(self, 5)
}
}
#[doc = "endpoint 5/6/7 mode\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep567_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep567_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep567ModSpec;
impl crate::RegisterSpec for R8Uep567ModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep567_mod::R`](R) reader structure"]
impl crate::Readable for R8Uep567ModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep567_mod::W`](W) writer structure"]
impl crate::Writable for R8Uep567ModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP567_MOD to value 0"]
impl crate::Resettable for R8Uep567ModSpec {}
}
#[doc = "R16_UEP0_DMA (rw) register accessor: endpoint 0 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep0_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep0_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep0_dma`] module"]
#[doc(alias = "R16_UEP0_DMA")]
pub type R16Uep0Dma = crate::Reg<r16_uep0_dma::R16Uep0DmaSpec>;
#[doc = "endpoint 0 DMA buffer address"]
pub mod r16_uep0_dma {
#[doc = "Register `R16_UEP0_DMA` reader"]
pub type R = crate::R<R16Uep0DmaSpec>;
#[doc = "Register `R16_UEP0_DMA` writer"]
pub type W = crate::W<R16Uep0DmaSpec>;
#[doc = "Field `R16_UEP0_DMA` reader - RW,endpoint 0 DMA buffer address"]
pub type R16Uep0DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP0_DMA` writer - RW,endpoint 0 DMA buffer address"]
pub type R16Uep0DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 0 DMA buffer address"]
#[inline(always)]
pub fn r16_uep0_dma(&self) -> R16Uep0DmaR {
R16Uep0DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 0 DMA buffer address"]
#[inline(always)]
pub fn r16_uep0_dma(&mut self) -> R16Uep0DmaW<R16Uep0DmaSpec> {
R16Uep0DmaW::new(self, 0)
}
}
#[doc = "endpoint 0 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep0_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep0_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep0DmaSpec;
impl crate::RegisterSpec for R16Uep0DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep0_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep0DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep0_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep0DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP0_DMA to value 0"]
impl crate::Resettable for R16Uep0DmaSpec {}
}
#[doc = "R16_UEP1_DMA (rw) register accessor: endpoint 1 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep1_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep1_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep1_dma`] module"]
#[doc(alias = "R16_UEP1_DMA")]
pub type R16Uep1Dma = crate::Reg<r16_uep1_dma::R16Uep1DmaSpec>;
#[doc = "endpoint 1 DMA buffer address"]
pub mod r16_uep1_dma {
#[doc = "Register `R16_UEP1_DMA` reader"]
pub type R = crate::R<R16Uep1DmaSpec>;
#[doc = "Register `R16_UEP1_DMA` writer"]
pub type W = crate::W<R16Uep1DmaSpec>;
#[doc = "Field `R16_UEP1_DMA` reader - RW,endpoint 1 DMA buffer address"]
pub type R16Uep1DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP1_DMA` writer - RW,endpoint 1 DMA buffer address"]
pub type R16Uep1DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 1 DMA buffer address"]
#[inline(always)]
pub fn r16_uep1_dma(&self) -> R16Uep1DmaR {
R16Uep1DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 1 DMA buffer address"]
#[inline(always)]
pub fn r16_uep1_dma(&mut self) -> R16Uep1DmaW<R16Uep1DmaSpec> {
R16Uep1DmaW::new(self, 0)
}
}
#[doc = "endpoint 1 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep1_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep1_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep1DmaSpec;
impl crate::RegisterSpec for R16Uep1DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep1_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep1DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep1_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep1DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP1_DMA to value 0"]
impl crate::Resettable for R16Uep1DmaSpec {}
}
#[doc = "R16_UEP2_DMA (rw) register accessor: endpoint 2 DMA buffer address;host rx endpoint buffer high address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep2_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep2_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep2_dma`] module"]
#[doc(alias = "R16_UEP2_DMA")]
pub type R16Uep2Dma = crate::Reg<r16_uep2_dma::R16Uep2DmaSpec>;
#[doc = "endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
pub mod r16_uep2_dma {
#[doc = "Register `R16_UEP2_DMA` reader"]
pub type R = crate::R<R16Uep2DmaSpec>;
#[doc = "Register `R16_UEP2_DMA` writer"]
pub type W = crate::W<R16Uep2DmaSpec>;
#[doc = "Field `R16_UEP2_DMA` reader - RW,endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep2DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP2_DMA` writer - RW,endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep2DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep2_dma(&self) -> R16Uep2DmaR {
R16Uep2DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep2_dma(&mut self) -> R16Uep2DmaW<R16Uep2DmaSpec> {
R16Uep2DmaW::new(self, 0)
}
}
#[doc = "endpoint 2 DMA buffer address;host rx endpoint buffer high address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep2_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep2_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep2DmaSpec;
impl crate::RegisterSpec for R16Uep2DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep2_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep2DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep2_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep2DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP2_DMA to value 0"]
impl crate::Resettable for R16Uep2DmaSpec {}
}
#[doc = "R16_UEP3_DMA (rw) register accessor: endpoint 3 DMA buffer address;host tx endpoint buffer high address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep3_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep3_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep3_dma`] module"]
#[doc(alias = "R16_UEP3_DMA")]
pub type R16Uep3Dma = crate::Reg<r16_uep3_dma::R16Uep3DmaSpec>;
#[doc = "endpoint 3 DMA buffer address;host tx endpoint buffer high address"]
pub mod r16_uep3_dma {
#[doc = "Register `R16_UEP3_DMA` reader"]
pub type R = crate::R<R16Uep3DmaSpec>;
#[doc = "Register `R16_UEP3_DMA` writer"]
pub type W = crate::W<R16Uep3DmaSpec>;
#[doc = "Field `R16_UEP3_DMA` reader - RW,endpoint 3 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep3DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP3_DMA` writer - RW,endpoint 3 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep3DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 3 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep3_dma(&self) -> R16Uep3DmaR {
R16Uep3DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 3 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep3_dma(&mut self) -> R16Uep3DmaW<R16Uep3DmaSpec> {
R16Uep3DmaW::new(self, 0)
}
}
#[doc = "endpoint 3 DMA buffer address;host tx endpoint buffer high address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep3_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep3_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep3DmaSpec;
impl crate::RegisterSpec for R16Uep3DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep3_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep3DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep3_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep3DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP3_DMA to value 0"]
impl crate::Resettable for R16Uep3DmaSpec {}
}
#[doc = "R16_UEP5_DMA (rw) register accessor: endpoint 5 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep5_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep5_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep5_dma`] module"]
#[doc(alias = "R16_UEP5_DMA")]
pub type R16Uep5Dma = crate::Reg<r16_uep5_dma::R16Uep5DmaSpec>;
#[doc = "endpoint 5 DMA buffer address"]
pub mod r16_uep5_dma {
#[doc = "Register `R16_UEP5_DMA` reader"]
pub type R = crate::R<R16Uep5DmaSpec>;
#[doc = "Register `R16_UEP5_DMA` writer"]
pub type W = crate::W<R16Uep5DmaSpec>;
#[doc = "Field `R16_UEP5_DMA` reader - RW,endpoint 5 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep5DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP5_DMA` writer - RW,endpoint 5 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep5DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 5 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep5_dma(&self) -> R16Uep5DmaR {
R16Uep5DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 5 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep5_dma(&mut self) -> R16Uep5DmaW<R16Uep5DmaSpec> {
R16Uep5DmaW::new(self, 0)
}
}
#[doc = "endpoint 5 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep5_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep5_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep5DmaSpec;
impl crate::RegisterSpec for R16Uep5DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep5_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep5DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep5_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep5DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP5_DMA to value 0"]
impl crate::Resettable for R16Uep5DmaSpec {}
}
#[doc = "R16_UEP6_DMA (rw) register accessor: endpoint 6 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep6_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep6_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep6_dma`] module"]
#[doc(alias = "R16_UEP6_DMA")]
pub type R16Uep6Dma = crate::Reg<r16_uep6_dma::R16Uep6DmaSpec>;
#[doc = "endpoint 6 DMA buffer address"]
pub mod r16_uep6_dma {
#[doc = "Register `R16_UEP6_DMA` reader"]
pub type R = crate::R<R16Uep6DmaSpec>;
#[doc = "Register `R16_UEP6_DMA` writer"]
pub type W = crate::W<R16Uep6DmaSpec>;
#[doc = "Field `R16_UEP6_DMA` reader - RW,endpoint 6 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep6DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP6_DMA` writer - RW,endpoint 6 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep6DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 6 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep6_dma(&self) -> R16Uep6DmaR {
R16Uep6DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 6 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep6_dma(&mut self) -> R16Uep6DmaW<R16Uep6DmaSpec> {
R16Uep6DmaW::new(self, 0)
}
}
#[doc = "endpoint 6 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep6_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep6_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep6DmaSpec;
impl crate::RegisterSpec for R16Uep6DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep6_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep6DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep6_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep6DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP6_DMA to value 0"]
impl crate::Resettable for R16Uep6DmaSpec {}
}
#[doc = "R16_UEP7_DMA (rw) register accessor: endpoint 7 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep7_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep7_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep7_dma`] module"]
#[doc(alias = "R16_UEP7_DMA")]
pub type R16Uep7Dma = crate::Reg<r16_uep7_dma::R16Uep7DmaSpec>;
#[doc = "endpoint 7 DMA buffer address"]
pub mod r16_uep7_dma {
#[doc = "Register `R16_UEP7_DMA` reader"]
pub type R = crate::R<R16Uep7DmaSpec>;
#[doc = "Register `R16_UEP7_DMA` writer"]
pub type W = crate::W<R16Uep7DmaSpec>;
#[doc = "Field `R16_UEP7_DMA` reader - RW,endpoint 7 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep7DmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UEP7_DMA` writer - RW,endpoint 7 DMA buffer address;host rx endpoint buffer high address"]
pub type R16Uep7DmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RW,endpoint 7 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep7_dma(&self) -> R16Uep7DmaR {
R16Uep7DmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - RW,endpoint 7 DMA buffer address;host rx endpoint buffer high address"]
#[inline(always)]
pub fn r16_uep7_dma(&mut self) -> R16Uep7DmaW<R16Uep7DmaSpec> {
R16Uep7DmaW::new(self, 0)
}
}
#[doc = "endpoint 7 DMA buffer address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uep7_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uep7_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16Uep7DmaSpec;
impl crate::RegisterSpec for R16Uep7DmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uep7_dma::R`](R) reader structure"]
impl crate::Readable for R16Uep7DmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uep7_dma::W`](W) writer structure"]
impl crate::Writable for R16Uep7DmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UEP7_DMA to value 0"]
impl crate::Resettable for R16Uep7DmaSpec {}
}
#[doc = "R8_UEP0_T_LEN (rw) register accessor: endpoint 0 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep0_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep0_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep0_t_len`] module"]
#[doc(alias = "R8_UEP0_T_LEN")]
pub type R8Uep0TLen = crate::Reg<r8_uep0_t_len::R8Uep0TLenSpec>;
#[doc = "endpoint 0 transmittal length"]
pub mod r8_uep0_t_len {
#[doc = "Register `R8_UEP0_T_LEN` reader"]
pub type R = crate::R<R8Uep0TLenSpec>;
#[doc = "Register `R8_UEP0_T_LEN` writer"]
pub type W = crate::W<R8Uep0TLenSpec>;
#[doc = "Field `R8_UEP0_T_LEN` reader - endpoint 0 transmittal length"]
pub type R8Uep0TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP0_T_LEN` writer - endpoint 0 transmittal length"]
pub type R8Uep0TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 0 transmittal length"]
#[inline(always)]
pub fn r8_uep0_t_len(&self) -> R8Uep0TLenR {
R8Uep0TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 0 transmittal length"]
#[inline(always)]
pub fn r8_uep0_t_len(&mut self) -> R8Uep0TLenW<R8Uep0TLenSpec> {
R8Uep0TLenW::new(self, 0)
}
}
#[doc = "endpoint 0 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep0_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep0_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep0TLenSpec;
impl crate::RegisterSpec for R8Uep0TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep0_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep0TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep0_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep0TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP0_T_LEN to value 0"]
impl crate::Resettable for R8Uep0TLenSpec {}
}
#[doc = "R8_UEP0_CTRL (rw) register accessor: endpoint 0 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep0_ctrl`] module"]
#[doc(alias = "R8_UEP0_CTRL")]
pub type R8Uep0Ctrl = crate::Reg<r8_uep0_ctrl::R8Uep0CtrlSpec>;
#[doc = "endpoint 0 control"]
pub mod r8_uep0_ctrl {
#[doc = "Register `R8_UEP0_CTRL` reader"]
pub type R = crate::R<R8Uep0CtrlSpec>;
#[doc = "Register `R8_UEP0_CTRL` writer"]
pub type W = crate::W<R8Uep0CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep0CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep0CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep0CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep0CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep0CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 0 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep0CtrlSpec;
impl crate::RegisterSpec for R8Uep0CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep0_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep0CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep0_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep0CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP0_CTRL to value 0"]
impl crate::Resettable for R8Uep0CtrlSpec {}
}
#[doc = "R8_UEP1_T_LEN (rw) register accessor: endpoint 1 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep1_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep1_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep1_t_len`] module"]
#[doc(alias = "R8_UEP1_T_LEN")]
pub type R8Uep1TLen = crate::Reg<r8_uep1_t_len::R8Uep1TLenSpec>;
#[doc = "endpoint 1 transmittal length"]
pub mod r8_uep1_t_len {
#[doc = "Register `R8_UEP1_T_LEN` reader"]
pub type R = crate::R<R8Uep1TLenSpec>;
#[doc = "Register `R8_UEP1_T_LEN` writer"]
pub type W = crate::W<R8Uep1TLenSpec>;
#[doc = "Field `R8_UEP1_T_LEN` reader - endpoint 1 transmittal length"]
pub type R8Uep1TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP1_T_LEN` writer - endpoint 1 transmittal length"]
pub type R8Uep1TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 1 transmittal length"]
#[inline(always)]
pub fn r8_uep1_t_len(&self) -> R8Uep1TLenR {
R8Uep1TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 1 transmittal length"]
#[inline(always)]
pub fn r8_uep1_t_len(&mut self) -> R8Uep1TLenW<R8Uep1TLenSpec> {
R8Uep1TLenW::new(self, 0)
}
}
#[doc = "endpoint 1 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep1_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep1_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep1TLenSpec;
impl crate::RegisterSpec for R8Uep1TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep1_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep1TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep1_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep1TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP1_T_LEN to value 0"]
impl crate::Resettable for R8Uep1TLenSpec {}
}
#[doc = "R8_UEP1_CTRL (rw) register accessor: endpoint 1 control;host aux setup\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep1_ctrl`] module"]
#[doc(alias = "R8_UEP1_CTRL")]
pub type R8Uep1Ctrl = crate::Reg<r8_uep1_ctrl::R8Uep1CtrlSpec>;
#[doc = "endpoint 1 control;host aux setup"]
pub mod r8_uep1_ctrl {
#[doc = "Register `R8_UEP1_CTRL` reader"]
pub type R = crate::R<R8Uep1CtrlSpec>;
#[doc = "Register `R8_UEP1_CTRL` writer"]
pub type W = crate::W<R8Uep1CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep1CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep1CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep1CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep1CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep1CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 1 control;host aux setup\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep1CtrlSpec;
impl crate::RegisterSpec for R8Uep1CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep1_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep1CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep1_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep1CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP1_CTRL to value 0"]
impl crate::Resettable for R8Uep1CtrlSpec {}
}
#[doc = "R8_UEP2_T_LEN (rw) register accessor: endpoint 2 transmittal length;host endpoint and PID\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_t_len`] module"]
#[doc(alias = "R8_UEP2_T_LEN")]
pub type R8Uep2TLen = crate::Reg<r8_uep2_t_len::R8Uep2TLenSpec>;
#[doc = "endpoint 2 transmittal length;host endpoint and PID"]
pub mod r8_uep2_t_len {
#[doc = "Register `R8_UEP2_T_LEN` reader"]
pub type R = crate::R<R8Uep2TLenSpec>;
#[doc = "Register `R8_UEP2_T_LEN` writer"]
pub type W = crate::W<R8Uep2TLenSpec>;
#[doc = "Field `R8_UEP2_T_LEN` reader - Set the number of data bytes to be sent by USB endpoint n"]
pub type R8Uep2TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP2_T_LEN` writer - Set the number of data bytes to be sent by USB endpoint n"]
pub type R8Uep2TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `R8_UEP2_HOST_PID3` reader - The token in host mode identifies the bit3 of the PID"]
pub type R8Uep2HostPid3R = crate::BitReader;
#[doc = "Field `R8_UEP2_HOST_PID3` writer - The token in host mode identifies the bit3 of the PID"]
pub type R8Uep2HostPid3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:6 - Set the number of data bytes to be sent by USB endpoint n"]
#[inline(always)]
pub fn r8_uep2_t_len(&self) -> R8Uep2TLenR {
R8Uep2TLenR::new(self.bits & 0x7f)
}
#[doc = "Bit 7 - The token in host mode identifies the bit3 of the PID"]
#[inline(always)]
pub fn r8_uep2_host_pid3(&self) -> R8Uep2HostPid3R {
R8Uep2HostPid3R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6 - Set the number of data bytes to be sent by USB endpoint n"]
#[inline(always)]
pub fn r8_uep2_t_len(&mut self) -> R8Uep2TLenW<R8Uep2TLenSpec> {
R8Uep2TLenW::new(self, 0)
}
#[doc = "Bit 7 - The token in host mode identifies the bit3 of the PID"]
#[inline(always)]
pub fn r8_uep2_host_pid3(&mut self) -> R8Uep2HostPid3W<R8Uep2TLenSpec> {
R8Uep2HostPid3W::new(self, 7)
}
}
#[doc = "endpoint 2 transmittal length;host endpoint and PID\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep2TLenSpec;
impl crate::RegisterSpec for R8Uep2TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep2_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep2TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep2_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep2TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP2_T_LEN to value 0"]
impl crate::Resettable for R8Uep2TLenSpec {}
}
#[doc = "R8_UEP2_CTRL (rw) register accessor: endpoint 2 control;host receiver endpoint control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_ctrl`] module"]
#[doc(alias = "R8_UEP2_CTRL")]
pub type R8Uep2Ctrl = crate::Reg<r8_uep2_ctrl::R8Uep2CtrlSpec>;
#[doc = "endpoint 2 control;host receiver endpoint control"]
pub mod r8_uep2_ctrl {
#[doc = "Register `R8_UEP2_CTRL` reader"]
pub type R = crate::R<R8Uep2CtrlSpec>;
#[doc = "Register `R8_UEP2_CTRL` writer"]
pub type W = crate::W<R8Uep2CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UH_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUhRResR = crate::BitReader;
#[doc = "Field `MASK_UH_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUhRResW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bit 2 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uh_r_res(&self) -> MaskUhRResR {
MaskUhRResR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep2CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bit 2 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uh_r_res(&mut self) -> MaskUhRResW<R8Uep2CtrlSpec> {
MaskUhRResW::new(self, 2)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep2CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep2CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep2CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep2CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 2 control;host receiver endpoint control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep2CtrlSpec;
impl crate::RegisterSpec for R8Uep2CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep2_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep2CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep2_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep2CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP2_CTRL to value 0"]
impl crate::Resettable for R8Uep2CtrlSpec {}
}
#[doc = "R8_UEP3_T_LEN (rw) register accessor: endpoint 3 transmittal length;host transmittal endpoint transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep3_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep3_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep3_t_len`] module"]
#[doc(alias = "R8_UEP3_T_LEN")]
pub type R8Uep3TLen = crate::Reg<r8_uep3_t_len::R8Uep3TLenSpec>;
#[doc = "endpoint 3 transmittal length;host transmittal endpoint transmittal length"]
pub mod r8_uep3_t_len {
#[doc = "Register `R8_UEP3_T_LEN` reader"]
pub type R = crate::R<R8Uep3TLenSpec>;
#[doc = "Register `R8_UEP3_T_LEN` writer"]
pub type W = crate::W<R8Uep3TLenSpec>;
#[doc = "Field `R8_UEP3_T_LEN` reader - endpoint 1 transmittal length"]
pub type R8Uep3TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP3_T_LEN` writer - endpoint 1 transmittal length"]
pub type R8Uep3TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 1 transmittal length"]
#[inline(always)]
pub fn r8_uep3_t_len(&self) -> R8Uep3TLenR {
R8Uep3TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 1 transmittal length"]
#[inline(always)]
pub fn r8_uep3_t_len(&mut self) -> R8Uep3TLenW<R8Uep3TLenSpec> {
R8Uep3TLenW::new(self, 0)
}
}
#[doc = "endpoint 3 transmittal length;host transmittal endpoint transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep3_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep3_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep3TLenSpec;
impl crate::RegisterSpec for R8Uep3TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep3_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep3TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep3_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep3TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP3_T_LEN to value 0"]
impl crate::Resettable for R8Uep3TLenSpec {}
}
#[doc = "R8_UEP3_CTRL (rw) register accessor: endpoint 3 control;host transmittal endpoint control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep3_ctrl`] module"]
#[doc(alias = "R8_UEP3_CTRL")]
pub type R8Uep3Ctrl = crate::Reg<r8_uep3_ctrl::R8Uep3CtrlSpec>;
#[doc = "endpoint 3 control;host transmittal endpoint control"]
pub mod r8_uep3_ctrl {
#[doc = "Register `R8_UEP3_CTRL` reader"]
pub type R = crate::R<R8Uep3CtrlSpec>;
#[doc = "Register `R8_UEP3_CTRL` writer"]
pub type W = crate::W<R8Uep3CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep3CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep3CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep3CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep3CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep3CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 3 control;host transmittal endpoint control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep3CtrlSpec;
impl crate::RegisterSpec for R8Uep3CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep3_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep3CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep3_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep3CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP3_CTRL to value 0"]
impl crate::Resettable for R8Uep3CtrlSpec {}
}
#[doc = "R8_UEP4_T_LEN (rw) register accessor: endpoint 4 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_t_len`] module"]
#[doc(alias = "R8_UEP4_T_LEN")]
pub type R8Uep4TLen = crate::Reg<r8_uep4_t_len::R8Uep4TLenSpec>;
#[doc = "endpoint 4 transmittal length"]
pub mod r8_uep4_t_len {
#[doc = "Register `R8_UEP4_T_LEN` reader"]
pub type R = crate::R<R8Uep4TLenSpec>;
#[doc = "Register `R8_UEP4_T_LEN` writer"]
pub type W = crate::W<R8Uep4TLenSpec>;
#[doc = "Field `R8_UEP4_T_LEN` reader - endpoint 4 transmittal length"]
pub type R8Uep4TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP4_T_LEN` writer - endpoint 4 transmittal length"]
pub type R8Uep4TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 4 transmittal length"]
#[inline(always)]
pub fn r8_uep4_t_len(&self) -> R8Uep4TLenR {
R8Uep4TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 4 transmittal length"]
#[inline(always)]
pub fn r8_uep4_t_len(&mut self) -> R8Uep4TLenW<R8Uep4TLenSpec> {
R8Uep4TLenW::new(self, 0)
}
}
#[doc = "endpoint 4 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep4TLenSpec;
impl crate::RegisterSpec for R8Uep4TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep4_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep4TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep4_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep4TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP4_T_LEN to value 0"]
impl crate::Resettable for R8Uep4TLenSpec {}
}
#[doc = "R8_UEP4_CTRL (rw) register accessor: endpoint 4 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_ctrl`] module"]
#[doc(alias = "R8_UEP4_CTRL")]
pub type R8Uep4Ctrl = crate::Reg<r8_uep4_ctrl::R8Uep4CtrlSpec>;
#[doc = "endpoint 4 control"]
pub mod r8_uep4_ctrl {
#[doc = "Register `R8_UEP4_CTRL` reader"]
pub type R = crate::R<R8Uep4CtrlSpec>;
#[doc = "Register `R8_UEP4_CTRL` writer"]
pub type W = crate::W<R8Uep4CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep4CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep4CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep4CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep4CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep4CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 4 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep4_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep4_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep4CtrlSpec;
impl crate::RegisterSpec for R8Uep4CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep4_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep4CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep4_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep4CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP4_CTRL to value 0"]
impl crate::Resettable for R8Uep4CtrlSpec {}
}
#[doc = "R8_UEP5_T_LEN (rw) register accessor: endpoint 5 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep5_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep5_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep5_t_len`] module"]
#[doc(alias = "R8_UEP5_T_LEN")]
pub type R8Uep5TLen = crate::Reg<r8_uep5_t_len::R8Uep5TLenSpec>;
#[doc = "endpoint 5 transmittal length"]
pub mod r8_uep5_t_len {
#[doc = "Register `R8_UEP5_T_LEN` reader"]
pub type R = crate::R<R8Uep5TLenSpec>;
#[doc = "Register `R8_UEP5_T_LEN` writer"]
pub type W = crate::W<R8Uep5TLenSpec>;
#[doc = "Field `R8_UEP5_T_LEN` reader - endpoint 5 transmittal length"]
pub type R8Uep5TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP5_T_LEN` writer - endpoint 5 transmittal length"]
pub type R8Uep5TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 5 transmittal length"]
#[inline(always)]
pub fn r8_uep5_t_len(&self) -> R8Uep5TLenR {
R8Uep5TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 5 transmittal length"]
#[inline(always)]
pub fn r8_uep5_t_len(&mut self) -> R8Uep5TLenW<R8Uep5TLenSpec> {
R8Uep5TLenW::new(self, 0)
}
}
#[doc = "endpoint 5 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep5_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep5_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep5TLenSpec;
impl crate::RegisterSpec for R8Uep5TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep5_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep5TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep5_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep5TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP5_T_LEN to value 0"]
impl crate::Resettable for R8Uep5TLenSpec {}
}
#[doc = "R8_UEP5_CTRL (rw) register accessor: endpoint 5 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep5_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep5_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep5_ctrl`] module"]
#[doc(alias = "R8_UEP5_CTRL")]
pub type R8Uep5Ctrl = crate::Reg<r8_uep5_ctrl::R8Uep5CtrlSpec>;
#[doc = "endpoint 5 control"]
pub mod r8_uep5_ctrl {
#[doc = "Register `R8_UEP5_CTRL` reader"]
pub type R = crate::R<R8Uep5CtrlSpec>;
#[doc = "Register `R8_UEP5_CTRL` writer"]
pub type W = crate::W<R8Uep5CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep5CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep5CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep5CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep5CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep5CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 5 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep5_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep5_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep5CtrlSpec;
impl crate::RegisterSpec for R8Uep5CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep5_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep5CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep5_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep5CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP5_CTRL to value 0"]
impl crate::Resettable for R8Uep5CtrlSpec {}
}
#[doc = "R8_UEP6_T_LEN (rw) register accessor: endpoint 6 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep6_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep6_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep6_t_len`] module"]
#[doc(alias = "R8_UEP6_T_LEN")]
pub type R8Uep6TLen = crate::Reg<r8_uep6_t_len::R8Uep6TLenSpec>;
#[doc = "endpoint 6 transmittal length"]
pub mod r8_uep6_t_len {
#[doc = "Register `R8_UEP6_T_LEN` reader"]
pub type R = crate::R<R8Uep6TLenSpec>;
#[doc = "Register `R8_UEP6_T_LEN` writer"]
pub type W = crate::W<R8Uep6TLenSpec>;
#[doc = "Field `R8_UEP6_T_LEN` reader - endpoint 6 transmittal length"]
pub type R8Uep6TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP6_T_LEN` writer - endpoint 6 transmittal length"]
pub type R8Uep6TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 6 transmittal length"]
#[inline(always)]
pub fn r8_uep6_t_len(&self) -> R8Uep6TLenR {
R8Uep6TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 6 transmittal length"]
#[inline(always)]
pub fn r8_uep6_t_len(&mut self) -> R8Uep6TLenW<R8Uep6TLenSpec> {
R8Uep6TLenW::new(self, 0)
}
}
#[doc = "endpoint 6 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep6_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep6_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep6TLenSpec;
impl crate::RegisterSpec for R8Uep6TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep6_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep6TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep6_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep6TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP6_T_LEN to value 0"]
impl crate::Resettable for R8Uep6TLenSpec {}
}
#[doc = "R8_UEP6_CTRL (rw) register accessor: endpoint 6 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep6_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep6_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep6_ctrl`] module"]
#[doc(alias = "R8_UEP6_CTRL")]
pub type R8Uep6Ctrl = crate::Reg<r8_uep6_ctrl::R8Uep6CtrlSpec>;
#[doc = "endpoint 6 control"]
pub mod r8_uep6_ctrl {
#[doc = "Register `R8_UEP6_CTRL` reader"]
pub type R = crate::R<R8Uep6CtrlSpec>;
#[doc = "Register `R8_UEP6_CTRL` writer"]
pub type W = crate::W<R8Uep6CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep6CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep6CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep6CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep6CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep6CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 6 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep6_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep6_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep6CtrlSpec;
impl crate::RegisterSpec for R8Uep6CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep6_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep6CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep6_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep6CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP6_CTRL to value 0"]
impl crate::Resettable for R8Uep6CtrlSpec {}
}
#[doc = "R8_UEP7_T_LEN (rw) register accessor: endpoint 7 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep7_t_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep7_t_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep7_t_len`] module"]
#[doc(alias = "R8_UEP7_T_LEN")]
pub type R8Uep7TLen = crate::Reg<r8_uep7_t_len::R8Uep7TLenSpec>;
#[doc = "endpoint 7 transmittal length"]
pub mod r8_uep7_t_len {
#[doc = "Register `R8_UEP7_T_LEN` reader"]
pub type R = crate::R<R8Uep7TLenSpec>;
#[doc = "Register `R8_UEP7_T_LEN` writer"]
pub type W = crate::W<R8Uep7TLenSpec>;
#[doc = "Field `R8_UEP7_T_LEN` reader - endpoint 7 transmittal length"]
pub type R8Uep7TLenR = crate::FieldReader;
#[doc = "Field `R8_UEP7_T_LEN` writer - endpoint 7 transmittal length"]
pub type R8Uep7TLenW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - endpoint 7 transmittal length"]
#[inline(always)]
pub fn r8_uep7_t_len(&self) -> R8Uep7TLenR {
R8Uep7TLenR::new(self.bits & 0x7f)
}
}
impl W {
#[doc = "Bits 0:6 - endpoint 7 transmittal length"]
#[inline(always)]
pub fn r8_uep7_t_len(&mut self) -> R8Uep7TLenW<R8Uep7TLenSpec> {
R8Uep7TLenW::new(self, 0)
}
}
#[doc = "endpoint 7 transmittal length\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep7_t_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep7_t_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep7TLenSpec;
impl crate::RegisterSpec for R8Uep7TLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep7_t_len::R`](R) reader structure"]
impl crate::Readable for R8Uep7TLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep7_t_len::W`](W) writer structure"]
impl crate::Writable for R8Uep7TLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP7_T_LEN to value 0"]
impl crate::Resettable for R8Uep7TLenSpec {}
}
#[doc = "R8_UEP7_CTRL (rw) register accessor: endpoint 7 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep7_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep7_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep7_ctrl`] module"]
#[doc(alias = "R8_UEP7_CTRL")]
pub type R8Uep7Ctrl = crate::Reg<r8_uep7_ctrl::R8Uep7CtrlSpec>;
#[doc = "endpoint 7 control"]
pub mod r8_uep7_ctrl {
#[doc = "Register `R8_UEP7_CTRL` reader"]
pub type R = crate::R<R8Uep7CtrlSpec>;
#[doc = "Register `R8_UEP7_CTRL` writer"]
pub type W = crate::W<R8Uep7CtrlSpec>;
#[doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MaskUepTResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResR = crate::FieldReader;
#[doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MaskUepRResW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogR = crate::BitReader;
#[doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
pub type RbUepAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogR = crate::BitReader;
#[doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RbUepTTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogR = crate::BitReader;
#[doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RbUepRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&self) -> MaskUepTResR {
MaskUepTResR::new(self.bits & 3)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&self) -> MaskUepRResR {
MaskUepRResR::new((self.bits >> 2) & 3)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&self) -> RbUepAutoTogR {
RbUepAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&self) -> RbUepTTogR {
RbUepTTogR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&self) -> RbUepRTogR {
RbUepRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
#[inline(always)]
pub fn mask_uep_t_res(&mut self) -> MaskUepTResW<R8Uep7CtrlSpec> {
MaskUepTResW::new(self, 0)
}
#[doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
#[inline(always)]
pub fn mask_uep_r_res(&mut self) -> MaskUepRResW<R8Uep7CtrlSpec> {
MaskUepRResW::new(self, 2)
}
#[doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle"]
#[inline(always)]
pub fn rb_uep_auto_tog(&mut self) -> RbUepAutoTogW<R8Uep7CtrlSpec> {
RbUepAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_t_tog(&mut self) -> RbUepTTogW<R8Uep7CtrlSpec> {
RbUepTTogW::new(self, 6)
}
#[doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
#[inline(always)]
pub fn rb_uep_r_tog(&mut self) -> RbUepRTogW<R8Uep7CtrlSpec> {
RbUepRTogW::new(self, 7)
}
}
#[doc = "endpoint 7 control\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uep7_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uep7_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8Uep7CtrlSpec;
impl crate::RegisterSpec for R8Uep7CtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uep7_ctrl::R`](R) reader structure"]
impl crate::Readable for R8Uep7CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uep7_ctrl::W`](W) writer structure"]
impl crate::Writable for R8Uep7CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UEP7_CTRL to value 0"]
impl crate::Resettable for R8Uep7CtrlSpec {}
}
#[doc = "R32_EPn_MODE (rw) register accessor: endpoint n control,（n=8/10/11/12/13/14/15）\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_epn_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_epn_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_epn_mode`] module"]
#[doc(alias = "R32_EPn_MODE")]
pub type R32EpnMode = crate::Reg<r32_epn_mode::R32EpnModeSpec>;
#[doc = "endpoint n control,（n=8/10/11/12/13/14/15）"]
pub mod r32_epn_mode {
#[doc = "Register `R32_EPn_MODE` reader"]
pub type R = crate::R<R32EpnModeSpec>;
#[doc = "Register `R32_EPn_MODE` writer"]
pub type W = crate::W<R32EpnModeSpec>;
#[doc = "Field `RB_EP_T_EN` reader - 1: Enable endpoint 8-15 to send (IN); 0: Prohibit endpoints 8-15 from sending"]
pub type RbEpTEnR = crate::FieldReader;
#[doc = "Field `RB_EP_T_EN` writer - 1: Enable endpoint 8-15 to send (IN); 0: Prohibit endpoints 8-15 from sending"]
pub type RbEpTEnW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RB_EP_R_EN` reader - 1: Enable endpoints 8-15 to receive (OUT); 0: Prohibit endpoints 8-15 from receiving"]
pub type RbEpREnR = crate::FieldReader;
#[doc = "Field `RB_EP_R_EN` writer - 1: Enable endpoints 8-15 to receive (OUT); 0: Prohibit endpoints 8-15 from receiving"]
pub type RbEpREnW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RB_EP_T_AF` reader - 1: Enable endpoints 8-15 to send multiplexing; 0: Prohibit endpoints 8-15 from sending multiplexed messages"]
pub type RbEpTAfR = crate::FieldReader;
#[doc = "Field `RB_EP_T_AF` writer - 1: Enable endpoints 8-15 to send multiplexing; 0: Prohibit endpoints 8-15 from sending multiplexed messages"]
pub type RbEpTAfW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:7 - 1: Enable endpoint 8-15 to send (IN); 0: Prohibit endpoints 8-15 from sending"]
#[inline(always)]
pub fn rb_ep_t_en(&self) -> RbEpTEnR {
RbEpTEnR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - 1: Enable endpoints 8-15 to receive (OUT); 0: Prohibit endpoints 8-15 from receiving"]
#[inline(always)]
pub fn rb_ep_r_en(&self) -> RbEpREnR {
RbEpREnR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 17:23 - 1: Enable endpoints 8-15 to send multiplexing; 0: Prohibit endpoints 8-15 from sending multiplexed messages"]
#[inline(always)]
pub fn rb_ep_t_af(&self) -> RbEpTAfR {
RbEpTAfR::new(((self.bits >> 17) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - 1: Enable endpoint 8-15 to send (IN); 0: Prohibit endpoints 8-15 from sending"]
#[inline(always)]
pub fn rb_ep_t_en(&mut self) -> RbEpTEnW<R32EpnModeSpec> {
RbEpTEnW::new(self, 0)
}
#[doc = "Bits 8:15 - 1: Enable endpoints 8-15 to receive (OUT); 0: Prohibit endpoints 8-15 from receiving"]
#[inline(always)]
pub fn rb_ep_r_en(&mut self) -> RbEpREnW<R32EpnModeSpec> {
RbEpREnW::new(self, 8)
}
#[doc = "Bits 17:23 - 1: Enable endpoints 8-15 to send multiplexing; 0: Prohibit endpoints 8-15 from sending multiplexed messages"]
#[inline(always)]
pub fn rb_ep_t_af(&mut self) -> RbEpTAfW<R32EpnModeSpec> {
RbEpTAfW::new(self, 17)
}
}
#[doc = "endpoint n control,（n=8/10/11/12/13/14/15）\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_epn_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_epn_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32EpnModeSpec;
impl crate::RegisterSpec for R32EpnModeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_epn_mode::R`](R) reader structure"]
impl crate::Readable for R32EpnModeSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_epn_mode::W`](W) writer structure"]
impl crate::Writable for R32EpnModeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_EPn_MODE to value 0"]
impl crate::Resettable for R32EpnModeSpec {}
}
#[doc = "R8_UHOST_CTRL (rw) register accessor: USB host physical port control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uhost_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uhost_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uhost_ctrl`] module"]
#[doc(alias = "R8_UHOST_CTRL")]
pub type R8UhostCtrl = crate::Reg<r8_uhost_ctrl::R8UhostCtrlSpec>;
#[doc = "USB host physical port control register"]
pub mod r8_uhost_ctrl {
#[doc = "Register `R8_UHOST_CTRL` reader"]
pub type R = crate::R<R8UhostCtrlSpec>;
#[doc = "Register `R8_UHOST_CTRL` writer"]
pub type W = crate::W<R8UhostCtrlSpec>;
#[doc = "Field `RB_UH_PORT_EN` reader - USB host port enable bit"]
pub type RbUhPortEnR = crate::BitReader;
#[doc = "Field `RB_UH_PORT_EN` writer - USB host port enable bit"]
pub type RbUhPortEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_BUS_RESET` reader - USB host mode bus reset control bit"]
pub type RbUhBusResetR = crate::BitReader;
#[doc = "Field `RB_UH_BUS_RESET` writer - USB host mode bus reset control bit"]
pub type RbUhBusResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_LOW_SPEED` reader - USB host port low-speed mode enable bit"]
pub type RbUhLowSpeedR = crate::BitReader;
#[doc = "Field `RB_UH_LOW_SPEED` writer - USB host port low-speed mode enable bit"]
pub type RbUhLowSpeedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_DM_PIN` reader - Current UD- pin status"]
pub type RbUhDmPinR = crate::BitReader;
#[doc = "Field `RB_UH_DM_PIN` writer - Current UD- pin status"]
pub type RbUhDmPinW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_DP_PIN` reader - Current UD+ pin status"]
pub type RbUhDpPinR = crate::BitReader;
#[doc = "Field `RB_UH_DP_PIN` writer - Current UD+ pin status"]
pub type RbUhDpPinW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_PD_DIS` reader - USB host port UD+/UD - pin internal pull-down resistor control bit"]
pub type RbUhPdDisR = crate::BitReader;
#[doc = "Field `RB_UH_PD_DIS` writer - USB host port UD+/UD - pin internal pull-down resistor control bit"]
pub type RbUhPdDisW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USB host port enable bit"]
#[inline(always)]
pub fn rb_uh_port_en(&self) -> RbUhPortEnR {
RbUhPortEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USB host mode bus reset control bit"]
#[inline(always)]
pub fn rb_uh_bus_reset(&self) -> RbUhBusResetR {
RbUhBusResetR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - USB host port low-speed mode enable bit"]
#[inline(always)]
pub fn rb_uh_low_speed(&self) -> RbUhLowSpeedR {
RbUhLowSpeedR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Current UD- pin status"]
#[inline(always)]
pub fn rb_uh_dm_pin(&self) -> RbUhDmPinR {
RbUhDmPinR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Current UD+ pin status"]
#[inline(always)]
pub fn rb_uh_dp_pin(&self) -> RbUhDpPinR {
RbUhDpPinR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - USB host port UD+/UD - pin internal pull-down resistor control bit"]
#[inline(always)]
pub fn rb_uh_pd_dis(&self) -> RbUhPdDisR {
RbUhPdDisR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USB host port enable bit"]
#[inline(always)]
pub fn rb_uh_port_en(&mut self) -> RbUhPortEnW<R8UhostCtrlSpec> {
RbUhPortEnW::new(self, 0)
}
#[doc = "Bit 1 - USB host mode bus reset control bit"]
#[inline(always)]
pub fn rb_uh_bus_reset(&mut self) -> RbUhBusResetW<R8UhostCtrlSpec> {
RbUhBusResetW::new(self, 1)
}
#[doc = "Bit 2 - USB host port low-speed mode enable bit"]
#[inline(always)]
pub fn rb_uh_low_speed(&mut self) -> RbUhLowSpeedW<R8UhostCtrlSpec> {
RbUhLowSpeedW::new(self, 2)
}
#[doc = "Bit 4 - Current UD- pin status"]
#[inline(always)]
pub fn rb_uh_dm_pin(&mut self) -> RbUhDmPinW<R8UhostCtrlSpec> {
RbUhDmPinW::new(self, 4)
}
#[doc = "Bit 5 - Current UD+ pin status"]
#[inline(always)]
pub fn rb_uh_dp_pin(&mut self) -> RbUhDpPinW<R8UhostCtrlSpec> {
RbUhDpPinW::new(self, 5)
}
#[doc = "Bit 7 - USB host port UD+/UD - pin internal pull-down resistor control bit"]
#[inline(always)]
pub fn rb_uh_pd_dis(&mut self) -> RbUhPdDisW<R8UhostCtrlSpec> {
RbUhPdDisW::new(self, 7)
}
}
#[doc = "USB host physical port control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uhost_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uhost_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhostCtrlSpec;
impl crate::RegisterSpec for R8UhostCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uhost_ctrl::R`](R) reader structure"]
impl crate::Readable for R8UhostCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uhost_ctrl::W`](W) writer structure"]
impl crate::Writable for R8UhostCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UHOST_CTRL to value 0"]
impl crate::Resettable for R8UhostCtrlSpec {}
}
#[doc = "R8_UH_EP_MOD (rw) register accessor: USB host endpoint mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_ep_mod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_ep_mod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_ep_mod`] module"]
#[doc(alias = "R8_UH_EP_MOD")]
pub type R8UhEpMod = crate::Reg<r8_uh_ep_mod::R8UhEpModSpec>;
#[doc = "USB host endpoint mode control register"]
pub mod r8_uh_ep_mod {
#[doc = "Register `R8_UH_EP_MOD` reader"]
pub type R = crate::R<R8UhEpModSpec>;
#[doc = "Register `R8_UH_EP_MOD` writer"]
pub type W = crate::W<R8UhEpModSpec>;
#[doc = "Field `RB_UH_EP_RBUF_MOD` reader - USB host receiving endpoint receiving data buffer mode control bit"]
pub type RbUhEpRbufModR = crate::BitReader;
#[doc = "Field `RB_UH_EP_RBUF_MOD` writer - USB host receiving endpoint receiving data buffer mode control bit"]
pub type RbUhEpRbufModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_EP_RX_EN` reader - Host receiving endpoint receiving (IN) enable bit"]
pub type RbUhEpRxEnR = crate::BitReader;
#[doc = "Field `RB_UH_EP_RX_EN` writer - Host receiving endpoint receiving (IN) enable bit"]
pub type RbUhEpRxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_EP_TBUF_MOD` reader - Host sends endpoint sends data buffer mode control bit"]
pub type RbUhEpTbufModR = crate::BitReader;
#[doc = "Field `RB_UH_EP_TBUF_MOD` writer - Host sends endpoint sends data buffer mode control bit"]
pub type RbUhEpTbufModW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_EP_TX_EN` reader - Host sends endpoint send (SETUP/OUT) enable bit"]
pub type RbUhEpTxEnR = crate::BitReader;
#[doc = "Field `RB_UH_EP_TX_EN` writer - Host sends endpoint send (SETUP/OUT) enable bit"]
pub type RbUhEpTxEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USB host receiving endpoint receiving data buffer mode control bit"]
#[inline(always)]
pub fn rb_uh_ep_rbuf_mod(&self) -> RbUhEpRbufModR {
RbUhEpRbufModR::new((self.bits & 1) != 0)
}
#[doc = "Bit 3 - Host receiving endpoint receiving (IN) enable bit"]
#[inline(always)]
pub fn rb_uh_ep_rx_en(&self) -> RbUhEpRxEnR {
RbUhEpRxEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Host sends endpoint sends data buffer mode control bit"]
#[inline(always)]
pub fn rb_uh_ep_tbuf_mod(&self) -> RbUhEpTbufModR {
RbUhEpTbufModR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - Host sends endpoint send (SETUP/OUT) enable bit"]
#[inline(always)]
pub fn rb_uh_ep_tx_en(&self) -> RbUhEpTxEnR {
RbUhEpTxEnR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USB host receiving endpoint receiving data buffer mode control bit"]
#[inline(always)]
pub fn rb_uh_ep_rbuf_mod(&mut self) -> RbUhEpRbufModW<R8UhEpModSpec> {
RbUhEpRbufModW::new(self, 0)
}
#[doc = "Bit 3 - Host receiving endpoint receiving (IN) enable bit"]
#[inline(always)]
pub fn rb_uh_ep_rx_en(&mut self) -> RbUhEpRxEnW<R8UhEpModSpec> {
RbUhEpRxEnW::new(self, 3)
}
#[doc = "Bit 4 - Host sends endpoint sends data buffer mode control bit"]
#[inline(always)]
pub fn rb_uh_ep_tbuf_mod(&mut self) -> RbUhEpTbufModW<R8UhEpModSpec> {
RbUhEpTbufModW::new(self, 4)
}
#[doc = "Bit 6 - Host sends endpoint send (SETUP/OUT) enable bit"]
#[inline(always)]
pub fn rb_uh_ep_tx_en(&mut self) -> RbUhEpTxEnW<R8UhEpModSpec> {
RbUhEpTxEnW::new(self, 6)
}
}
#[doc = "USB host endpoint mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_ep_mod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_ep_mod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhEpModSpec;
impl crate::RegisterSpec for R8UhEpModSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_ep_mod::R`](R) reader structure"]
impl crate::Readable for R8UhEpModSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_ep_mod::W`](W) writer structure"]
impl crate::Writable for R8UhEpModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_EP_MOD to value 0"]
impl crate::Resettable for R8UhEpModSpec {}
}
#[doc = "R16_UH_RX_DMA (rw) register accessor: USB host receiving buffer starting address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uh_rx_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uh_rx_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uh_rx_dma`] module"]
#[doc(alias = "R16_UH_RX_DMA")]
pub type R16UhRxDma = crate::Reg<r16_uh_rx_dma::R16UhRxDmaSpec>;
#[doc = "USB host receiving buffer starting address"]
pub mod r16_uh_rx_dma {
#[doc = "Register `R16_UH_RX_DMA` reader"]
pub type R = crate::R<R16UhRxDmaSpec>;
#[doc = "Register `R16_UH_RX_DMA` writer"]
pub type W = crate::W<R16UhRxDmaSpec>;
#[doc = "Field `R16_UH_RX_DMA` reader - USB host receiving endpoint receiving data buffer mode control bit"]
pub type R16UhRxDmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UH_RX_DMA` writer - USB host receiving endpoint receiving data buffer mode control bit"]
pub type R16UhRxDmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - USB host receiving endpoint receiving data buffer mode control bit"]
#[inline(always)]
pub fn r16_uh_rx_dma(&self) -> R16UhRxDmaR {
R16UhRxDmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - USB host receiving endpoint receiving data buffer mode control bit"]
#[inline(always)]
pub fn r16_uh_rx_dma(&mut self) -> R16UhRxDmaW<R16UhRxDmaSpec> {
R16UhRxDmaW::new(self, 0)
}
}
#[doc = "USB host receiving buffer starting address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uh_rx_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uh_rx_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16UhRxDmaSpec;
impl crate::RegisterSpec for R16UhRxDmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uh_rx_dma::R`](R) reader structure"]
impl crate::Readable for R16UhRxDmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uh_rx_dma::W`](W) writer structure"]
impl crate::Writable for R16UhRxDmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UH_RX_DMA to value 0"]
impl crate::Resettable for R16UhRxDmaSpec {}
}
#[doc = "R16_UH_TX_DMA (rw) register accessor: USB host sends buffer starting address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uh_tx_dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uh_tx_dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uh_tx_dma`] module"]
#[doc(alias = "R16_UH_TX_DMA")]
pub type R16UhTxDma = crate::Reg<r16_uh_tx_dma::R16UhTxDmaSpec>;
#[doc = "USB host sends buffer starting address"]
pub mod r16_uh_tx_dma {
#[doc = "Register `R16_UH_TX_DMA` reader"]
pub type R = crate::R<R16UhTxDmaSpec>;
#[doc = "Register `R16_UH_TX_DMA` writer"]
pub type W = crate::W<R16UhTxDmaSpec>;
#[doc = "Field `R16_UH_TX_DMA` reader - Starting address of host endpoint data sending buffer"]
pub type R16UhTxDmaR = crate::FieldReader<u16>;
#[doc = "Field `R16_UH_TX_DMA` writer - Starting address of host endpoint data sending buffer"]
pub type R16UhTxDmaW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Starting address of host endpoint data sending buffer"]
#[inline(always)]
pub fn r16_uh_tx_dma(&self) -> R16UhTxDmaR {
R16UhTxDmaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:15 - Starting address of host endpoint data sending buffer"]
#[inline(always)]
pub fn r16_uh_tx_dma(&mut self) -> R16UhTxDmaW<R16UhTxDmaSpec> {
R16UhTxDmaW::new(self, 0)
}
}
#[doc = "USB host sends buffer starting address\n\nYou can [`read`](crate::Reg::read) this register and get [`r16_uh_tx_dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r16_uh_tx_dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16UhTxDmaSpec;
impl crate::RegisterSpec for R16UhTxDmaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`r16_uh_tx_dma::R`](R) reader structure"]
impl crate::Readable for R16UhTxDmaSpec {}
#[doc = "`write(|w| ..)` method takes [`r16_uh_tx_dma::W`](W) writer structure"]
impl crate::Writable for R16UhTxDmaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R16_UH_TX_DMA to value 0"]
impl crate::Resettable for R16UhTxDmaSpec {}
}
#[doc = "R8_UH_SETUP (rw) register accessor: USB Host Auxiliary Settings Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_setup`] module"]
#[doc(alias = "R8_UH_SETUP")]
pub type R8UhSetup = crate::Reg<r8_uh_setup::R8UhSetupSpec>;
#[doc = "USB Host Auxiliary Settings Register"]
pub mod r8_uh_setup {
#[doc = "Register `R8_UH_SETUP` reader"]
pub type R = crate::R<R8UhSetupSpec>;
#[doc = "Register `R8_UH_SETUP` writer"]
pub type W = crate::W<R8UhSetupSpec>;
#[doc = "Field `RB_UH_SOF_EN` reader - Automatically generate SOF packet enable bit"]
pub type RbUhSofEnR = crate::BitReader;
#[doc = "Field `RB_UH_SOF_EN` writer - Automatically generate SOF packet enable bit"]
pub type RbUhSofEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_PRE_PID_EN` reader - Low speed preamble packet PRE PID enable bit"]
pub type RbUhPrePidEnR = crate::BitReader;
#[doc = "Field `RB_UH_PRE_PID_EN` writer - Low speed preamble packet PRE PID enable bit"]
pub type RbUhPrePidEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 6 - Automatically generate SOF packet enable bit"]
#[inline(always)]
pub fn rb_uh_sof_en(&self) -> RbUhSofEnR {
RbUhSofEnR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Low speed preamble packet PRE PID enable bit"]
#[inline(always)]
pub fn rb_uh_pre_pid_en(&self) -> RbUhPrePidEnR {
RbUhPrePidEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 6 - Automatically generate SOF packet enable bit"]
#[inline(always)]
pub fn rb_uh_sof_en(&mut self) -> RbUhSofEnW<R8UhSetupSpec> {
RbUhSofEnW::new(self, 6)
}
#[doc = "Bit 7 - Low speed preamble packet PRE PID enable bit"]
#[inline(always)]
pub fn rb_uh_pre_pid_en(&mut self) -> RbUhPrePidEnW<R8UhSetupSpec> {
RbUhPrePidEnW::new(self, 7)
}
}
#[doc = "USB Host Auxiliary Settings Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhSetupSpec;
impl crate::RegisterSpec for R8UhSetupSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_setup::R`](R) reader structure"]
impl crate::Readable for R8UhSetupSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_setup::W`](W) writer structure"]
impl crate::Writable for R8UhSetupSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_SETUP to value 0"]
impl crate::Resettable for R8UhSetupSpec {}
}
#[doc = "R8_UH_EP_PID (rw) register accessor: USB host token setting register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_ep_pid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_ep_pid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_ep_pid`] module"]
#[doc(alias = "R8_UH_EP_PID")]
pub type R8UhEpPid = crate::Reg<r8_uh_ep_pid::R8UhEpPidSpec>;
#[doc = "USB host token setting register"]
pub mod r8_uh_ep_pid {
#[doc = "Register `R8_UH_EP_PID` reader"]
pub type R = crate::R<R8UhEpPidSpec>;
#[doc = "Register `R8_UH_EP_PID` writer"]
pub type W = crate::W<R8UhEpPidSpec>;
#[doc = "Field `MASK_UH_ENDP` reader - Set the endpoint number of the target device being operated on this time"]
pub type MaskUhEndpR = crate::FieldReader;
#[doc = "Field `MASK_UH_ENDP` writer - Set the endpoint number of the target device being operated on this time"]
pub type MaskUhEndpW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MASK_UH_TOKEN` reader - Set the token PID packet identifier for this USB transfer transaction"]
pub type MaskUhTokenR = crate::FieldReader;
#[doc = "Field `MASK_UH_TOKEN` writer - Set the token PID packet identifier for this USB transfer transaction"]
pub type MaskUhTokenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Set the endpoint number of the target device being operated on this time"]
#[inline(always)]
pub fn mask_uh_endp(&self) -> MaskUhEndpR {
MaskUhEndpR::new(self.bits & 0x0f)
}
#[doc = "Bits 4:7 - Set the token PID packet identifier for this USB transfer transaction"]
#[inline(always)]
pub fn mask_uh_token(&self) -> MaskUhTokenR {
MaskUhTokenR::new((self.bits >> 4) & 0x0f)
}
}
impl W {
#[doc = "Bits 0:3 - Set the endpoint number of the target device being operated on this time"]
#[inline(always)]
pub fn mask_uh_endp(&mut self) -> MaskUhEndpW<R8UhEpPidSpec> {
MaskUhEndpW::new(self, 0)
}
#[doc = "Bits 4:7 - Set the token PID packet identifier for this USB transfer transaction"]
#[inline(always)]
pub fn mask_uh_token(&mut self) -> MaskUhTokenW<R8UhEpPidSpec> {
MaskUhTokenW::new(self, 4)
}
}
#[doc = "USB host token setting register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_ep_pid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_ep_pid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhEpPidSpec;
impl crate::RegisterSpec for R8UhEpPidSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_ep_pid::R`](R) reader structure"]
impl crate::Readable for R8UhEpPidSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_ep_pid::W`](W) writer structure"]
impl crate::Writable for R8UhEpPidSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_EP_PID to value 0"]
impl crate::Resettable for R8UhEpPidSpec {}
}
#[doc = "R8_UH_RX_CTRL (rw) register accessor: USB host receiving endpoint control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_rx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_rx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_rx_ctrl`] module"]
#[doc(alias = "R8_UH_RX_CTRL")]
pub type R8UhRxCtrl = crate::Reg<r8_uh_rx_ctrl::R8UhRxCtrlSpec>;
#[doc = "USB host receiving endpoint control register"]
pub mod r8_uh_rx_ctrl {
#[doc = "Register `R8_UH_RX_CTRL` reader"]
pub type R = crate::R<R8UhRxCtrlSpec>;
#[doc = "Register `R8_UH_RX_CTRL` writer"]
pub type W = crate::W<R8UhRxCtrlSpec>;
#[doc = "Field `RB_UH_R_RES` reader - Response control bit of host receiver to IN transaction"]
pub type RbUhRResR = crate::BitReader;
#[doc = "Field `RB_UH_R_RES` writer - Response control bit of host receiver to IN transaction"]
pub type RbUhRResW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_R_AUTO_TOG` reader - Synchronization trigger bit, automatic flipping enable control bit"]
pub type RbUhRAutoTogR = crate::BitReader;
#[doc = "Field `RB_UH_R_AUTO_TOG` writer - Synchronization trigger bit, automatic flipping enable control bit"]
pub type RbUhRAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_R_TOG` reader - Expected synchronization trigger bit for USB host receiver (handling IN transactions)"]
pub type RbUhRTogR = crate::BitReader;
#[doc = "Field `RB_UH_R_TOG` writer - Expected synchronization trigger bit for USB host receiver (handling IN transactions)"]
pub type RbUhRTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - Response control bit of host receiver to IN transaction"]
#[inline(always)]
pub fn rb_uh_r_res(&self) -> RbUhRResR {
RbUhRResR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Synchronization trigger bit, automatic flipping enable control bit"]
#[inline(always)]
pub fn rb_uh_r_auto_tog(&self) -> RbUhRAutoTogR {
RbUhRAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7 - Expected synchronization trigger bit for USB host receiver (handling IN transactions)"]
#[inline(always)]
pub fn rb_uh_r_tog(&self) -> RbUhRTogR {
RbUhRTogR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - Response control bit of host receiver to IN transaction"]
#[inline(always)]
pub fn rb_uh_r_res(&mut self) -> RbUhRResW<R8UhRxCtrlSpec> {
RbUhRResW::new(self, 2)
}
#[doc = "Bit 4 - Synchronization trigger bit, automatic flipping enable control bit"]
#[inline(always)]
pub fn rb_uh_r_auto_tog(&mut self) -> RbUhRAutoTogW<R8UhRxCtrlSpec> {
RbUhRAutoTogW::new(self, 4)
}
#[doc = "Bit 7 - Expected synchronization trigger bit for USB host receiver (handling IN transactions)"]
#[inline(always)]
pub fn rb_uh_r_tog(&mut self) -> RbUhRTogW<R8UhRxCtrlSpec> {
RbUhRTogW::new(self, 7)
}
}
#[doc = "USB host receiving endpoint control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_rx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_rx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhRxCtrlSpec;
impl crate::RegisterSpec for R8UhRxCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_rx_ctrl::R`](R) reader structure"]
impl crate::Readable for R8UhRxCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_rx_ctrl::W`](W) writer structure"]
impl crate::Writable for R8UhRxCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_RX_CTRL to value 0"]
impl crate::Resettable for R8UhRxCtrlSpec {}
}
#[doc = "R8_UH_TX_LEN (rw) register accessor: USB host sends length register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_tx_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_tx_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_tx_len`] module"]
#[doc(alias = "R8_UH_TX_LEN")]
pub type R8UhTxLen = crate::Reg<r8_uh_tx_len::R8UhTxLenSpec>;
#[doc = "USB host sends length register"]
pub mod r8_uh_tx_len {
#[doc = "Register `R8_UH_TX_LEN` reader"]
pub type R = crate::R<R8UhTxLenSpec>;
#[doc = "Register `R8_UH_TX_LEN` writer"]
pub type W = crate::W<R8UhTxLenSpec>;
#[doc = "Field `R8_UH_TX_LEN` reader - Set the number of bytes of data to be sent by the USB host sending endpoint"]
pub type R8UhTxLenR = crate::FieldReader;
#[doc = "Field `R8_UH_TX_LEN` writer - Set the number of bytes of data to be sent by the USB host sending endpoint"]
pub type R8UhTxLenW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Set the number of bytes of data to be sent by the USB host sending endpoint"]
#[inline(always)]
pub fn r8_uh_tx_len(&self) -> R8UhTxLenR {
R8UhTxLenR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:7 - Set the number of bytes of data to be sent by the USB host sending endpoint"]
#[inline(always)]
pub fn r8_uh_tx_len(&mut self) -> R8UhTxLenW<R8UhTxLenSpec> {
R8UhTxLenW::new(self, 0)
}
}
#[doc = "USB host sends length register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_tx_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_tx_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhTxLenSpec;
impl crate::RegisterSpec for R8UhTxLenSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_tx_len::R`](R) reader structure"]
impl crate::Readable for R8UhTxLenSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_tx_len::W`](W) writer structure"]
impl crate::Writable for R8UhTxLenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_TX_LEN to value 0"]
impl crate::Resettable for R8UhTxLenSpec {}
}
#[doc = "R8_UH_TX_CTRL (rw) register accessor: USB host sends endpoint control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_tx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_tx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uh_tx_ctrl`] module"]
#[doc(alias = "R8_UH_TX_CTRL")]
pub type R8UhTxCtrl = crate::Reg<r8_uh_tx_ctrl::R8UhTxCtrlSpec>;
#[doc = "USB host sends endpoint control register"]
pub mod r8_uh_tx_ctrl {
#[doc = "Register `R8_UH_TX_CTRL` reader"]
pub type R = crate::R<R8UhTxCtrlSpec>;
#[doc = "Register `R8_UH_TX_CTRL` writer"]
pub type W = crate::W<R8UhTxCtrlSpec>;
#[doc = "Field `RB_UH_T_RES` reader - Response control bit of USB host transmitter to SETUP/OUT transaction"]
pub type RbUhTResR = crate::BitReader;
#[doc = "Field `RB_UH_T_RES` writer - Response control bit of USB host transmitter to SETUP/OUT transaction"]
pub type RbUhTResW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_T_AUTO_TOG` reader - Synchronization trigger bit, automatic flipping enable control bit"]
pub type RbUhTAutoTogR = crate::BitReader;
#[doc = "Field `RB_UH_T_AUTO_TOG` writer - Synchronization trigger bit, automatic flipping enable control bit"]
pub type RbUhTAutoTogW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RB_UH_T_TOG` reader - The synchronization trigger bit prepared by the USB host transmitter (handling SETUP/OUT transactions)"]
pub type RbUhTTogR = crate::BitReader;
#[doc = "Field `RB_UH_T_TOG` writer - The synchronization trigger bit prepared by the USB host transmitter (handling SETUP/OUT transactions)"]
pub type RbUhTTogW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Response control bit of USB host transmitter to SETUP/OUT transaction"]
#[inline(always)]
pub fn rb_uh_t_res(&self) -> RbUhTResR {
RbUhTResR::new((self.bits & 1) != 0)
}
#[doc = "Bit 4 - Synchronization trigger bit, automatic flipping enable control bit"]
#[inline(always)]
pub fn rb_uh_t_auto_tog(&self) -> RbUhTAutoTogR {
RbUhTAutoTogR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - The synchronization trigger bit prepared by the USB host transmitter (handling SETUP/OUT transactions)"]
#[inline(always)]
pub fn rb_uh_t_tog(&self) -> RbUhTTogR {
RbUhTTogR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Response control bit of USB host transmitter to SETUP/OUT transaction"]
#[inline(always)]
pub fn rb_uh_t_res(&mut self) -> RbUhTResW<R8UhTxCtrlSpec> {
RbUhTResW::new(self, 0)
}
#[doc = "Bit 4 - Synchronization trigger bit, automatic flipping enable control bit"]
#[inline(always)]
pub fn rb_uh_t_auto_tog(&mut self) -> RbUhTAutoTogW<R8UhTxCtrlSpec> {
RbUhTAutoTogW::new(self, 4)
}
#[doc = "Bit 6 - The synchronization trigger bit prepared by the USB host transmitter (handling SETUP/OUT transactions)"]
#[inline(always)]
pub fn rb_uh_t_tog(&mut self) -> RbUhTTogW<R8UhTxCtrlSpec> {
RbUhTTogW::new(self, 6)
}
}
#[doc = "USB host sends endpoint control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r8_uh_tx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r8_uh_tx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8UhTxCtrlSpec;
impl crate::RegisterSpec for R8UhTxCtrlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`r8_uh_tx_ctrl::R`](R) reader structure"]
impl crate::Readable for R8UhTxCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`r8_uh_tx_ctrl::W`](W) writer structure"]
impl crate::Writable for R8UhTxCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R8_UH_TX_CTRL to value 0"]
impl crate::Resettable for R8UhTxCtrlSpec {}
}
}
#[doc = "Program Fast Interrupt Controller"]
pub type Pfic = crate::Periph<pfic::RegisterBlock, 0xe000_e000>;
impl core::fmt::Debug for Pfic {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pfic").finish()
}
}
#[doc = "Program Fast Interrupt Controller"]
pub mod pfic {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r32_pfic_isr1: R32PficIsr1,
r32_pfic_isr2: R32PficIsr2,
_reserved2: [u8; 0x18],
r32_pfic_ipr1: R32PficIpr1,
r32_pfic_ipr2: R32PficIpr2,
_reserved4: [u8; 0x18],
r32_pfic_ithresdr: R32PficIthresdr,
_reserved5: [u8; 0x04],
r32_pfic_cfgr: R32PficCfgr,
r32_pfic_gisr: R32PficGisr,
r32_pfic_idcfgr: R32PficIdcfgr,
_reserved8: [u8; 0x0c],
r32_pfic_fiaddrr0: R32PficFiaddrr0,
r32_pfic_fiaddrr1: R32PficFiaddrr1,
r32_pfic_fiaddrr2: R32PficFiaddrr2,
r32_pfic_fiaddrr3: R32PficFiaddrr3,
_reserved12: [u8; 0x90],
r32_pfic_ienr1: R32PficIenr1,
r32_pfic_ienr2: R32PficIenr2,
_reserved14: [u8; 0x78],
r32_pfic_irer1: R32PficIrer1,
r32_pfic_irer2: R32PficIrer2,
_reserved16: [u8; 0x78],
r32_pfic_ipsr1: R32PficIpsr1,
r32_pfic_ipsr2: R32PficIpsr2,
_reserved18: [u8; 0x78],
r32_pfic_iprr1: R32PficIprr1,
r32_pfic_iprr2: R32PficIprr2,
_reserved20: [u8; 0x78],
r32_pfic_iactr1: R32PficIactr1,
r32_pfic_iactr2: R32PficIactr2,
_reserved22: [u8; 0xf8],
r32_pfic_iprior0: R32PficIprior0,
_reserved23: [u8; 0x1c],
r32_pfic_iprior1: R32PficIprior1,
_reserved24: [u8; 0x1c],
r32_pfic_iprior2: R32PficIprior2,
_reserved25: [u8; 0x1c],
r32_pfic_iprior3: R32PficIprior3,
_reserved26: [u8; 0x1c],
r32_pfic_iprior4: R32PficIprior4,
_reserved27: [u8; 0x1c],
r32_pfic_iprior5: R32PficIprior5,
_reserved28: [u8; 0x1c],
r32_pfic_iprior6: R32PficIprior6,
_reserved29: [u8; 0x1c],
r32_pfic_iprior7: R32PficIprior7,
_reserved30: [u8; 0x1c],
r32_pfic_iprior8: R32PficIprior8,
_reserved31: [u8; 0x1c],
r32_pfic_iprior9: R32PficIprior9,
_reserved32: [u8; 0x1c],
r32_pfic_iprior10: R32PficIprior10,
_reserved33: [u8; 0x1c],
r32_pfic_iprior11: R32PficIprior11,
_reserved34: [u8; 0x1c],
r32_pfic_iprior12: R32PficIprior12,
_reserved35: [u8; 0x1c],
r32_pfic_iprior13: R32PficIprior13,
_reserved36: [u8; 0x1c],
r32_pfic_iprior14: R32PficIprior14,
_reserved37: [u8; 0x1c],
r32_pfic_iprior15: R32PficIprior15,
_reserved38: [u8; 0x1c],
r32_pfic_iprior16: R32PficIprior16,
_reserved39: [u8; 0x1c],
r32_pfic_iprior17: R32PficIprior17,
_reserved40: [u8; 0x1c],
r32_pfic_iprior18: R32PficIprior18,
_reserved41: [u8; 0x1c],
r32_pfic_iprior19: R32PficIprior19,
_reserved42: [u8; 0x1c],
r32_pfic_iprior20: R32PficIprior20,
_reserved43: [u8; 0x1c],
r32_pfic_iprior21: R32PficIprior21,
_reserved44: [u8; 0x1c],
r32_pfic_iprior22: R32PficIprior22,
_reserved45: [u8; 0x1c],
r32_pfic_iprior23: R32PficIprior23,
_reserved46: [u8; 0x1c],
r32_pfic_iprior24: R32PficIprior24,
_reserved47: [u8; 0x1c],
r32_pfic_iprior25: R32PficIprior25,
_reserved48: [u8; 0x1c],
r32_pfic_iprior26: R32PficIprior26,
_reserved49: [u8; 0x1c],
r32_pfic_iprior27: R32PficIprior27,
_reserved50: [u8; 0x1c],
r32_pfic_iprior28: R32PficIprior28,
_reserved51: [u8; 0x1c],
r32_pfic_iprior29: R32PficIprior29,
_reserved52: [u8; 0x1c],
r32_pfic_iprior30: R32PficIprior30,
_reserved53: [u8; 0x1c],
r32_pfic_iprior31: R32PficIprior31,
_reserved54: [u8; 0x1c],
r32_pfic_iprior32: R32PficIprior32,
_reserved55: [u8; 0x1c],
r32_pfic_iprior33: R32PficIprior33,
_reserved56: [u8; 0x1c],
r32_pfic_iprior34: R32PficIprior34,
_reserved57: [u8; 0x1c],
r32_pfic_iprior35: R32PficIprior35,
_reserved58: [u8; 0x1c],
r32_pfic_iprior36: R32PficIprior36,
_reserved59: [u8; 0x1c],
r32_pfic_iprior37: R32PficIprior37,
_reserved60: [u8; 0x1c],
r32_pfic_iprior38: R32PficIprior38,
_reserved61: [u8; 0x1c],
r32_pfic_iprior39: R32PficIprior39,
_reserved62: [u8; 0x1c],
r32_pfic_iprior40: R32PficIprior40,
_reserved63: [u8; 0x1c],
r32_pfic_iprior41: R32PficIprior41,
_reserved64: [u8; 0x1c],
r32_pfic_iprior42: R32PficIprior42,
_reserved65: [u8; 0x1c],
r32_pfic_iprior43: R32PficIprior43,
_reserved66: [u8; 0x1c],
r32_pfic_iprior44: R32PficIprior44,
_reserved67: [u8; 0x1c],
r32_pfic_iprior45: R32PficIprior45,
_reserved68: [u8; 0x1c],
r32_pfic_iprior46: R32PficIprior46,
_reserved69: [u8; 0x1c],
r32_pfic_iprior47: R32PficIprior47,
_reserved70: [u8; 0x1c],
r32_pfic_iprior48: R32PficIprior48,
_reserved71: [u8; 0x1c],
r32_pfic_iprior49: R32PficIprior49,
_reserved72: [u8; 0x1c],
r32_pfic_iprior50: R32PficIprior50,
_reserved73: [u8; 0x1c],
r32_pfic_iprior51: R32PficIprior51,
_reserved74: [u8; 0x1c],
r32_pfic_iprior52: R32PficIprior52,
_reserved75: [u8; 0x1c],
r32_pfic_iprior53: R32PficIprior53,
_reserved76: [u8; 0x2c],
r32_pfic_iprior54: R32PficIprior54,
_reserved77: [u8; 0x0c],
r32_pfic_iprior55: R32PficIprior55,
_reserved78: [u8; 0x1c],
r32_pfic_iprior56: R32PficIprior56,
_reserved79: [u8; 0x1c],
r32_pfic_iprior57: R32PficIprior57,
_reserved80: [u8; 0x1c],
r32_pfic_iprior58: R32PficIprior58,
_reserved81: [u8; 0x1c],
r32_pfic_iprior59: R32PficIprior59,
_reserved82: [u8; 0x1c],
r32_pfic_iprior60: R32PficIprior60,
_reserved83: [u8; 0x1c],
r32_pfic_iprior61: R32PficIprior61,
_reserved84: [u8; 0x3c],
r32_pfic_iprior62: R32PficIprior62,
_reserved85: [u8; 0x1c],
r32_pfic_iprior63: R32PficIprior63,
_reserved86: [u8; 0x010c],
r32_pfic_sctlr: R32PficSctlr,
}
impl RegisterBlock {
#[doc = "0x00 - RO,Interrupt Status Register 1"]
#[inline(always)]
pub const fn r32_pfic_isr1(&self) -> &R32PficIsr1 {
&self.r32_pfic_isr1
}
#[doc = "0x04 - RO,Interrupt Status Register 2"]
#[inline(always)]
pub const fn r32_pfic_isr2(&self) -> &R32PficIsr2 {
&self.r32_pfic_isr2
}
#[doc = "0x20 - RO,Interrupt Pending Register 1"]
#[inline(always)]
pub const fn r32_pfic_ipr1(&self) -> &R32PficIpr1 {
&self.r32_pfic_ipr1
}
#[doc = "0x24 - RO,Interrupt Pending Register 2"]
#[inline(always)]
pub const fn r32_pfic_ipr2(&self) -> &R32PficIpr2 {
&self.r32_pfic_ipr2
}
#[doc = "0x40 - RW,Interrupt Priority Register"]
#[inline(always)]
pub const fn r32_pfic_ithresdr(&self) -> &R32PficIthresdr {
&self.r32_pfic_ithresdr
}
#[doc = "0x48 - Interrupt Config Register"]
#[inline(always)]
pub const fn r32_pfic_cfgr(&self) -> &R32PficCfgr {
&self.r32_pfic_cfgr
}
#[doc = "0x4c - Interrupt Global Register"]
#[inline(always)]
pub const fn r32_pfic_gisr(&self) -> &R32PficGisr {
&self.r32_pfic_gisr
}
#[doc = "0x50 - RW,Interrupt Fast ID Config Register"]
#[inline(always)]
pub const fn r32_pfic_idcfgr(&self) -> &R32PficIdcfgr {
&self.r32_pfic_idcfgr
}
#[doc = "0x60 - Interrupt 0 address Register"]
#[inline(always)]
pub const fn r32_pfic_fiaddrr0(&self) -> &R32PficFiaddrr0 {
&self.r32_pfic_fiaddrr0
}
#[doc = "0x64 - Interrupt 1 address Register"]
#[inline(always)]
pub const fn r32_pfic_fiaddrr1(&self) -> &R32PficFiaddrr1 {
&self.r32_pfic_fiaddrr1
}
#[doc = "0x68 - Interrupt 2 address Register"]
#[inline(always)]
pub const fn r32_pfic_fiaddrr2(&self) -> &R32PficFiaddrr2 {
&self.r32_pfic_fiaddrr2
}
#[doc = "0x6c - Interrupt 3 address Register"]
#[inline(always)]
pub const fn r32_pfic_fiaddrr3(&self) -> &R32PficFiaddrr3 {
&self.r32_pfic_fiaddrr3
}
#[doc = "0x100 - Interrupt Setting Register"]
#[inline(always)]
pub const fn r32_pfic_ienr1(&self) -> &R32PficIenr1 {
&self.r32_pfic_ienr1
}
#[doc = "0x104 - Interrupt Setting Register"]
#[inline(always)]
pub const fn r32_pfic_ienr2(&self) -> &R32PficIenr2 {
&self.r32_pfic_ienr2
}
#[doc = "0x180 - Interrupt Clear Register"]
#[inline(always)]
pub const fn r32_pfic_irer1(&self) -> &R32PficIrer1 {
&self.r32_pfic_irer1
}
#[doc = "0x184 - Interrupt Clear Register"]
#[inline(always)]
pub const fn r32_pfic_irer2(&self) -> &R32PficIrer2 {
&self.r32_pfic_irer2
}
#[doc = "0x200 - Interrupt Pending Register"]
#[inline(always)]
pub const fn r32_pfic_ipsr1(&self) -> &R32PficIpsr1 {
&self.r32_pfic_ipsr1
}
#[doc = "0x204 - Interrupt Pending Register"]
#[inline(always)]
pub const fn r32_pfic_ipsr2(&self) -> &R32PficIpsr2 {
&self.r32_pfic_ipsr2
}
#[doc = "0x280 - Interrupt Pending Clear Register"]
#[inline(always)]
pub const fn r32_pfic_iprr1(&self) -> &R32PficIprr1 {
&self.r32_pfic_iprr1
}
#[doc = "0x284 - Interrupt Pending Clear Register"]
#[inline(always)]
pub const fn r32_pfic_iprr2(&self) -> &R32PficIprr2 {
&self.r32_pfic_iprr2
}
#[doc = "0x300 - Interrupt ACTIVE Register"]
#[inline(always)]
pub const fn r32_pfic_iactr1(&self) -> &R32PficIactr1 {
&self.r32_pfic_iactr1
}
#[doc = "0x304 - Interrupt ACTIVE Register"]
#[inline(always)]
pub const fn r32_pfic_iactr2(&self) -> &R32PficIactr2 {
&self.r32_pfic_iactr2
}
#[doc = "0x400 - Interrupt Priority configuration Register 0"]
#[inline(always)]
pub const fn r32_pfic_iprior0(&self) -> &R32PficIprior0 {
&self.r32_pfic_iprior0
}
#[doc = "0x420 - Interrupt Priority configuration Register 1"]
#[inline(always)]
pub const fn r32_pfic_iprior1(&self) -> &R32PficIprior1 {
&self.r32_pfic_iprior1
}
#[doc = "0x440 - Interrupt Priority configuration Register 2"]
#[inline(always)]
pub const fn r32_pfic_iprior2(&self) -> &R32PficIprior2 {
&self.r32_pfic_iprior2
}
#[doc = "0x460 - Interrupt Priority configuration Register 3"]
#[inline(always)]
pub const fn r32_pfic_iprior3(&self) -> &R32PficIprior3 {
&self.r32_pfic_iprior3
}
#[doc = "0x480 - Interrupt Priority configuration Register 4"]
#[inline(always)]
pub const fn r32_pfic_iprior4(&self) -> &R32PficIprior4 {
&self.r32_pfic_iprior4
}
#[doc = "0x4a0 - Interrupt Priority configuration Register 5"]
#[inline(always)]
pub const fn r32_pfic_iprior5(&self) -> &R32PficIprior5 {
&self.r32_pfic_iprior5
}
#[doc = "0x4c0 - Interrupt Priority configuration Register 6"]
#[inline(always)]
pub const fn r32_pfic_iprior6(&self) -> &R32PficIprior6 {
&self.r32_pfic_iprior6
}
#[doc = "0x4e0 - Interrupt Priority configuration Register 7"]
#[inline(always)]
pub const fn r32_pfic_iprior7(&self) -> &R32PficIprior7 {
&self.r32_pfic_iprior7
}
#[doc = "0x500 - Interrupt Priority configuration Register 8"]
#[inline(always)]
pub const fn r32_pfic_iprior8(&self) -> &R32PficIprior8 {
&self.r32_pfic_iprior8
}
#[doc = "0x520 - Interrupt Priority configuration Register 9"]
#[inline(always)]
pub const fn r32_pfic_iprior9(&self) -> &R32PficIprior9 {
&self.r32_pfic_iprior9
}
#[doc = "0x540 - Interrupt Priority configuration Register 10"]
#[inline(always)]
pub const fn r32_pfic_iprior10(&self) -> &R32PficIprior10 {
&self.r32_pfic_iprior10
}
#[doc = "0x560 - Interrupt Priority configuration Register 11"]
#[inline(always)]
pub const fn r32_pfic_iprior11(&self) -> &R32PficIprior11 {
&self.r32_pfic_iprior11
}
#[doc = "0x580 - Interrupt Priority configuration Register 12"]
#[inline(always)]
pub const fn r32_pfic_iprior12(&self) -> &R32PficIprior12 {
&self.r32_pfic_iprior12
}
#[doc = "0x5a0 - Interrupt Priority configuration Register 13"]
#[inline(always)]
pub const fn r32_pfic_iprior13(&self) -> &R32PficIprior13 {
&self.r32_pfic_iprior13
}
#[doc = "0x5c0 - Interrupt Priority configuration Register 14"]
#[inline(always)]
pub const fn r32_pfic_iprior14(&self) -> &R32PficIprior14 {
&self.r32_pfic_iprior14
}
#[doc = "0x5e0 - Interrupt Priority configuration Register 15"]
#[inline(always)]
pub const fn r32_pfic_iprior15(&self) -> &R32PficIprior15 {
&self.r32_pfic_iprior15
}
#[doc = "0x600 - Interrupt Priority configuration Register 16"]
#[inline(always)]
pub const fn r32_pfic_iprior16(&self) -> &R32PficIprior16 {
&self.r32_pfic_iprior16
}
#[doc = "0x620 - Interrupt Priority configuration Register 17"]
#[inline(always)]
pub const fn r32_pfic_iprior17(&self) -> &R32PficIprior17 {
&self.r32_pfic_iprior17
}
#[doc = "0x640 - Interrupt Priority configuration Register 18"]
#[inline(always)]
pub const fn r32_pfic_iprior18(&self) -> &R32PficIprior18 {
&self.r32_pfic_iprior18
}
#[doc = "0x660 - Interrupt Priority configuration Register 19"]
#[inline(always)]
pub const fn r32_pfic_iprior19(&self) -> &R32PficIprior19 {
&self.r32_pfic_iprior19
}
#[doc = "0x680 - Interrupt Priority configuration Register 20"]
#[inline(always)]
pub const fn r32_pfic_iprior20(&self) -> &R32PficIprior20 {
&self.r32_pfic_iprior20
}
#[doc = "0x6a0 - Interrupt Priority configuration Register 21"]
#[inline(always)]
pub const fn r32_pfic_iprior21(&self) -> &R32PficIprior21 {
&self.r32_pfic_iprior21
}
#[doc = "0x6c0 - Interrupt Priority configuration Register 22"]
#[inline(always)]
pub const fn r32_pfic_iprior22(&self) -> &R32PficIprior22 {
&self.r32_pfic_iprior22
}
#[doc = "0x6e0 - Interrupt Priority configuration Register 23"]
#[inline(always)]
pub const fn r32_pfic_iprior23(&self) -> &R32PficIprior23 {
&self.r32_pfic_iprior23
}
#[doc = "0x700 - Interrupt Priority configuration Register 24"]
#[inline(always)]
pub const fn r32_pfic_iprior24(&self) -> &R32PficIprior24 {
&self.r32_pfic_iprior24
}
#[doc = "0x720 - Interrupt Priority configuration Register 25"]
#[inline(always)]
pub const fn r32_pfic_iprior25(&self) -> &R32PficIprior25 {
&self.r32_pfic_iprior25
}
#[doc = "0x740 - Interrupt Priority configuration Register 26"]
#[inline(always)]
pub const fn r32_pfic_iprior26(&self) -> &R32PficIprior26 {
&self.r32_pfic_iprior26
}
#[doc = "0x760 - Interrupt Priority configuration Register 27"]
#[inline(always)]
pub const fn r32_pfic_iprior27(&self) -> &R32PficIprior27 {
&self.r32_pfic_iprior27
}
#[doc = "0x780 - Interrupt Priority configuration Register 28"]
#[inline(always)]
pub const fn r32_pfic_iprior28(&self) -> &R32PficIprior28 {
&self.r32_pfic_iprior28
}
#[doc = "0x7a0 - Interrupt Priority configuration Register 29"]
#[inline(always)]
pub const fn r32_pfic_iprior29(&self) -> &R32PficIprior29 {
&self.r32_pfic_iprior29
}
#[doc = "0x7c0 - Interrupt Priority configuration Register 30"]
#[inline(always)]
pub const fn r32_pfic_iprior30(&self) -> &R32PficIprior30 {
&self.r32_pfic_iprior30
}
#[doc = "0x7e0 - Interrupt Priority configuration Register 31"]
#[inline(always)]
pub const fn r32_pfic_iprior31(&self) -> &R32PficIprior31 {
&self.r32_pfic_iprior31
}
#[doc = "0x800 - Interrupt Priority configuration Register 32"]
#[inline(always)]
pub const fn r32_pfic_iprior32(&self) -> &R32PficIprior32 {
&self.r32_pfic_iprior32
}
#[doc = "0x820 - Interrupt Priority configuration Register 33"]
#[inline(always)]
pub const fn r32_pfic_iprior33(&self) -> &R32PficIprior33 {
&self.r32_pfic_iprior33
}
#[doc = "0x840 - Interrupt Priority configuration Register 34"]
#[inline(always)]
pub const fn r32_pfic_iprior34(&self) -> &R32PficIprior34 {
&self.r32_pfic_iprior34
}
#[doc = "0x860 - Interrupt Priority configuration Register 35"]
#[inline(always)]
pub const fn r32_pfic_iprior35(&self) -> &R32PficIprior35 {
&self.r32_pfic_iprior35
}
#[doc = "0x880 - Interrupt Priority configuration Register 36"]
#[inline(always)]
pub const fn r32_pfic_iprior36(&self) -> &R32PficIprior36 {
&self.r32_pfic_iprior36
}
#[doc = "0x8a0 - Interrupt Priority configuration Register 37"]
#[inline(always)]
pub const fn r32_pfic_iprior37(&self) -> &R32PficIprior37 {
&self.r32_pfic_iprior37
}
#[doc = "0x8c0 - Interrupt Priority configuration Register 38"]
#[inline(always)]
pub const fn r32_pfic_iprior38(&self) -> &R32PficIprior38 {
&self.r32_pfic_iprior38
}
#[doc = "0x8e0 - Interrupt Priority configuration Register 39"]
#[inline(always)]
pub const fn r32_pfic_iprior39(&self) -> &R32PficIprior39 {
&self.r32_pfic_iprior39
}
#[doc = "0x900 - Interrupt Priority configuration Register 40"]
#[inline(always)]
pub const fn r32_pfic_iprior40(&self) -> &R32PficIprior40 {
&self.r32_pfic_iprior40
}
#[doc = "0x920 - Interrupt Priority configuration Register 41"]
#[inline(always)]
pub const fn r32_pfic_iprior41(&self) -> &R32PficIprior41 {
&self.r32_pfic_iprior41
}
#[doc = "0x940 - Interrupt Priority configuration Register 42"]
#[inline(always)]
pub const fn r32_pfic_iprior42(&self) -> &R32PficIprior42 {
&self.r32_pfic_iprior42
}
#[doc = "0x960 - Interrupt Priority configuration Register 43"]
#[inline(always)]
pub const fn r32_pfic_iprior43(&self) -> &R32PficIprior43 {
&self.r32_pfic_iprior43
}
#[doc = "0x980 - Interrupt Priority configuration Register 44"]
#[inline(always)]
pub const fn r32_pfic_iprior44(&self) -> &R32PficIprior44 {
&self.r32_pfic_iprior44
}
#[doc = "0x9a0 - Interrupt Priority configuration Register 45"]
#[inline(always)]
pub const fn r32_pfic_iprior45(&self) -> &R32PficIprior45 {
&self.r32_pfic_iprior45
}
#[doc = "0x9c0 - Interrupt Priority configuration Register 46"]
#[inline(always)]
pub const fn r32_pfic_iprior46(&self) -> &R32PficIprior46 {
&self.r32_pfic_iprior46
}
#[doc = "0x9e0 - Interrupt Priority configuration Register 47"]
#[inline(always)]
pub const fn r32_pfic_iprior47(&self) -> &R32PficIprior47 {
&self.r32_pfic_iprior47
}
#[doc = "0xa00 - Interrupt Priority configuration Register 48"]
#[inline(always)]
pub const fn r32_pfic_iprior48(&self) -> &R32PficIprior48 {
&self.r32_pfic_iprior48
}
#[doc = "0xa20 - Interrupt Priority configuration Register 49"]
#[inline(always)]
pub const fn r32_pfic_iprior49(&self) -> &R32PficIprior49 {
&self.r32_pfic_iprior49
}
#[doc = "0xa40 - Interrupt Priority configuration Register 50"]
#[inline(always)]
pub const fn r32_pfic_iprior50(&self) -> &R32PficIprior50 {
&self.r32_pfic_iprior50
}
#[doc = "0xa60 - Interrupt Priority configuration Register 51"]
#[inline(always)]
pub const fn r32_pfic_iprior51(&self) -> &R32PficIprior51 {
&self.r32_pfic_iprior51
}
#[doc = "0xa80 - Interrupt Priority configuration Register 52"]
#[inline(always)]
pub const fn r32_pfic_iprior52(&self) -> &R32PficIprior52 {
&self.r32_pfic_iprior52
}
#[doc = "0xaa0 - Interrupt Priority configuration Register 53"]
#[inline(always)]
pub const fn r32_pfic_iprior53(&self) -> &R32PficIprior53 {
&self.r32_pfic_iprior53
}
#[doc = "0xad0 - Interrupt Priority configuration Register 54"]
#[inline(always)]
pub const fn r32_pfic_iprior54(&self) -> &R32PficIprior54 {
&self.r32_pfic_iprior54
}
#[doc = "0xae0 - Interrupt Priority configuration Register 55"]
#[inline(always)]
pub const fn r32_pfic_iprior55(&self) -> &R32PficIprior55 {
&self.r32_pfic_iprior55
}
#[doc = "0xb00 - Interrupt Priority configuration Register 56"]
#[inline(always)]
pub const fn r32_pfic_iprior56(&self) -> &R32PficIprior56 {
&self.r32_pfic_iprior56
}
#[doc = "0xb20 - Interrupt Priority configuration Register 57"]
#[inline(always)]
pub const fn r32_pfic_iprior57(&self) -> &R32PficIprior57 {
&self.r32_pfic_iprior57
}
#[doc = "0xb40 - Interrupt Priority configuration Register 58"]
#[inline(always)]
pub const fn r32_pfic_iprior58(&self) -> &R32PficIprior58 {
&self.r32_pfic_iprior58
}
#[doc = "0xb60 - Interrupt Priority configuration Register 59"]
#[inline(always)]
pub const fn r32_pfic_iprior59(&self) -> &R32PficIprior59 {
&self.r32_pfic_iprior59
}
#[doc = "0xb80 - Interrupt Priority configuration Register 60"]
#[inline(always)]
pub const fn r32_pfic_iprior60(&self) -> &R32PficIprior60 {
&self.r32_pfic_iprior60
}
#[doc = "0xba0 - Interrupt Priority configuration Register 61"]
#[inline(always)]
pub const fn r32_pfic_iprior61(&self) -> &R32PficIprior61 {
&self.r32_pfic_iprior61
}
#[doc = "0xbe0 - Interrupt Priority configuration Register 62"]
#[inline(always)]
pub const fn r32_pfic_iprior62(&self) -> &R32PficIprior62 {
&self.r32_pfic_iprior62
}
#[doc = "0xc00 - Interrupt Priority configuration Register 63"]
#[inline(always)]
pub const fn r32_pfic_iprior63(&self) -> &R32PficIprior63 {
&self.r32_pfic_iprior63
}
#[doc = "0xd10 - System Control Register"]
#[inline(always)]
pub const fn r32_pfic_sctlr(&self) -> &R32PficSctlr {
&self.r32_pfic_sctlr
}
}
#[doc = "R32_PFIC_ISR1 (r) register accessor: RO,Interrupt Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_isr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_isr1`] module"]
#[doc(alias = "R32_PFIC_ISR1")]
pub type R32PficIsr1 = crate::Reg<r32_pfic_isr1::R32PficIsr1Spec>;
#[doc = "RO,Interrupt Status Register 1"]
pub mod r32_pfic_isr1 {
#[doc = "Register `R32_PFIC_ISR1` reader"]
pub type R = crate::R<R32PficIsr1Spec>;
#[doc = "Field `INTENSTA` reader - Interrupt ID Status"]
pub type IntenstaR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 12:31 - Interrupt ID Status"]
#[inline(always)]
pub fn intensta(&self) -> IntenstaR {
IntenstaR::new((self.bits >> 12) & 0x000f_ffff)
}
}
#[doc = "RO,Interrupt Status Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_isr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIsr1Spec;
impl crate::RegisterSpec for R32PficIsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_isr1::R`](R) reader structure"]
impl crate::Readable for R32PficIsr1Spec {}
#[doc = "`reset()` method sets R32_PFIC_ISR1 to value 0x0c"]
impl crate::Resettable for R32PficIsr1Spec {
const RESET_VALUE: u32 = 0x0c;
}
}
#[doc = "R32_PFIC_ISR2 (r) register accessor: RO,Interrupt Status Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_isr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_isr2`] module"]
#[doc(alias = "R32_PFIC_ISR2")]
pub type R32PficIsr2 = crate::Reg<r32_pfic_isr2::R32PficIsr2Spec>;
#[doc = "RO,Interrupt Status Register 2"]
pub mod r32_pfic_isr2 {
#[doc = "Register `R32_PFIC_ISR2` reader"]
pub type R = crate::R<R32PficIsr2Spec>;
#[doc = "Field `INTENSTA` reader - Interrupt ID Status"]
pub type IntenstaR = crate::FieldReader;
impl R {
#[doc = "Bits 0:3 - Interrupt ID Status"]
#[inline(always)]
pub fn intensta(&self) -> IntenstaR {
IntenstaR::new((self.bits & 0x0f) as u8)
}
}
#[doc = "RO,Interrupt Status Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_isr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIsr2Spec;
impl crate::RegisterSpec for R32PficIsr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_isr2::R`](R) reader structure"]
impl crate::Readable for R32PficIsr2Spec {}
#[doc = "`reset()` method sets R32_PFIC_ISR2 to value 0"]
impl crate::Resettable for R32PficIsr2Spec {}
}
#[doc = "R32_PFIC_IPR1 (r) register accessor: RO,Interrupt Pending Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ipr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ipr1`] module"]
#[doc(alias = "R32_PFIC_IPR1")]
pub type R32PficIpr1 = crate::Reg<r32_pfic_ipr1::R32PficIpr1Spec>;
#[doc = "RO,Interrupt Pending Register 1"]
pub mod r32_pfic_ipr1 {
#[doc = "Register `R32_PFIC_IPR1` reader"]
pub type R = crate::R<R32PficIpr1Spec>;
#[doc = "Field `PENDSTA` reader - PENDSTA"]
pub type PendstaR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 12:31 - PENDSTA"]
#[inline(always)]
pub fn pendsta(&self) -> PendstaR {
PendstaR::new((self.bits >> 12) & 0x000f_ffff)
}
}
#[doc = "RO,Interrupt Pending Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ipr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIpr1Spec;
impl crate::RegisterSpec for R32PficIpr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_ipr1::R`](R) reader structure"]
impl crate::Readable for R32PficIpr1Spec {}
#[doc = "`reset()` method sets R32_PFIC_IPR1 to value 0"]
impl crate::Resettable for R32PficIpr1Spec {}
}
#[doc = "R32_PFIC_IPR2 (r) register accessor: RO,Interrupt Pending Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ipr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ipr2`] module"]
#[doc(alias = "R32_PFIC_IPR2")]
pub type R32PficIpr2 = crate::Reg<r32_pfic_ipr2::R32PficIpr2Spec>;
#[doc = "RO,Interrupt Pending Register 2"]
pub mod r32_pfic_ipr2 {
#[doc = "Register `R32_PFIC_IPR2` reader"]
pub type R = crate::R<R32PficIpr2Spec>;
#[doc = "Field `PENDSTA` reader - PENDSTA"]
pub type PendstaR = crate::FieldReader;
impl R {
#[doc = "Bits 0:3 - PENDSTA"]
#[inline(always)]
pub fn pendsta(&self) -> PendstaR {
PendstaR::new((self.bits & 0x0f) as u8)
}
}
#[doc = "RO,Interrupt Pending Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ipr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIpr2Spec;
impl crate::RegisterSpec for R32PficIpr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_ipr2::R`](R) reader structure"]
impl crate::Readable for R32PficIpr2Spec {}
#[doc = "`reset()` method sets R32_PFIC_IPR2 to value 0"]
impl crate::Resettable for R32PficIpr2Spec {}
}
#[doc = "R32_PFIC_ITHRESDR (rw) register accessor: RW,Interrupt Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ithresdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ithresdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ithresdr`] module"]
#[doc(alias = "R32_PFIC_ITHRESDR")]
pub type R32PficIthresdr = crate::Reg<r32_pfic_ithresdr::R32PficIthresdrSpec>;
#[doc = "RW,Interrupt Priority Register"]
pub mod r32_pfic_ithresdr {
#[doc = "Register `R32_PFIC_ITHRESDR` reader"]
pub type R = crate::R<R32PficIthresdrSpec>;
#[doc = "Register `R32_PFIC_ITHRESDR` writer"]
pub type W = crate::W<R32PficIthresdrSpec>;
#[doc = "Field `THRESHOLD` reader - RW,THRESHOLD"]
pub type ThresholdR = crate::FieldReader;
#[doc = "Field `THRESHOLD` writer - RW,THRESHOLD"]
pub type ThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW,THRESHOLD"]
#[inline(always)]
pub fn threshold(&self) -> ThresholdR {
ThresholdR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - RW,THRESHOLD"]
#[inline(always)]
pub fn threshold(&mut self) -> ThresholdW<R32PficIthresdrSpec> {
ThresholdW::new(self, 0)
}
}
#[doc = "RW,Interrupt Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_ithresdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ithresdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIthresdrSpec;
impl crate::RegisterSpec for R32PficIthresdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_ithresdr::R`](R) reader structure"]
impl crate::Readable for R32PficIthresdrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_ithresdr::W`](W) writer structure"]
impl crate::Writable for R32PficIthresdrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_ITHRESDR to value 0"]
impl crate::Resettable for R32PficIthresdrSpec {}
}
#[doc = "R32_PFIC_CFGR (w) register accessor: Interrupt Config Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_cfgr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_cfgr`] module"]
#[doc(alias = "R32_PFIC_CFGR")]
pub type R32PficCfgr = crate::Reg<r32_pfic_cfgr::R32PficCfgrSpec>;
#[doc = "Interrupt Config Register"]
pub mod r32_pfic_cfgr {
#[doc = "Register `R32_PFIC_CFGR` writer"]
pub type W = crate::W<R32PficCfgrSpec>;
#[doc = "Field `RESETSYS` writer - WO,RESETSYS"]
pub type ResetsysW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `KEYCODE` writer - WO,KEYCODE"]
pub type KeycodeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl W {
#[doc = "Bit 7 - WO,RESETSYS"]
#[inline(always)]
pub fn resetsys(&mut self) -> ResetsysW<R32PficCfgrSpec> {
ResetsysW::new(self, 7)
}
#[doc = "Bits 16:31 - WO,KEYCODE"]
#[inline(always)]
pub fn keycode(&mut self) -> KeycodeW<R32PficCfgrSpec> {
KeycodeW::new(self, 16)
}
}
#[doc = "Interrupt Config Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_cfgr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficCfgrSpec;
impl crate::RegisterSpec for R32PficCfgrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_cfgr::W`](W) writer structure"]
impl crate::Writable for R32PficCfgrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_CFGR to value 0"]
impl crate::Resettable for R32PficCfgrSpec {}
}
#[doc = "R32_PFIC_GISR (r) register accessor: Interrupt Global Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_gisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_gisr`] module"]
#[doc(alias = "R32_PFIC_GISR")]
pub type R32PficGisr = crate::Reg<r32_pfic_gisr::R32PficGisrSpec>;
#[doc = "Interrupt Global Register"]
pub mod r32_pfic_gisr {
#[doc = "Register `R32_PFIC_GISR` reader"]
pub type R = crate::R<R32PficGisrSpec>;
#[doc = "Field `NESTSTA` reader - RO,NESTSTA"]
pub type NeststaR = crate::FieldReader;
#[doc = "Field `GACTSTA` reader - RO,GACTSTA"]
pub type GactstaR = crate::BitReader;
#[doc = "Field `GPENDSTA` reader - RO,GPENDSTA"]
pub type GpendstaR = crate::BitReader;
impl R {
#[doc = "Bits 0:7 - RO,NESTSTA"]
#[inline(always)]
pub fn neststa(&self) -> NeststaR {
NeststaR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - RO,GACTSTA"]
#[inline(always)]
pub fn gactsta(&self) -> GactstaR {
GactstaR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - RO,GPENDSTA"]
#[inline(always)]
pub fn gpendsta(&self) -> GpendstaR {
GpendstaR::new(((self.bits >> 9) & 1) != 0)
}
}
#[doc = "Interrupt Global Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_gisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficGisrSpec;
impl crate::RegisterSpec for R32PficGisrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_gisr::R`](R) reader structure"]
impl crate::Readable for R32PficGisrSpec {}
#[doc = "`reset()` method sets R32_PFIC_GISR to value 0"]
impl crate::Resettable for R32PficGisrSpec {}
}
#[doc = "R32_PFIC_IDCFGR (rw) register accessor: RW,Interrupt Fast ID Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_idcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_idcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_idcfgr`] module"]
#[doc(alias = "R32_PFIC_IDCFGR")]
pub type R32PficIdcfgr = crate::Reg<r32_pfic_idcfgr::R32PficIdcfgrSpec>;
#[doc = "RW,Interrupt Fast ID Config Register"]
pub mod r32_pfic_idcfgr {
#[doc = "Register `R32_PFIC_IDCFGR` reader"]
pub type R = crate::R<R32PficIdcfgrSpec>;
#[doc = "Register `R32_PFIC_IDCFGR` writer"]
pub type W = crate::W<R32PficIdcfgrSpec>;
#[doc = "Field `FIID0` reader - RW,FIID0"]
pub type Fiid0R = crate::FieldReader;
#[doc = "Field `FIID0` writer - RW,FIID0"]
pub type Fiid0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `FIID1` reader - RW,FIID1"]
pub type Fiid1R = crate::FieldReader;
#[doc = "Field `FIID1` writer - RW,FIID1"]
pub type Fiid1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `FIID2` reader - RW,FIID2"]
pub type Fiid2R = crate::FieldReader;
#[doc = "Field `FIID2` writer - RW,FIID2"]
pub type Fiid2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `FIID3` reader - RW,FIID3"]
pub type Fiid3R = crate::FieldReader;
#[doc = "Field `FIID3` writer - RW,FIID3"]
pub type Fiid3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RW,FIID0"]
#[inline(always)]
pub fn fiid0(&self) -> Fiid0R {
Fiid0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - RW,FIID1"]
#[inline(always)]
pub fn fiid1(&self) -> Fiid1R {
Fiid1R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - RW,FIID2"]
#[inline(always)]
pub fn fiid2(&self) -> Fiid2R {
Fiid2R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - RW,FIID3"]
#[inline(always)]
pub fn fiid3(&self) -> Fiid3R {
Fiid3R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - RW,FIID0"]
#[inline(always)]
pub fn fiid0(&mut self) -> Fiid0W<R32PficIdcfgrSpec> {
Fiid0W::new(self, 0)
}
#[doc = "Bits 8:15 - RW,FIID1"]
#[inline(always)]
pub fn fiid1(&mut self) -> Fiid1W<R32PficIdcfgrSpec> {
Fiid1W::new(self, 8)
}
#[doc = "Bits 16:23 - RW,FIID2"]
#[inline(always)]
pub fn fiid2(&mut self) -> Fiid2W<R32PficIdcfgrSpec> {
Fiid2W::new(self, 16)
}
#[doc = "Bits 24:31 - RW,FIID3"]
#[inline(always)]
pub fn fiid3(&mut self) -> Fiid3W<R32PficIdcfgrSpec> {
Fiid3W::new(self, 24)
}
}
#[doc = "RW,Interrupt Fast ID Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_idcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_idcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIdcfgrSpec;
impl crate::RegisterSpec for R32PficIdcfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_idcfgr::R`](R) reader structure"]
impl crate::Readable for R32PficIdcfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_idcfgr::W`](W) writer structure"]
impl crate::Writable for R32PficIdcfgrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IDCFGR to value 0"]
impl crate::Resettable for R32PficIdcfgrSpec {}
}
#[doc = "R32_PFIC_FIADDRR0 (rw) register accessor: Interrupt 0 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_fiaddrr0`] module"]
#[doc(alias = "R32_PFIC_FIADDRR0")]
pub type R32PficFiaddrr0 = crate::Reg<r32_pfic_fiaddrr0::R32PficFiaddrr0Spec>;
#[doc = "Interrupt 0 address Register"]
pub mod r32_pfic_fiaddrr0 {
#[doc = "Register `R32_PFIC_FIADDRR0` reader"]
pub type R = crate::R<R32PficFiaddrr0Spec>;
#[doc = "Register `R32_PFIC_FIADDRR0` writer"]
pub type W = crate::W<R32PficFiaddrr0Spec>;
#[doc = "Field `FI0EN` reader - RW,Fast interrupt channel 0 enable bit"]
pub type Fi0enR = crate::BitReader;
#[doc = "Field `FI0EN` writer - RW,Fast interrupt channel 0 enable bit"]
pub type Fi0enW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADDR0` reader - RW,ADDR0"]
pub type Addr0R = crate::FieldReader<u32>;
#[doc = "Field `ADDR0` writer - RW,ADDR0"]
pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - RW,Fast interrupt channel 0 enable bit"]
#[inline(always)]
pub fn fi0en(&self) -> Fi0enR {
Fi0enR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31 - RW,ADDR0"]
#[inline(always)]
pub fn addr0(&self) -> Addr0R {
Addr0R::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RW,Fast interrupt channel 0 enable bit"]
#[inline(always)]
pub fn fi0en(&mut self) -> Fi0enW<R32PficFiaddrr0Spec> {
Fi0enW::new(self, 0)
}
#[doc = "Bits 1:31 - RW,ADDR0"]
#[inline(always)]
pub fn addr0(&mut self) -> Addr0W<R32PficFiaddrr0Spec> {
Addr0W::new(self, 1)
}
}
#[doc = "Interrupt 0 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficFiaddrr0Spec;
impl crate::RegisterSpec for R32PficFiaddrr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_fiaddrr0::R`](R) reader structure"]
impl crate::Readable for R32PficFiaddrr0Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_fiaddrr0::W`](W) writer structure"]
impl crate::Writable for R32PficFiaddrr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_FIADDRR0 to value 0"]
impl crate::Resettable for R32PficFiaddrr0Spec {}
}
#[doc = "R32_PFIC_FIADDRR1 (rw) register accessor: Interrupt 1 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_fiaddrr1`] module"]
#[doc(alias = "R32_PFIC_FIADDRR1")]
pub type R32PficFiaddrr1 = crate::Reg<r32_pfic_fiaddrr1::R32PficFiaddrr1Spec>;
#[doc = "Interrupt 1 address Register"]
pub mod r32_pfic_fiaddrr1 {
#[doc = "Register `R32_PFIC_FIADDRR1` reader"]
pub type R = crate::R<R32PficFiaddrr1Spec>;
#[doc = "Register `R32_PFIC_FIADDRR1` writer"]
pub type W = crate::W<R32PficFiaddrr1Spec>;
#[doc = "Field `FI1EN` reader - RW,Fast interrupt channel 1 enable bit"]
pub type Fi1enR = crate::BitReader;
#[doc = "Field `FI1EN` writer - RW,Fast interrupt channel 1 enable bit"]
pub type Fi1enW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADDR1` reader - RW,ADDR1"]
pub type Addr1R = crate::FieldReader<u32>;
#[doc = "Field `ADDR1` writer - RW,ADDR1"]
pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - RW,Fast interrupt channel 1 enable bit"]
#[inline(always)]
pub fn fi1en(&self) -> Fi1enR {
Fi1enR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31 - RW,ADDR1"]
#[inline(always)]
pub fn addr1(&self) -> Addr1R {
Addr1R::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RW,Fast interrupt channel 1 enable bit"]
#[inline(always)]
pub fn fi1en(&mut self) -> Fi1enW<R32PficFiaddrr1Spec> {
Fi1enW::new(self, 0)
}
#[doc = "Bits 1:31 - RW,ADDR1"]
#[inline(always)]
pub fn addr1(&mut self) -> Addr1W<R32PficFiaddrr1Spec> {
Addr1W::new(self, 1)
}
}
#[doc = "Interrupt 1 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficFiaddrr1Spec;
impl crate::RegisterSpec for R32PficFiaddrr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_fiaddrr1::R`](R) reader structure"]
impl crate::Readable for R32PficFiaddrr1Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_fiaddrr1::W`](W) writer structure"]
impl crate::Writable for R32PficFiaddrr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_FIADDRR1 to value 0"]
impl crate::Resettable for R32PficFiaddrr1Spec {}
}
#[doc = "R32_PFIC_FIADDRR2 (rw) register accessor: Interrupt 2 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_fiaddrr2`] module"]
#[doc(alias = "R32_PFIC_FIADDRR2")]
pub type R32PficFiaddrr2 = crate::Reg<r32_pfic_fiaddrr2::R32PficFiaddrr2Spec>;
#[doc = "Interrupt 2 address Register"]
pub mod r32_pfic_fiaddrr2 {
#[doc = "Register `R32_PFIC_FIADDRR2` reader"]
pub type R = crate::R<R32PficFiaddrr2Spec>;
#[doc = "Register `R32_PFIC_FIADDRR2` writer"]
pub type W = crate::W<R32PficFiaddrr2Spec>;
#[doc = "Field `FI2EN` reader - RW,Fast interrupt channel 2 enable bit"]
pub type Fi2enR = crate::BitReader;
#[doc = "Field `FI2EN` writer - RW,Fast interrupt channel 2 enable bit"]
pub type Fi2enW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADDR2` reader - RW,ADDR2"]
pub type Addr2R = crate::FieldReader<u32>;
#[doc = "Field `ADDR2` writer - RW,ADDR2"]
pub type Addr2W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - RW,Fast interrupt channel 2 enable bit"]
#[inline(always)]
pub fn fi2en(&self) -> Fi2enR {
Fi2enR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31 - RW,ADDR2"]
#[inline(always)]
pub fn addr2(&self) -> Addr2R {
Addr2R::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RW,Fast interrupt channel 2 enable bit"]
#[inline(always)]
pub fn fi2en(&mut self) -> Fi2enW<R32PficFiaddrr2Spec> {
Fi2enW::new(self, 0)
}
#[doc = "Bits 1:31 - RW,ADDR2"]
#[inline(always)]
pub fn addr2(&mut self) -> Addr2W<R32PficFiaddrr2Spec> {
Addr2W::new(self, 1)
}
}
#[doc = "Interrupt 2 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficFiaddrr2Spec;
impl crate::RegisterSpec for R32PficFiaddrr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_fiaddrr2::R`](R) reader structure"]
impl crate::Readable for R32PficFiaddrr2Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_fiaddrr2::W`](W) writer structure"]
impl crate::Writable for R32PficFiaddrr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_FIADDRR2 to value 0"]
impl crate::Resettable for R32PficFiaddrr2Spec {}
}
#[doc = "R32_PFIC_FIADDRR3 (rw) register accessor: Interrupt 3 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_fiaddrr3`] module"]
#[doc(alias = "R32_PFIC_FIADDRR3")]
pub type R32PficFiaddrr3 = crate::Reg<r32_pfic_fiaddrr3::R32PficFiaddrr3Spec>;
#[doc = "Interrupt 3 address Register"]
pub mod r32_pfic_fiaddrr3 {
#[doc = "Register `R32_PFIC_FIADDRR3` reader"]
pub type R = crate::R<R32PficFiaddrr3Spec>;
#[doc = "Register `R32_PFIC_FIADDRR3` writer"]
pub type W = crate::W<R32PficFiaddrr3Spec>;
#[doc = "Field `FI3EN` reader - RW,Fast interrupt channel 3 enable bit"]
pub type Fi3enR = crate::BitReader;
#[doc = "Field `FI3EN` writer - RW,Fast interrupt channel 3 enable bit"]
pub type Fi3enW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADDR3` reader - RW,ADDR3"]
pub type Addr3R = crate::FieldReader<u32>;
#[doc = "Field `ADDR3` writer - RW,ADDR3"]
pub type Addr3W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - RW,Fast interrupt channel 3 enable bit"]
#[inline(always)]
pub fn fi3en(&self) -> Fi3enR {
Fi3enR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31 - RW,ADDR3"]
#[inline(always)]
pub fn addr3(&self) -> Addr3R {
Addr3R::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RW,Fast interrupt channel 3 enable bit"]
#[inline(always)]
pub fn fi3en(&mut self) -> Fi3enW<R32PficFiaddrr3Spec> {
Fi3enW::new(self, 0)
}
#[doc = "Bits 1:31 - RW,ADDR3"]
#[inline(always)]
pub fn addr3(&mut self) -> Addr3W<R32PficFiaddrr3Spec> {
Addr3W::new(self, 1)
}
}
#[doc = "Interrupt 3 address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_fiaddrr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_fiaddrr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficFiaddrr3Spec;
impl crate::RegisterSpec for R32PficFiaddrr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_fiaddrr3::R`](R) reader structure"]
impl crate::Readable for R32PficFiaddrr3Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_fiaddrr3::W`](W) writer structure"]
impl crate::Writable for R32PficFiaddrr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_FIADDRR3 to value 0"]
impl crate::Resettable for R32PficFiaddrr3Spec {}
}
#[doc = "R32_PFIC_IENR1 (w) register accessor: Interrupt Setting Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ienr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ienr1`] module"]
#[doc(alias = "R32_PFIC_IENR1")]
pub type R32PficIenr1 = crate::Reg<r32_pfic_ienr1::R32PficIenr1Spec>;
#[doc = "Interrupt Setting Register"]
pub mod r32_pfic_ienr1 {
#[doc = "Register `R32_PFIC_IENR1` writer"]
pub type W = crate::W<R32PficIenr1Spec>;
#[doc = "Field `INTEN` writer - RW1,INTEN"]
pub type IntenW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl W {
#[doc = "Bits 12:31 - RW1,INTEN"]
#[inline(always)]
pub fn inten(&mut self) -> IntenW<R32PficIenr1Spec> {
IntenW::new(self, 12)
}
}
#[doc = "Interrupt Setting Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ienr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIenr1Spec;
impl crate::RegisterSpec for R32PficIenr1Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_ienr1::W`](W) writer structure"]
impl crate::Writable for R32PficIenr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IENR1 to value 0"]
impl crate::Resettable for R32PficIenr1Spec {}
}
#[doc = "R32_PFIC_IENR2 (w) register accessor: Interrupt Setting Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ienr2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ienr2`] module"]
#[doc(alias = "R32_PFIC_IENR2")]
pub type R32PficIenr2 = crate::Reg<r32_pfic_ienr2::R32PficIenr2Spec>;
#[doc = "Interrupt Setting Register"]
pub mod r32_pfic_ienr2 {
#[doc = "Register `R32_PFIC_IENR2` writer"]
pub type W = crate::W<R32PficIenr2Spec>;
#[doc = "Field `INTEN` writer - RW1,INTEN"]
pub type IntenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl W {
#[doc = "Bits 0:3 - RW1,INTEN"]
#[inline(always)]
pub fn inten(&mut self) -> IntenW<R32PficIenr2Spec> {
IntenW::new(self, 0)
}
}
#[doc = "Interrupt Setting Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ienr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIenr2Spec;
impl crate::RegisterSpec for R32PficIenr2Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_ienr2::W`](W) writer structure"]
impl crate::Writable for R32PficIenr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IENR2 to value 0"]
impl crate::Resettable for R32PficIenr2Spec {}
}
#[doc = "R32_PFIC_IRER1 (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_irer1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_irer1`] module"]
#[doc(alias = "R32_PFIC_IRER1")]
pub type R32PficIrer1 = crate::Reg<r32_pfic_irer1::R32PficIrer1Spec>;
#[doc = "Interrupt Clear Register"]
pub mod r32_pfic_irer1 {
#[doc = "Register `R32_PFIC_IRER1` writer"]
pub type W = crate::W<R32PficIrer1Spec>;
#[doc = "Field `INTRESET` writer - RW1,INTRESET"]
pub type IntresetW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl W {
#[doc = "Bits 12:31 - RW1,INTRESET"]
#[inline(always)]
pub fn intreset(&mut self) -> IntresetW<R32PficIrer1Spec> {
IntresetW::new(self, 12)
}
}
#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_irer1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIrer1Spec;
impl crate::RegisterSpec for R32PficIrer1Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_irer1::W`](W) writer structure"]
impl crate::Writable for R32PficIrer1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IRER1 to value 0"]
impl crate::Resettable for R32PficIrer1Spec {}
}
#[doc = "R32_PFIC_IRER2 (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_irer2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_irer2`] module"]
#[doc(alias = "R32_PFIC_IRER2")]
pub type R32PficIrer2 = crate::Reg<r32_pfic_irer2::R32PficIrer2Spec>;
#[doc = "Interrupt Clear Register"]
pub mod r32_pfic_irer2 {
#[doc = "Register `R32_PFIC_IRER2` writer"]
pub type W = crate::W<R32PficIrer2Spec>;
#[doc = "Field `INTRESET` writer - RW1,INTRESET"]
pub type IntresetW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl W {
#[doc = "Bits 0:3 - RW1,INTRESET"]
#[inline(always)]
pub fn intreset(&mut self) -> IntresetW<R32PficIrer2Spec> {
IntresetW::new(self, 0)
}
}
#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_irer2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIrer2Spec;
impl crate::RegisterSpec for R32PficIrer2Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_irer2::W`](W) writer structure"]
impl crate::Writable for R32PficIrer2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IRER2 to value 0"]
impl crate::Resettable for R32PficIrer2Spec {}
}
#[doc = "R32_PFIC_IPSR1 (w) register accessor: Interrupt Pending Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ipsr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ipsr1`] module"]
#[doc(alias = "R32_PFIC_IPSR1")]
pub type R32PficIpsr1 = crate::Reg<r32_pfic_ipsr1::R32PficIpsr1Spec>;
#[doc = "Interrupt Pending Register"]
pub mod r32_pfic_ipsr1 {
#[doc = "Register `R32_PFIC_IPSR1` writer"]
pub type W = crate::W<R32PficIpsr1Spec>;
#[doc = "Field `PENDSET` writer - RW1,PENDSET"]
pub type PendsetW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl W {
#[doc = "Bits 12:31 - RW1,PENDSET"]
#[inline(always)]
pub fn pendset(&mut self) -> PendsetW<R32PficIpsr1Spec> {
PendsetW::new(self, 12)
}
}
#[doc = "Interrupt Pending Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ipsr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIpsr1Spec;
impl crate::RegisterSpec for R32PficIpsr1Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_ipsr1::W`](W) writer structure"]
impl crate::Writable for R32PficIpsr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPSR1 to value 0"]
impl crate::Resettable for R32PficIpsr1Spec {}
}
#[doc = "R32_PFIC_IPSR2 (w) register accessor: Interrupt Pending Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ipsr2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_ipsr2`] module"]
#[doc(alias = "R32_PFIC_IPSR2")]
pub type R32PficIpsr2 = crate::Reg<r32_pfic_ipsr2::R32PficIpsr2Spec>;
#[doc = "Interrupt Pending Register"]
pub mod r32_pfic_ipsr2 {
#[doc = "Register `R32_PFIC_IPSR2` writer"]
pub type W = crate::W<R32PficIpsr2Spec>;
#[doc = "Field `PENDSET` writer - RW1,PENDSET"]
pub type PendsetW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl W {
#[doc = "Bits 0:3 - RW1,PENDSET"]
#[inline(always)]
pub fn pendset(&mut self) -> PendsetW<R32PficIpsr2Spec> {
PendsetW::new(self, 0)
}
}
#[doc = "Interrupt Pending Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_ipsr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIpsr2Spec;
impl crate::RegisterSpec for R32PficIpsr2Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_ipsr2::W`](W) writer structure"]
impl crate::Writable for R32PficIpsr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPSR2 to value 0"]
impl crate::Resettable for R32PficIpsr2Spec {}
}
#[doc = "R32_PFIC_IPRR1 (w) register accessor: Interrupt Pending Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprr1`] module"]
#[doc(alias = "R32_PFIC_IPRR1")]
pub type R32PficIprr1 = crate::Reg<r32_pfic_iprr1::R32PficIprr1Spec>;
#[doc = "Interrupt Pending Clear Register"]
pub mod r32_pfic_iprr1 {
#[doc = "Register `R32_PFIC_IPRR1` writer"]
pub type W = crate::W<R32PficIprr1Spec>;
#[doc = "Field `PENDRESET` writer - RW1,PENDRESET"]
pub type PendresetW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl W {
#[doc = "Bits 12:31 - RW1,PENDRESET"]
#[inline(always)]
pub fn pendreset(&mut self) -> PendresetW<R32PficIprr1Spec> {
PendresetW::new(self, 12)
}
}
#[doc = "Interrupt Pending Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprr1Spec;
impl crate::RegisterSpec for R32PficIprr1Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprr1::W`](W) writer structure"]
impl crate::Writable for R32PficIprr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRR1 to value 0"]
impl crate::Resettable for R32PficIprr1Spec {}
}
#[doc = "R32_PFIC_IPRR2 (w) register accessor: Interrupt Pending Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprr2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprr2`] module"]
#[doc(alias = "R32_PFIC_IPRR2")]
pub type R32PficIprr2 = crate::Reg<r32_pfic_iprr2::R32PficIprr2Spec>;
#[doc = "Interrupt Pending Clear Register"]
pub mod r32_pfic_iprr2 {
#[doc = "Register `R32_PFIC_IPRR2` writer"]
pub type W = crate::W<R32PficIprr2Spec>;
#[doc = "Field `PENDRESET` writer - RW1,PENDRESET"]
pub type PendresetW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl W {
#[doc = "Bits 0:3 - RW1,PENDRESET"]
#[inline(always)]
pub fn pendreset(&mut self) -> PendresetW<R32PficIprr2Spec> {
PendresetW::new(self, 0)
}
}
#[doc = "Interrupt Pending Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprr2Spec;
impl crate::RegisterSpec for R32PficIprr2Spec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprr2::W`](W) writer structure"]
impl crate::Writable for R32PficIprr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRR2 to value 0"]
impl crate::Resettable for R32PficIprr2Spec {}
}
#[doc = "R32_PFIC_IACTR1 (rw) register accessor: Interrupt ACTIVE Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iactr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iactr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iactr1`] module"]
#[doc(alias = "R32_PFIC_IACTR1")]
pub type R32PficIactr1 = crate::Reg<r32_pfic_iactr1::R32PficIactr1Spec>;
#[doc = "Interrupt ACTIVE Register"]
pub mod r32_pfic_iactr1 {
#[doc = "Register `R32_PFIC_IACTR1` reader"]
pub type R = crate::R<R32PficIactr1Spec>;
#[doc = "Register `R32_PFIC_IACTR1` writer"]
pub type W = crate::W<R32PficIactr1Spec>;
#[doc = "Field `IACTS` reader - RW1,IACTS"]
pub type IactsR = crate::FieldReader<u32>;
#[doc = "Field `IACTS` writer - RW1,IACTS"]
pub type IactsW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl R {
#[doc = "Bits 12:31 - RW1,IACTS"]
#[inline(always)]
pub fn iacts(&self) -> IactsR {
IactsR::new((self.bits >> 12) & 0x000f_ffff)
}
}
impl W {
#[doc = "Bits 12:31 - RW1,IACTS"]
#[inline(always)]
pub fn iacts(&mut self) -> IactsW<R32PficIactr1Spec> {
IactsW::new(self, 12)
}
}
#[doc = "Interrupt ACTIVE Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iactr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iactr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIactr1Spec;
impl crate::RegisterSpec for R32PficIactr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iactr1::R`](R) reader structure"]
impl crate::Readable for R32PficIactr1Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iactr1::W`](W) writer structure"]
impl crate::Writable for R32PficIactr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IACTR1 to value 0"]
impl crate::Resettable for R32PficIactr1Spec {}
}
#[doc = "R32_PFIC_IACTR2 (rw) register accessor: Interrupt ACTIVE Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iactr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iactr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iactr2`] module"]
#[doc(alias = "R32_PFIC_IACTR2")]
pub type R32PficIactr2 = crate::Reg<r32_pfic_iactr2::R32PficIactr2Spec>;
#[doc = "Interrupt ACTIVE Register"]
pub mod r32_pfic_iactr2 {
#[doc = "Register `R32_PFIC_IACTR2` reader"]
pub type R = crate::R<R32PficIactr2Spec>;
#[doc = "Register `R32_PFIC_IACTR2` writer"]
pub type W = crate::W<R32PficIactr2Spec>;
#[doc = "Field `IACTS` reader - RW1,IACTS"]
pub type IactsR = crate::FieldReader;
#[doc = "Field `IACTS` writer - RW1,IACTS"]
pub type IactsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - RW1,IACTS"]
#[inline(always)]
pub fn iacts(&self) -> IactsR {
IactsR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - RW1,IACTS"]
#[inline(always)]
pub fn iacts(&mut self) -> IactsW<R32PficIactr2Spec> {
IactsW::new(self, 0)
}
}
#[doc = "Interrupt ACTIVE Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iactr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iactr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIactr2Spec;
impl crate::RegisterSpec for R32PficIactr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iactr2::R`](R) reader structure"]
impl crate::Readable for R32PficIactr2Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iactr2::W`](W) writer structure"]
impl crate::Writable for R32PficIactr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IACTR2 to value 0"]
impl crate::Resettable for R32PficIactr2Spec {}
}
#[doc = "R32_PFIC_IPRIOR0 (rw) register accessor: Interrupt Priority configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior0`] module"]
#[doc(alias = "R32_PFIC_IPRIOR0")]
pub type R32PficIprior0 = crate::Reg<r32_pfic_iprior0::R32PficIprior0Spec>;
#[doc = "Interrupt Priority configuration Register 0"]
pub mod r32_pfic_iprior0 {
#[doc = "Register `R32_PFIC_IPRIOR0` reader"]
pub type R = crate::R<R32PficIprior0Spec>;
#[doc = "Register `R32_PFIC_IPRIOR0` writer"]
pub type W = crate::W<R32PficIprior0Spec>;
#[doc = "Field `IPRIOR0` reader - RW,Interrupt priority for number 0-3"]
pub type Iprior0R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR0` writer - RW,Interrupt priority for number 0-3"]
pub type Iprior0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 0-3"]
#[inline(always)]
pub fn iprior0(&self) -> Iprior0R {
Iprior0R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 0-3"]
#[inline(always)]
pub fn iprior0(&mut self) -> Iprior0W<R32PficIprior0Spec> {
Iprior0W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior0Spec;
impl crate::RegisterSpec for R32PficIprior0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior0::R`](R) reader structure"]
impl crate::Readable for R32PficIprior0Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior0::W`](W) writer structure"]
impl crate::Writable for R32PficIprior0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR0 to value 0"]
impl crate::Resettable for R32PficIprior0Spec {}
}
#[doc = "R32_PFIC_IPRIOR1 (rw) register accessor: Interrupt Priority configuration Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior1`] module"]
#[doc(alias = "R32_PFIC_IPRIOR1")]
pub type R32PficIprior1 = crate::Reg<r32_pfic_iprior1::R32PficIprior1Spec>;
#[doc = "Interrupt Priority configuration Register 1"]
pub mod r32_pfic_iprior1 {
#[doc = "Register `R32_PFIC_IPRIOR1` reader"]
pub type R = crate::R<R32PficIprior1Spec>;
#[doc = "Register `R32_PFIC_IPRIOR1` writer"]
pub type W = crate::W<R32PficIprior1Spec>;
#[doc = "Field `IPRIOR1` reader - >RW,Interrupt priority for number 4-7"]
pub type Iprior1R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR1` writer - >RW,Interrupt priority for number 4-7"]
pub type Iprior1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 4-7"]
#[inline(always)]
pub fn iprior1(&self) -> Iprior1R {
Iprior1R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 4-7"]
#[inline(always)]
pub fn iprior1(&mut self) -> Iprior1W<R32PficIprior1Spec> {
Iprior1W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior1Spec;
impl crate::RegisterSpec for R32PficIprior1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior1::R`](R) reader structure"]
impl crate::Readable for R32PficIprior1Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior1::W`](W) writer structure"]
impl crate::Writable for R32PficIprior1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR1 to value 0"]
impl crate::Resettable for R32PficIprior1Spec {}
}
#[doc = "R32_PFIC_IPRIOR2 (rw) register accessor: Interrupt Priority configuration Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior2`] module"]
#[doc(alias = "R32_PFIC_IPRIOR2")]
pub type R32PficIprior2 = crate::Reg<r32_pfic_iprior2::R32PficIprior2Spec>;
#[doc = "Interrupt Priority configuration Register 2"]
pub mod r32_pfic_iprior2 {
#[doc = "Register `R32_PFIC_IPRIOR2` reader"]
pub type R = crate::R<R32PficIprior2Spec>;
#[doc = "Register `R32_PFIC_IPRIOR2` writer"]
pub type W = crate::W<R32PficIprior2Spec>;
#[doc = "Field `IPRIOR2` reader - >RW,Interrupt priority for number 8-11"]
pub type Iprior2R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR2` writer - >RW,Interrupt priority for number 8-11"]
pub type Iprior2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 8-11"]
#[inline(always)]
pub fn iprior2(&self) -> Iprior2R {
Iprior2R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 8-11"]
#[inline(always)]
pub fn iprior2(&mut self) -> Iprior2W<R32PficIprior2Spec> {
Iprior2W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior2Spec;
impl crate::RegisterSpec for R32PficIprior2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior2::R`](R) reader structure"]
impl crate::Readable for R32PficIprior2Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior2::W`](W) writer structure"]
impl crate::Writable for R32PficIprior2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR2 to value 0"]
impl crate::Resettable for R32PficIprior2Spec {}
}
#[doc = "R32_PFIC_IPRIOR3 (rw) register accessor: Interrupt Priority configuration Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior3`] module"]
#[doc(alias = "R32_PFIC_IPRIOR3")]
pub type R32PficIprior3 = crate::Reg<r32_pfic_iprior3::R32PficIprior3Spec>;
#[doc = "Interrupt Priority configuration Register 3"]
pub mod r32_pfic_iprior3 {
#[doc = "Register `R32_PFIC_IPRIOR3` reader"]
pub type R = crate::R<R32PficIprior3Spec>;
#[doc = "Register `R32_PFIC_IPRIOR3` writer"]
pub type W = crate::W<R32PficIprior3Spec>;
#[doc = "Field `IPRIOR3` reader - >RW,Interrupt priority for number 12-15"]
pub type Iprior3R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR3` writer - >RW,Interrupt priority for number 12-15"]
pub type Iprior3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 12-15"]
#[inline(always)]
pub fn iprior3(&self) -> Iprior3R {
Iprior3R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 12-15"]
#[inline(always)]
pub fn iprior3(&mut self) -> Iprior3W<R32PficIprior3Spec> {
Iprior3W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior3Spec;
impl crate::RegisterSpec for R32PficIprior3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior3::R`](R) reader structure"]
impl crate::Readable for R32PficIprior3Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior3::W`](W) writer structure"]
impl crate::Writable for R32PficIprior3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR3 to value 0"]
impl crate::Resettable for R32PficIprior3Spec {}
}
#[doc = "R32_PFIC_IPRIOR4 (rw) register accessor: Interrupt Priority configuration Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior4`] module"]
#[doc(alias = "R32_PFIC_IPRIOR4")]
pub type R32PficIprior4 = crate::Reg<r32_pfic_iprior4::R32PficIprior4Spec>;
#[doc = "Interrupt Priority configuration Register 4"]
pub mod r32_pfic_iprior4 {
#[doc = "Register `R32_PFIC_IPRIOR4` reader"]
pub type R = crate::R<R32PficIprior4Spec>;
#[doc = "Register `R32_PFIC_IPRIOR4` writer"]
pub type W = crate::W<R32PficIprior4Spec>;
#[doc = "Field `IPRIOR4` reader - >RW,Interrupt priority for number 16-19"]
pub type Iprior4R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR4` writer - >RW,Interrupt priority for number 16-19"]
pub type Iprior4W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 16-19"]
#[inline(always)]
pub fn iprior4(&self) -> Iprior4R {
Iprior4R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 16-19"]
#[inline(always)]
pub fn iprior4(&mut self) -> Iprior4W<R32PficIprior4Spec> {
Iprior4W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior4Spec;
impl crate::RegisterSpec for R32PficIprior4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior4::R`](R) reader structure"]
impl crate::Readable for R32PficIprior4Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior4::W`](W) writer structure"]
impl crate::Writable for R32PficIprior4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR4 to value 0"]
impl crate::Resettable for R32PficIprior4Spec {}
}
#[doc = "R32_PFIC_IPRIOR5 (rw) register accessor: Interrupt Priority configuration Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior5`] module"]
#[doc(alias = "R32_PFIC_IPRIOR5")]
pub type R32PficIprior5 = crate::Reg<r32_pfic_iprior5::R32PficIprior5Spec>;
#[doc = "Interrupt Priority configuration Register 5"]
pub mod r32_pfic_iprior5 {
#[doc = "Register `R32_PFIC_IPRIOR5` reader"]
pub type R = crate::R<R32PficIprior5Spec>;
#[doc = "Register `R32_PFIC_IPRIOR5` writer"]
pub type W = crate::W<R32PficIprior5Spec>;
#[doc = "Field `IPRIOR5` reader - >RW,Interrupt priority for number 20-23"]
pub type Iprior5R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR5` writer - >RW,Interrupt priority for number 20-23"]
pub type Iprior5W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 20-23"]
#[inline(always)]
pub fn iprior5(&self) -> Iprior5R {
Iprior5R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 20-23"]
#[inline(always)]
pub fn iprior5(&mut self) -> Iprior5W<R32PficIprior5Spec> {
Iprior5W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior5Spec;
impl crate::RegisterSpec for R32PficIprior5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior5::R`](R) reader structure"]
impl crate::Readable for R32PficIprior5Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior5::W`](W) writer structure"]
impl crate::Writable for R32PficIprior5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR5 to value 0"]
impl crate::Resettable for R32PficIprior5Spec {}
}
#[doc = "R32_PFIC_IPRIOR6 (rw) register accessor: Interrupt Priority configuration Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior6`] module"]
#[doc(alias = "R32_PFIC_IPRIOR6")]
pub type R32PficIprior6 = crate::Reg<r32_pfic_iprior6::R32PficIprior6Spec>;
#[doc = "Interrupt Priority configuration Register 6"]
pub mod r32_pfic_iprior6 {
#[doc = "Register `R32_PFIC_IPRIOR6` reader"]
pub type R = crate::R<R32PficIprior6Spec>;
#[doc = "Register `R32_PFIC_IPRIOR6` writer"]
pub type W = crate::W<R32PficIprior6Spec>;
#[doc = "Field `IPRIOR6` reader - >RW,Interrupt priority for number 24-27"]
pub type Iprior6R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR6` writer - >RW,Interrupt priority for number 24-27"]
pub type Iprior6W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 24-27"]
#[inline(always)]
pub fn iprior6(&self) -> Iprior6R {
Iprior6R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 24-27"]
#[inline(always)]
pub fn iprior6(&mut self) -> Iprior6W<R32PficIprior6Spec> {
Iprior6W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior6Spec;
impl crate::RegisterSpec for R32PficIprior6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior6::R`](R) reader structure"]
impl crate::Readable for R32PficIprior6Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior6::W`](W) writer structure"]
impl crate::Writable for R32PficIprior6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR6 to value 0"]
impl crate::Resettable for R32PficIprior6Spec {}
}
#[doc = "R32_PFIC_IPRIOR7 (rw) register accessor: Interrupt Priority configuration Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior7`] module"]
#[doc(alias = "R32_PFIC_IPRIOR7")]
pub type R32PficIprior7 = crate::Reg<r32_pfic_iprior7::R32PficIprior7Spec>;
#[doc = "Interrupt Priority configuration Register 7"]
pub mod r32_pfic_iprior7 {
#[doc = "Register `R32_PFIC_IPRIOR7` reader"]
pub type R = crate::R<R32PficIprior7Spec>;
#[doc = "Register `R32_PFIC_IPRIOR7` writer"]
pub type W = crate::W<R32PficIprior7Spec>;
#[doc = "Field `IPRIOR7` reader - >RW,Interrupt priority for number 28-31"]
pub type Iprior7R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR7` writer - >RW,Interrupt priority for number 28-31"]
pub type Iprior7W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 28-31"]
#[inline(always)]
pub fn iprior7(&self) -> Iprior7R {
Iprior7R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 28-31"]
#[inline(always)]
pub fn iprior7(&mut self) -> Iprior7W<R32PficIprior7Spec> {
Iprior7W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior7Spec;
impl crate::RegisterSpec for R32PficIprior7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior7::R`](R) reader structure"]
impl crate::Readable for R32PficIprior7Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior7::W`](W) writer structure"]
impl crate::Writable for R32PficIprior7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR7 to value 0"]
impl crate::Resettable for R32PficIprior7Spec {}
}
#[doc = "R32_PFIC_IPRIOR8 (rw) register accessor: Interrupt Priority configuration Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior8`] module"]
#[doc(alias = "R32_PFIC_IPRIOR8")]
pub type R32PficIprior8 = crate::Reg<r32_pfic_iprior8::R32PficIprior8Spec>;
#[doc = "Interrupt Priority configuration Register 8"]
pub mod r32_pfic_iprior8 {
#[doc = "Register `R32_PFIC_IPRIOR8` reader"]
pub type R = crate::R<R32PficIprior8Spec>;
#[doc = "Register `R32_PFIC_IPRIOR8` writer"]
pub type W = crate::W<R32PficIprior8Spec>;
#[doc = "Field `IPRIOR8` reader - RW,Interrupt priority for number 32-35"]
pub type Iprior8R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR8` writer - RW,Interrupt priority for number 32-35"]
pub type Iprior8W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 32-35"]
#[inline(always)]
pub fn iprior8(&self) -> Iprior8R {
Iprior8R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 32-35"]
#[inline(always)]
pub fn iprior8(&mut self) -> Iprior8W<R32PficIprior8Spec> {
Iprior8W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior8Spec;
impl crate::RegisterSpec for R32PficIprior8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior8::R`](R) reader structure"]
impl crate::Readable for R32PficIprior8Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior8::W`](W) writer structure"]
impl crate::Writable for R32PficIprior8Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR8 to value 0"]
impl crate::Resettable for R32PficIprior8Spec {}
}
#[doc = "R32_PFIC_IPRIOR9 (rw) register accessor: Interrupt Priority configuration Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior9`] module"]
#[doc(alias = "R32_PFIC_IPRIOR9")]
pub type R32PficIprior9 = crate::Reg<r32_pfic_iprior9::R32PficIprior9Spec>;
#[doc = "Interrupt Priority configuration Register 9"]
pub mod r32_pfic_iprior9 {
#[doc = "Register `R32_PFIC_IPRIOR9` reader"]
pub type R = crate::R<R32PficIprior9Spec>;
#[doc = "Register `R32_PFIC_IPRIOR9` writer"]
pub type W = crate::W<R32PficIprior9Spec>;
#[doc = "Field `IPRIOR9` reader - >RW,Interrupt priority for number 36-39"]
pub type Iprior9R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR9` writer - >RW,Interrupt priority for number 36-39"]
pub type Iprior9W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 36-39"]
#[inline(always)]
pub fn iprior9(&self) -> Iprior9R {
Iprior9R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 36-39"]
#[inline(always)]
pub fn iprior9(&mut self) -> Iprior9W<R32PficIprior9Spec> {
Iprior9W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior9Spec;
impl crate::RegisterSpec for R32PficIprior9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior9::R`](R) reader structure"]
impl crate::Readable for R32PficIprior9Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior9::W`](W) writer structure"]
impl crate::Writable for R32PficIprior9Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR9 to value 0"]
impl crate::Resettable for R32PficIprior9Spec {}
}
#[doc = "R32_PFIC_IPRIOR10 (rw) register accessor: Interrupt Priority configuration Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior10`] module"]
#[doc(alias = "R32_PFIC_IPRIOR10")]
pub type R32PficIprior10 = crate::Reg<r32_pfic_iprior10::R32PficIprior10Spec>;
#[doc = "Interrupt Priority configuration Register 10"]
pub mod r32_pfic_iprior10 {
#[doc = "Register `R32_PFIC_IPRIOR10` reader"]
pub type R = crate::R<R32PficIprior10Spec>;
#[doc = "Register `R32_PFIC_IPRIOR10` writer"]
pub type W = crate::W<R32PficIprior10Spec>;
#[doc = "Field `IPRIOR10` reader - >RW,Interrupt priority for number 40-43"]
pub type Iprior10R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR10` writer - >RW,Interrupt priority for number 40-43"]
pub type Iprior10W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 40-43"]
#[inline(always)]
pub fn iprior10(&self) -> Iprior10R {
Iprior10R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - >RW,Interrupt priority for number 40-43"]
#[inline(always)]
pub fn iprior10(&mut self) -> Iprior10W<R32PficIprior10Spec> {
Iprior10W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior10Spec;
impl crate::RegisterSpec for R32PficIprior10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior10::R`](R) reader structure"]
impl crate::Readable for R32PficIprior10Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior10::W`](W) writer structure"]
impl crate::Writable for R32PficIprior10Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR10 to value 0"]
impl crate::Resettable for R32PficIprior10Spec {}
}
#[doc = "R32_PFIC_IPRIOR11 (rw) register accessor: Interrupt Priority configuration Register 11\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior11`] module"]
#[doc(alias = "R32_PFIC_IPRIOR11")]
pub type R32PficIprior11 = crate::Reg<r32_pfic_iprior11::R32PficIprior11Spec>;
#[doc = "Interrupt Priority configuration Register 11"]
pub mod r32_pfic_iprior11 {
#[doc = "Register `R32_PFIC_IPRIOR11` reader"]
pub type R = crate::R<R32PficIprior11Spec>;
#[doc = "Register `R32_PFIC_IPRIOR11` writer"]
pub type W = crate::W<R32PficIprior11Spec>;
#[doc = "Field `IPRIOR11` reader - RW,Interrupt priority for number 44-47"]
pub type Iprior11R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR11` writer - RW,Interrupt priority for number 44-47"]
pub type Iprior11W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 44-47"]
#[inline(always)]
pub fn iprior11(&self) -> Iprior11R {
Iprior11R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 44-47"]
#[inline(always)]
pub fn iprior11(&mut self) -> Iprior11W<R32PficIprior11Spec> {
Iprior11W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 11\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior11Spec;
impl crate::RegisterSpec for R32PficIprior11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior11::R`](R) reader structure"]
impl crate::Readable for R32PficIprior11Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior11::W`](W) writer structure"]
impl crate::Writable for R32PficIprior11Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR11 to value 0"]
impl crate::Resettable for R32PficIprior11Spec {}
}
#[doc = "R32_PFIC_IPRIOR12 (rw) register accessor: Interrupt Priority configuration Register 12\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior12`] module"]
#[doc(alias = "R32_PFIC_IPRIOR12")]
pub type R32PficIprior12 = crate::Reg<r32_pfic_iprior12::R32PficIprior12Spec>;
#[doc = "Interrupt Priority configuration Register 12"]
pub mod r32_pfic_iprior12 {
#[doc = "Register `R32_PFIC_IPRIOR12` reader"]
pub type R = crate::R<R32PficIprior12Spec>;
#[doc = "Register `R32_PFIC_IPRIOR12` writer"]
pub type W = crate::W<R32PficIprior12Spec>;
#[doc = "Field `IPRIOR12` reader - RW,Interrupt priority for number 48-51"]
pub type Iprior12R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR12` writer - RW,Interrupt priority for number 48-51"]
pub type Iprior12W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 48-51"]
#[inline(always)]
pub fn iprior12(&self) -> Iprior12R {
Iprior12R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 48-51"]
#[inline(always)]
pub fn iprior12(&mut self) -> Iprior12W<R32PficIprior12Spec> {
Iprior12W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 12\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior12Spec;
impl crate::RegisterSpec for R32PficIprior12Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior12::R`](R) reader structure"]
impl crate::Readable for R32PficIprior12Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior12::W`](W) writer structure"]
impl crate::Writable for R32PficIprior12Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR12 to value 0"]
impl crate::Resettable for R32PficIprior12Spec {}
}
#[doc = "R32_PFIC_IPRIOR13 (rw) register accessor: Interrupt Priority configuration Register 13\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior13`] module"]
#[doc(alias = "R32_PFIC_IPRIOR13")]
pub type R32PficIprior13 = crate::Reg<r32_pfic_iprior13::R32PficIprior13Spec>;
#[doc = "Interrupt Priority configuration Register 13"]
pub mod r32_pfic_iprior13 {
#[doc = "Register `R32_PFIC_IPRIOR13` reader"]
pub type R = crate::R<R32PficIprior13Spec>;
#[doc = "Register `R32_PFIC_IPRIOR13` writer"]
pub type W = crate::W<R32PficIprior13Spec>;
#[doc = "Field `IPRIOR13` reader - RW,Interrupt priority for number 52-55"]
pub type Iprior13R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR13` writer - RW,Interrupt priority for number 52-55"]
pub type Iprior13W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 52-55"]
#[inline(always)]
pub fn iprior13(&self) -> Iprior13R {
Iprior13R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 52-55"]
#[inline(always)]
pub fn iprior13(&mut self) -> Iprior13W<R32PficIprior13Spec> {
Iprior13W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 13\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior13Spec;
impl crate::RegisterSpec for R32PficIprior13Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior13::R`](R) reader structure"]
impl crate::Readable for R32PficIprior13Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior13::W`](W) writer structure"]
impl crate::Writable for R32PficIprior13Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR13 to value 0"]
impl crate::Resettable for R32PficIprior13Spec {}
}
#[doc = "R32_PFIC_IPRIOR14 (rw) register accessor: Interrupt Priority configuration Register 14\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior14`] module"]
#[doc(alias = "R32_PFIC_IPRIOR14")]
pub type R32PficIprior14 = crate::Reg<r32_pfic_iprior14::R32PficIprior14Spec>;
#[doc = "Interrupt Priority configuration Register 14"]
pub mod r32_pfic_iprior14 {
#[doc = "Register `R32_PFIC_IPRIOR14` reader"]
pub type R = crate::R<R32PficIprior14Spec>;
#[doc = "Register `R32_PFIC_IPRIOR14` writer"]
pub type W = crate::W<R32PficIprior14Spec>;
#[doc = "Field `IPRIOR14` reader - RW,Interrupt priority for number 56-59"]
pub type Iprior14R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR14` writer - RW,Interrupt priority for number 56-59"]
pub type Iprior14W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 56-59"]
#[inline(always)]
pub fn iprior14(&self) -> Iprior14R {
Iprior14R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 56-59"]
#[inline(always)]
pub fn iprior14(&mut self) -> Iprior14W<R32PficIprior14Spec> {
Iprior14W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 14\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior14Spec;
impl crate::RegisterSpec for R32PficIprior14Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior14::R`](R) reader structure"]
impl crate::Readable for R32PficIprior14Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior14::W`](W) writer structure"]
impl crate::Writable for R32PficIprior14Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR14 to value 0"]
impl crate::Resettable for R32PficIprior14Spec {}
}
#[doc = "R32_PFIC_IPRIOR15 (rw) register accessor: Interrupt Priority configuration Register 15\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior15`] module"]
#[doc(alias = "R32_PFIC_IPRIOR15")]
pub type R32PficIprior15 = crate::Reg<r32_pfic_iprior15::R32PficIprior15Spec>;
#[doc = "Interrupt Priority configuration Register 15"]
pub mod r32_pfic_iprior15 {
#[doc = "Register `R32_PFIC_IPRIOR15` reader"]
pub type R = crate::R<R32PficIprior15Spec>;
#[doc = "Register `R32_PFIC_IPRIOR15` writer"]
pub type W = crate::W<R32PficIprior15Spec>;
#[doc = "Field `IPRIOR15` reader - RW,Interrupt priority for number 60-63"]
pub type Iprior15R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR15` writer - RW,Interrupt priority for number 60-63"]
pub type Iprior15W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 60-63"]
#[inline(always)]
pub fn iprior15(&self) -> Iprior15R {
Iprior15R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 60-63"]
#[inline(always)]
pub fn iprior15(&mut self) -> Iprior15W<R32PficIprior15Spec> {
Iprior15W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 15\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior15Spec;
impl crate::RegisterSpec for R32PficIprior15Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior15::R`](R) reader structure"]
impl crate::Readable for R32PficIprior15Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior15::W`](W) writer structure"]
impl crate::Writable for R32PficIprior15Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR15 to value 0"]
impl crate::Resettable for R32PficIprior15Spec {}
}
#[doc = "R32_PFIC_IPRIOR16 (rw) register accessor: Interrupt Priority configuration Register 16\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior16`] module"]
#[doc(alias = "R32_PFIC_IPRIOR16")]
pub type R32PficIprior16 = crate::Reg<r32_pfic_iprior16::R32PficIprior16Spec>;
#[doc = "Interrupt Priority configuration Register 16"]
pub mod r32_pfic_iprior16 {
#[doc = "Register `R32_PFIC_IPRIOR16` reader"]
pub type R = crate::R<R32PficIprior16Spec>;
#[doc = "Register `R32_PFIC_IPRIOR16` writer"]
pub type W = crate::W<R32PficIprior16Spec>;
#[doc = "Field `IPRIOR16` reader - RW,Interrupt priority for number 64-67"]
pub type Iprior16R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR16` writer - RW,Interrupt priority for number 64-67"]
pub type Iprior16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 64-67"]
#[inline(always)]
pub fn iprior16(&self) -> Iprior16R {
Iprior16R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 64-67"]
#[inline(always)]
pub fn iprior16(&mut self) -> Iprior16W<R32PficIprior16Spec> {
Iprior16W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 16\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior16Spec;
impl crate::RegisterSpec for R32PficIprior16Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior16::R`](R) reader structure"]
impl crate::Readable for R32PficIprior16Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior16::W`](W) writer structure"]
impl crate::Writable for R32PficIprior16Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR16 to value 0"]
impl crate::Resettable for R32PficIprior16Spec {}
}
#[doc = "R32_PFIC_IPRIOR17 (rw) register accessor: Interrupt Priority configuration Register 17\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior17`] module"]
#[doc(alias = "R32_PFIC_IPRIOR17")]
pub type R32PficIprior17 = crate::Reg<r32_pfic_iprior17::R32PficIprior17Spec>;
#[doc = "Interrupt Priority configuration Register 17"]
pub mod r32_pfic_iprior17 {
#[doc = "Register `R32_PFIC_IPRIOR17` reader"]
pub type R = crate::R<R32PficIprior17Spec>;
#[doc = "Register `R32_PFIC_IPRIOR17` writer"]
pub type W = crate::W<R32PficIprior17Spec>;
#[doc = "Field `IPRIOR17` reader - RW,Interrupt priority for number 68-71"]
pub type Iprior17R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR17` writer - RW,Interrupt priority for number 68-71"]
pub type Iprior17W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 68-71"]
#[inline(always)]
pub fn iprior17(&self) -> Iprior17R {
Iprior17R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 68-71"]
#[inline(always)]
pub fn iprior17(&mut self) -> Iprior17W<R32PficIprior17Spec> {
Iprior17W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 17\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior17Spec;
impl crate::RegisterSpec for R32PficIprior17Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior17::R`](R) reader structure"]
impl crate::Readable for R32PficIprior17Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior17::W`](W) writer structure"]
impl crate::Writable for R32PficIprior17Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR17 to value 0"]
impl crate::Resettable for R32PficIprior17Spec {}
}
#[doc = "R32_PFIC_IPRIOR18 (rw) register accessor: Interrupt Priority configuration Register 18\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior18`] module"]
#[doc(alias = "R32_PFIC_IPRIOR18")]
pub type R32PficIprior18 = crate::Reg<r32_pfic_iprior18::R32PficIprior18Spec>;
#[doc = "Interrupt Priority configuration Register 18"]
pub mod r32_pfic_iprior18 {
#[doc = "Register `R32_PFIC_IPRIOR18` reader"]
pub type R = crate::R<R32PficIprior18Spec>;
#[doc = "Register `R32_PFIC_IPRIOR18` writer"]
pub type W = crate::W<R32PficIprior18Spec>;
#[doc = "Field `IPRIOR18` reader - RW,Interrupt priority for number 72-75"]
pub type Iprior18R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR18` writer - RW,Interrupt priority for number 72-75"]
pub type Iprior18W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 72-75"]
#[inline(always)]
pub fn iprior18(&self) -> Iprior18R {
Iprior18R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 72-75"]
#[inline(always)]
pub fn iprior18(&mut self) -> Iprior18W<R32PficIprior18Spec> {
Iprior18W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 18\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior18Spec;
impl crate::RegisterSpec for R32PficIprior18Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior18::R`](R) reader structure"]
impl crate::Readable for R32PficIprior18Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior18::W`](W) writer structure"]
impl crate::Writable for R32PficIprior18Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR18 to value 0"]
impl crate::Resettable for R32PficIprior18Spec {}
}
#[doc = "R32_PFIC_IPRIOR19 (rw) register accessor: Interrupt Priority configuration Register 19\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior19`] module"]
#[doc(alias = "R32_PFIC_IPRIOR19")]
pub type R32PficIprior19 = crate::Reg<r32_pfic_iprior19::R32PficIprior19Spec>;
#[doc = "Interrupt Priority configuration Register 19"]
pub mod r32_pfic_iprior19 {
#[doc = "Register `R32_PFIC_IPRIOR19` reader"]
pub type R = crate::R<R32PficIprior19Spec>;
#[doc = "Register `R32_PFIC_IPRIOR19` writer"]
pub type W = crate::W<R32PficIprior19Spec>;
#[doc = "Field `IPRIOR19` reader - RW,Interrupt priority for number 76-79"]
pub type Iprior19R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR19` writer - RW,Interrupt priority for number 76-79"]
pub type Iprior19W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 76-79"]
#[inline(always)]
pub fn iprior19(&self) -> Iprior19R {
Iprior19R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 76-79"]
#[inline(always)]
pub fn iprior19(&mut self) -> Iprior19W<R32PficIprior19Spec> {
Iprior19W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 19\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior19Spec;
impl crate::RegisterSpec for R32PficIprior19Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior19::R`](R) reader structure"]
impl crate::Readable for R32PficIprior19Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior19::W`](W) writer structure"]
impl crate::Writable for R32PficIprior19Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR19 to value 0"]
impl crate::Resettable for R32PficIprior19Spec {}
}
#[doc = "R32_PFIC_IPRIOR20 (rw) register accessor: Interrupt Priority configuration Register 20\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior20`] module"]
#[doc(alias = "R32_PFIC_IPRIOR20")]
pub type R32PficIprior20 = crate::Reg<r32_pfic_iprior20::R32PficIprior20Spec>;
#[doc = "Interrupt Priority configuration Register 20"]
pub mod r32_pfic_iprior20 {
#[doc = "Register `R32_PFIC_IPRIOR20` reader"]
pub type R = crate::R<R32PficIprior20Spec>;
#[doc = "Register `R32_PFIC_IPRIOR20` writer"]
pub type W = crate::W<R32PficIprior20Spec>;
#[doc = "Field `IPRIOR20` reader - RW,RW,Interrupt priority for number 80-83"]
pub type Iprior20R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR20` writer - RW,RW,Interrupt priority for number 80-83"]
pub type Iprior20W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,RW,Interrupt priority for number 80-83"]
#[inline(always)]
pub fn iprior20(&self) -> Iprior20R {
Iprior20R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,RW,Interrupt priority for number 80-83"]
#[inline(always)]
pub fn iprior20(&mut self) -> Iprior20W<R32PficIprior20Spec> {
Iprior20W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 20\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior20Spec;
impl crate::RegisterSpec for R32PficIprior20Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior20::R`](R) reader structure"]
impl crate::Readable for R32PficIprior20Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior20::W`](W) writer structure"]
impl crate::Writable for R32PficIprior20Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR20 to value 0"]
impl crate::Resettable for R32PficIprior20Spec {}
}
#[doc = "R32_PFIC_IPRIOR21 (rw) register accessor: Interrupt Priority configuration Register 21\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior21`] module"]
#[doc(alias = "R32_PFIC_IPRIOR21")]
pub type R32PficIprior21 = crate::Reg<r32_pfic_iprior21::R32PficIprior21Spec>;
#[doc = "Interrupt Priority configuration Register 21"]
pub mod r32_pfic_iprior21 {
#[doc = "Register `R32_PFIC_IPRIOR21` reader"]
pub type R = crate::R<R32PficIprior21Spec>;
#[doc = "Register `R32_PFIC_IPRIOR21` writer"]
pub type W = crate::W<R32PficIprior21Spec>;
#[doc = "Field `IPRIOR21` reader - RW,Interrupt priority for number 84-87"]
pub type Iprior21R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR21` writer - RW,Interrupt priority for number 84-87"]
pub type Iprior21W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 84-87"]
#[inline(always)]
pub fn iprior21(&self) -> Iprior21R {
Iprior21R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 84-87"]
#[inline(always)]
pub fn iprior21(&mut self) -> Iprior21W<R32PficIprior21Spec> {
Iprior21W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 21\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior21Spec;
impl crate::RegisterSpec for R32PficIprior21Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior21::R`](R) reader structure"]
impl crate::Readable for R32PficIprior21Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior21::W`](W) writer structure"]
impl crate::Writable for R32PficIprior21Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR21 to value 0"]
impl crate::Resettable for R32PficIprior21Spec {}
}
#[doc = "R32_PFIC_IPRIOR22 (rw) register accessor: Interrupt Priority configuration Register 22\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior22`] module"]
#[doc(alias = "R32_PFIC_IPRIOR22")]
pub type R32PficIprior22 = crate::Reg<r32_pfic_iprior22::R32PficIprior22Spec>;
#[doc = "Interrupt Priority configuration Register 22"]
pub mod r32_pfic_iprior22 {
#[doc = "Register `R32_PFIC_IPRIOR22` reader"]
pub type R = crate::R<R32PficIprior22Spec>;
#[doc = "Register `R32_PFIC_IPRIOR22` writer"]
pub type W = crate::W<R32PficIprior22Spec>;
#[doc = "Field `IPRIOR22` reader - RW,Interrupt priority for number 88-91"]
pub type Iprior22R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR22` writer - RW,Interrupt priority for number 88-91"]
pub type Iprior22W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 88-91"]
#[inline(always)]
pub fn iprior22(&self) -> Iprior22R {
Iprior22R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 88-91"]
#[inline(always)]
pub fn iprior22(&mut self) -> Iprior22W<R32PficIprior22Spec> {
Iprior22W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 22\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior22Spec;
impl crate::RegisterSpec for R32PficIprior22Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior22::R`](R) reader structure"]
impl crate::Readable for R32PficIprior22Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior22::W`](W) writer structure"]
impl crate::Writable for R32PficIprior22Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR22 to value 0"]
impl crate::Resettable for R32PficIprior22Spec {}
}
#[doc = "R32_PFIC_IPRIOR23 (rw) register accessor: Interrupt Priority configuration Register 23\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior23`] module"]
#[doc(alias = "R32_PFIC_IPRIOR23")]
pub type R32PficIprior23 = crate::Reg<r32_pfic_iprior23::R32PficIprior23Spec>;
#[doc = "Interrupt Priority configuration Register 23"]
pub mod r32_pfic_iprior23 {
#[doc = "Register `R32_PFIC_IPRIOR23` reader"]
pub type R = crate::R<R32PficIprior23Spec>;
#[doc = "Register `R32_PFIC_IPRIOR23` writer"]
pub type W = crate::W<R32PficIprior23Spec>;
#[doc = "Field `IPRIOR23` reader - RW,Interrupt priority for number 92-95"]
pub type Iprior23R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR23` writer - RW,Interrupt priority for number 92-95"]
pub type Iprior23W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 92-95"]
#[inline(always)]
pub fn iprior23(&self) -> Iprior23R {
Iprior23R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 92-95"]
#[inline(always)]
pub fn iprior23(&mut self) -> Iprior23W<R32PficIprior23Spec> {
Iprior23W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 23\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior23Spec;
impl crate::RegisterSpec for R32PficIprior23Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior23::R`](R) reader structure"]
impl crate::Readable for R32PficIprior23Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior23::W`](W) writer structure"]
impl crate::Writable for R32PficIprior23Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR23 to value 0"]
impl crate::Resettable for R32PficIprior23Spec {}
}
#[doc = "R32_PFIC_IPRIOR24 (rw) register accessor: Interrupt Priority configuration Register 24\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior24`] module"]
#[doc(alias = "R32_PFIC_IPRIOR24")]
pub type R32PficIprior24 = crate::Reg<r32_pfic_iprior24::R32PficIprior24Spec>;
#[doc = "Interrupt Priority configuration Register 24"]
pub mod r32_pfic_iprior24 {
#[doc = "Register `R32_PFIC_IPRIOR24` reader"]
pub type R = crate::R<R32PficIprior24Spec>;
#[doc = "Register `R32_PFIC_IPRIOR24` writer"]
pub type W = crate::W<R32PficIprior24Spec>;
#[doc = "Field `IPRIOR24` reader - RW,Interrupt priority for number 96-99"]
pub type Iprior24R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR24` writer - RW,Interrupt priority for number 96-99"]
pub type Iprior24W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 96-99"]
#[inline(always)]
pub fn iprior24(&self) -> Iprior24R {
Iprior24R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 96-99"]
#[inline(always)]
pub fn iprior24(&mut self) -> Iprior24W<R32PficIprior24Spec> {
Iprior24W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 24\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior24Spec;
impl crate::RegisterSpec for R32PficIprior24Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior24::R`](R) reader structure"]
impl crate::Readable for R32PficIprior24Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior24::W`](W) writer structure"]
impl crate::Writable for R32PficIprior24Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR24 to value 0"]
impl crate::Resettable for R32PficIprior24Spec {}
}
#[doc = "R32_PFIC_IPRIOR25 (rw) register accessor: Interrupt Priority configuration Register 25\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior25`] module"]
#[doc(alias = "R32_PFIC_IPRIOR25")]
pub type R32PficIprior25 = crate::Reg<r32_pfic_iprior25::R32PficIprior25Spec>;
#[doc = "Interrupt Priority configuration Register 25"]
pub mod r32_pfic_iprior25 {
#[doc = "Register `R32_PFIC_IPRIOR25` reader"]
pub type R = crate::R<R32PficIprior25Spec>;
#[doc = "Register `R32_PFIC_IPRIOR25` writer"]
pub type W = crate::W<R32PficIprior25Spec>;
#[doc = "Field `IPRIOR25` reader - RW,Interrupt priority for number 100-103"]
pub type Iprior25R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR25` writer - RW,Interrupt priority for number 100-103"]
pub type Iprior25W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 100-103"]
#[inline(always)]
pub fn iprior25(&self) -> Iprior25R {
Iprior25R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 100-103"]
#[inline(always)]
pub fn iprior25(&mut self) -> Iprior25W<R32PficIprior25Spec> {
Iprior25W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 25\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior25Spec;
impl crate::RegisterSpec for R32PficIprior25Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior25::R`](R) reader structure"]
impl crate::Readable for R32PficIprior25Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior25::W`](W) writer structure"]
impl crate::Writable for R32PficIprior25Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR25 to value 0"]
impl crate::Resettable for R32PficIprior25Spec {}
}
#[doc = "R32_PFIC_IPRIOR26 (rw) register accessor: Interrupt Priority configuration Register 26\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior26`] module"]
#[doc(alias = "R32_PFIC_IPRIOR26")]
pub type R32PficIprior26 = crate::Reg<r32_pfic_iprior26::R32PficIprior26Spec>;
#[doc = "Interrupt Priority configuration Register 26"]
pub mod r32_pfic_iprior26 {
#[doc = "Register `R32_PFIC_IPRIOR26` reader"]
pub type R = crate::R<R32PficIprior26Spec>;
#[doc = "Register `R32_PFIC_IPRIOR26` writer"]
pub type W = crate::W<R32PficIprior26Spec>;
#[doc = "Field `IPRIOR26` reader - RW,Interrupt priority for number 104-107"]
pub type Iprior26R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR26` writer - RW,Interrupt priority for number 104-107"]
pub type Iprior26W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 104-107"]
#[inline(always)]
pub fn iprior26(&self) -> Iprior26R {
Iprior26R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 104-107"]
#[inline(always)]
pub fn iprior26(&mut self) -> Iprior26W<R32PficIprior26Spec> {
Iprior26W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 26\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior26Spec;
impl crate::RegisterSpec for R32PficIprior26Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior26::R`](R) reader structure"]
impl crate::Readable for R32PficIprior26Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior26::W`](W) writer structure"]
impl crate::Writable for R32PficIprior26Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR26 to value 0"]
impl crate::Resettable for R32PficIprior26Spec {}
}
#[doc = "R32_PFIC_IPRIOR27 (rw) register accessor: Interrupt Priority configuration Register 27\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior27`] module"]
#[doc(alias = "R32_PFIC_IPRIOR27")]
pub type R32PficIprior27 = crate::Reg<r32_pfic_iprior27::R32PficIprior27Spec>;
#[doc = "Interrupt Priority configuration Register 27"]
pub mod r32_pfic_iprior27 {
#[doc = "Register `R32_PFIC_IPRIOR27` reader"]
pub type R = crate::R<R32PficIprior27Spec>;
#[doc = "Register `R32_PFIC_IPRIOR27` writer"]
pub type W = crate::W<R32PficIprior27Spec>;
#[doc = "Field `IPRIOR27` reader - RW,Interrupt priority for number 108-111"]
pub type Iprior27R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR27` writer - RW,Interrupt priority for number 108-111"]
pub type Iprior27W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 108-111"]
#[inline(always)]
pub fn iprior27(&self) -> Iprior27R {
Iprior27R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 108-111"]
#[inline(always)]
pub fn iprior27(&mut self) -> Iprior27W<R32PficIprior27Spec> {
Iprior27W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 27\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior27Spec;
impl crate::RegisterSpec for R32PficIprior27Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior27::R`](R) reader structure"]
impl crate::Readable for R32PficIprior27Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior27::W`](W) writer structure"]
impl crate::Writable for R32PficIprior27Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR27 to value 0"]
impl crate::Resettable for R32PficIprior27Spec {}
}
#[doc = "R32_PFIC_IPRIOR28 (rw) register accessor: Interrupt Priority configuration Register 28\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior28`] module"]
#[doc(alias = "R32_PFIC_IPRIOR28")]
pub type R32PficIprior28 = crate::Reg<r32_pfic_iprior28::R32PficIprior28Spec>;
#[doc = "Interrupt Priority configuration Register 28"]
pub mod r32_pfic_iprior28 {
#[doc = "Register `R32_PFIC_IPRIOR28` reader"]
pub type R = crate::R<R32PficIprior28Spec>;
#[doc = "Register `R32_PFIC_IPRIOR28` writer"]
pub type W = crate::W<R32PficIprior28Spec>;
#[doc = "Field `IPRIOR28` reader - RW,Interrupt priority for number 112-115"]
pub type Iprior28R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR28` writer - RW,Interrupt priority for number 112-115"]
pub type Iprior28W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 112-115"]
#[inline(always)]
pub fn iprior28(&self) -> Iprior28R {
Iprior28R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 112-115"]
#[inline(always)]
pub fn iprior28(&mut self) -> Iprior28W<R32PficIprior28Spec> {
Iprior28W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 28\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior28Spec;
impl crate::RegisterSpec for R32PficIprior28Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior28::R`](R) reader structure"]
impl crate::Readable for R32PficIprior28Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior28::W`](W) writer structure"]
impl crate::Writable for R32PficIprior28Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR28 to value 0"]
impl crate::Resettable for R32PficIprior28Spec {}
}
#[doc = "R32_PFIC_IPRIOR29 (rw) register accessor: Interrupt Priority configuration Register 29\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior29`] module"]
#[doc(alias = "R32_PFIC_IPRIOR29")]
pub type R32PficIprior29 = crate::Reg<r32_pfic_iprior29::R32PficIprior29Spec>;
#[doc = "Interrupt Priority configuration Register 29"]
pub mod r32_pfic_iprior29 {
#[doc = "Register `R32_PFIC_IPRIOR29` reader"]
pub type R = crate::R<R32PficIprior29Spec>;
#[doc = "Register `R32_PFIC_IPRIOR29` writer"]
pub type W = crate::W<R32PficIprior29Spec>;
#[doc = "Field `IPRIOR29` reader - RW,Interrupt priority for number 116-119"]
pub type Iprior29R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR29` writer - RW,Interrupt priority for number 116-119"]
pub type Iprior29W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 116-119"]
#[inline(always)]
pub fn iprior29(&self) -> Iprior29R {
Iprior29R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 116-119"]
#[inline(always)]
pub fn iprior29(&mut self) -> Iprior29W<R32PficIprior29Spec> {
Iprior29W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 29\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior29Spec;
impl crate::RegisterSpec for R32PficIprior29Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior29::R`](R) reader structure"]
impl crate::Readable for R32PficIprior29Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior29::W`](W) writer structure"]
impl crate::Writable for R32PficIprior29Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR29 to value 0"]
impl crate::Resettable for R32PficIprior29Spec {}
}
#[doc = "R32_PFIC_IPRIOR30 (rw) register accessor: Interrupt Priority configuration Register 30\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior30`] module"]
#[doc(alias = "R32_PFIC_IPRIOR30")]
pub type R32PficIprior30 = crate::Reg<r32_pfic_iprior30::R32PficIprior30Spec>;
#[doc = "Interrupt Priority configuration Register 30"]
pub mod r32_pfic_iprior30 {
#[doc = "Register `R32_PFIC_IPRIOR30` reader"]
pub type R = crate::R<R32PficIprior30Spec>;
#[doc = "Register `R32_PFIC_IPRIOR30` writer"]
pub type W = crate::W<R32PficIprior30Spec>;
#[doc = "Field `IPRIOR30` reader - RW,Interrupt priority for number 120-123"]
pub type Iprior30R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR30` writer - RW,Interrupt priority for number 120-123"]
pub type Iprior30W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 120-123"]
#[inline(always)]
pub fn iprior30(&self) -> Iprior30R {
Iprior30R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 120-123"]
#[inline(always)]
pub fn iprior30(&mut self) -> Iprior30W<R32PficIprior30Spec> {
Iprior30W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 30\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior30Spec;
impl crate::RegisterSpec for R32PficIprior30Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior30::R`](R) reader structure"]
impl crate::Readable for R32PficIprior30Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior30::W`](W) writer structure"]
impl crate::Writable for R32PficIprior30Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR30 to value 0"]
impl crate::Resettable for R32PficIprior30Spec {}
}
#[doc = "R32_PFIC_IPRIOR31 (rw) register accessor: Interrupt Priority configuration Register 31\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior31`] module"]
#[doc(alias = "R32_PFIC_IPRIOR31")]
pub type R32PficIprior31 = crate::Reg<r32_pfic_iprior31::R32PficIprior31Spec>;
#[doc = "Interrupt Priority configuration Register 31"]
pub mod r32_pfic_iprior31 {
#[doc = "Register `R32_PFIC_IPRIOR31` reader"]
pub type R = crate::R<R32PficIprior31Spec>;
#[doc = "Register `R32_PFIC_IPRIOR31` writer"]
pub type W = crate::W<R32PficIprior31Spec>;
#[doc = "Field `IPRIOR31` reader - RW,Interrupt priority for number 124-127"]
pub type Iprior31R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR31` writer - RW,Interrupt priority for number 124-127"]
pub type Iprior31W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 124-127"]
#[inline(always)]
pub fn iprior31(&self) -> Iprior31R {
Iprior31R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 124-127"]
#[inline(always)]
pub fn iprior31(&mut self) -> Iprior31W<R32PficIprior31Spec> {
Iprior31W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 31\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior31Spec;
impl crate::RegisterSpec for R32PficIprior31Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior31::R`](R) reader structure"]
impl crate::Readable for R32PficIprior31Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior31::W`](W) writer structure"]
impl crate::Writable for R32PficIprior31Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR31 to value 0"]
impl crate::Resettable for R32PficIprior31Spec {}
}
#[doc = "R32_PFIC_IPRIOR32 (rw) register accessor: Interrupt Priority configuration Register 32\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior32::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior32::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior32`] module"]
#[doc(alias = "R32_PFIC_IPRIOR32")]
pub type R32PficIprior32 = crate::Reg<r32_pfic_iprior32::R32PficIprior32Spec>;
#[doc = "Interrupt Priority configuration Register 32"]
pub mod r32_pfic_iprior32 {
#[doc = "Register `R32_PFIC_IPRIOR32` reader"]
pub type R = crate::R<R32PficIprior32Spec>;
#[doc = "Register `R32_PFIC_IPRIOR32` writer"]
pub type W = crate::W<R32PficIprior32Spec>;
#[doc = "Field `IPRIOR32` reader - RW,Interrupt priority for number 128-131"]
pub type Iprior32R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR32` writer - RW,Interrupt priority for number 128-131"]
pub type Iprior32W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 128-131"]
#[inline(always)]
pub fn iprior32(&self) -> Iprior32R {
Iprior32R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 128-131"]
#[inline(always)]
pub fn iprior32(&mut self) -> Iprior32W<R32PficIprior32Spec> {
Iprior32W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 32\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior32::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior32::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior32Spec;
impl crate::RegisterSpec for R32PficIprior32Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior32::R`](R) reader structure"]
impl crate::Readable for R32PficIprior32Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior32::W`](W) writer structure"]
impl crate::Writable for R32PficIprior32Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR32 to value 0"]
impl crate::Resettable for R32PficIprior32Spec {}
}
#[doc = "R32_PFIC_IPRIOR33 (rw) register accessor: Interrupt Priority configuration Register 33\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior33::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior33::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior33`] module"]
#[doc(alias = "R32_PFIC_IPRIOR33")]
pub type R32PficIprior33 = crate::Reg<r32_pfic_iprior33::R32PficIprior33Spec>;
#[doc = "Interrupt Priority configuration Register 33"]
pub mod r32_pfic_iprior33 {
#[doc = "Register `R32_PFIC_IPRIOR33` reader"]
pub type R = crate::R<R32PficIprior33Spec>;
#[doc = "Register `R32_PFIC_IPRIOR33` writer"]
pub type W = crate::W<R32PficIprior33Spec>;
#[doc = "Field `IPRIOR33` reader - RW,Interrupt priority for number 132-135"]
pub type Iprior33R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR33` writer - RW,Interrupt priority for number 132-135"]
pub type Iprior33W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 132-135"]
#[inline(always)]
pub fn iprior33(&self) -> Iprior33R {
Iprior33R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 132-135"]
#[inline(always)]
pub fn iprior33(&mut self) -> Iprior33W<R32PficIprior33Spec> {
Iprior33W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 33\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior33::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior33::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior33Spec;
impl crate::RegisterSpec for R32PficIprior33Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior33::R`](R) reader structure"]
impl crate::Readable for R32PficIprior33Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior33::W`](W) writer structure"]
impl crate::Writable for R32PficIprior33Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR33 to value 0"]
impl crate::Resettable for R32PficIprior33Spec {}
}
#[doc = "R32_PFIC_IPRIOR34 (rw) register accessor: Interrupt Priority configuration Register 34\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior34::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior34::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior34`] module"]
#[doc(alias = "R32_PFIC_IPRIOR34")]
pub type R32PficIprior34 = crate::Reg<r32_pfic_iprior34::R32PficIprior34Spec>;
#[doc = "Interrupt Priority configuration Register 34"]
pub mod r32_pfic_iprior34 {
#[doc = "Register `R32_PFIC_IPRIOR34` reader"]
pub type R = crate::R<R32PficIprior34Spec>;
#[doc = "Register `R32_PFIC_IPRIOR34` writer"]
pub type W = crate::W<R32PficIprior34Spec>;
#[doc = "Field `IPRIOR34` reader - RW,Interrupt priority for number 136-139"]
pub type Iprior34R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR34` writer - RW,Interrupt priority for number 136-139"]
pub type Iprior34W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 136-139"]
#[inline(always)]
pub fn iprior34(&self) -> Iprior34R {
Iprior34R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 136-139"]
#[inline(always)]
pub fn iprior34(&mut self) -> Iprior34W<R32PficIprior34Spec> {
Iprior34W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 34\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior34::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior34::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior34Spec;
impl crate::RegisterSpec for R32PficIprior34Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior34::R`](R) reader structure"]
impl crate::Readable for R32PficIprior34Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior34::W`](W) writer structure"]
impl crate::Writable for R32PficIprior34Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR34 to value 0"]
impl crate::Resettable for R32PficIprior34Spec {}
}
#[doc = "R32_PFIC_IPRIOR35 (rw) register accessor: Interrupt Priority configuration Register 35\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior35::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior35::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior35`] module"]
#[doc(alias = "R32_PFIC_IPRIOR35")]
pub type R32PficIprior35 = crate::Reg<r32_pfic_iprior35::R32PficIprior35Spec>;
#[doc = "Interrupt Priority configuration Register 35"]
pub mod r32_pfic_iprior35 {
#[doc = "Register `R32_PFIC_IPRIOR35` reader"]
pub type R = crate::R<R32PficIprior35Spec>;
#[doc = "Register `R32_PFIC_IPRIOR35` writer"]
pub type W = crate::W<R32PficIprior35Spec>;
#[doc = "Field `IPRIOR35` reader - RW,Interrupt priority for number 140-143"]
pub type Iprior35R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR35` writer - RW,Interrupt priority for number 140-143"]
pub type Iprior35W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 140-143"]
#[inline(always)]
pub fn iprior35(&self) -> Iprior35R {
Iprior35R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 140-143"]
#[inline(always)]
pub fn iprior35(&mut self) -> Iprior35W<R32PficIprior35Spec> {
Iprior35W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 35\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior35::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior35::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior35Spec;
impl crate::RegisterSpec for R32PficIprior35Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior35::R`](R) reader structure"]
impl crate::Readable for R32PficIprior35Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior35::W`](W) writer structure"]
impl crate::Writable for R32PficIprior35Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR35 to value 0"]
impl crate::Resettable for R32PficIprior35Spec {}
}
#[doc = "R32_PFIC_IPRIOR36 (rw) register accessor: Interrupt Priority configuration Register 36\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior36::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior36::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior36`] module"]
#[doc(alias = "R32_PFIC_IPRIOR36")]
pub type R32PficIprior36 = crate::Reg<r32_pfic_iprior36::R32PficIprior36Spec>;
#[doc = "Interrupt Priority configuration Register 36"]
pub mod r32_pfic_iprior36 {
#[doc = "Register `R32_PFIC_IPRIOR36` reader"]
pub type R = crate::R<R32PficIprior36Spec>;
#[doc = "Register `R32_PFIC_IPRIOR36` writer"]
pub type W = crate::W<R32PficIprior36Spec>;
#[doc = "Field `IPRIOR36` reader - RW,Interrupt priority for number 144-147"]
pub type Iprior36R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR36` writer - RW,Interrupt priority for number 144-147"]
pub type Iprior36W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 144-147"]
#[inline(always)]
pub fn iprior36(&self) -> Iprior36R {
Iprior36R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 144-147"]
#[inline(always)]
pub fn iprior36(&mut self) -> Iprior36W<R32PficIprior36Spec> {
Iprior36W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 36\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior36::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior36::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior36Spec;
impl crate::RegisterSpec for R32PficIprior36Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior36::R`](R) reader structure"]
impl crate::Readable for R32PficIprior36Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior36::W`](W) writer structure"]
impl crate::Writable for R32PficIprior36Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR36 to value 0"]
impl crate::Resettable for R32PficIprior36Spec {}
}
#[doc = "R32_PFIC_IPRIOR37 (rw) register accessor: Interrupt Priority configuration Register 37\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior37::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior37::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior37`] module"]
#[doc(alias = "R32_PFIC_IPRIOR37")]
pub type R32PficIprior37 = crate::Reg<r32_pfic_iprior37::R32PficIprior37Spec>;
#[doc = "Interrupt Priority configuration Register 37"]
pub mod r32_pfic_iprior37 {
#[doc = "Register `R32_PFIC_IPRIOR37` reader"]
pub type R = crate::R<R32PficIprior37Spec>;
#[doc = "Register `R32_PFIC_IPRIOR37` writer"]
pub type W = crate::W<R32PficIprior37Spec>;
#[doc = "Field `IPRIOR37` reader - RW,Interrupt priority for number 148-151"]
pub type Iprior37R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR37` writer - RW,Interrupt priority for number 148-151"]
pub type Iprior37W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 148-151"]
#[inline(always)]
pub fn iprior37(&self) -> Iprior37R {
Iprior37R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 148-151"]
#[inline(always)]
pub fn iprior37(&mut self) -> Iprior37W<R32PficIprior37Spec> {
Iprior37W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 37\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior37::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior37::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior37Spec;
impl crate::RegisterSpec for R32PficIprior37Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior37::R`](R) reader structure"]
impl crate::Readable for R32PficIprior37Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior37::W`](W) writer structure"]
impl crate::Writable for R32PficIprior37Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR37 to value 0"]
impl crate::Resettable for R32PficIprior37Spec {}
}
#[doc = "R32_PFIC_IPRIOR38 (rw) register accessor: Interrupt Priority configuration Register 38\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior38::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior38::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior38`] module"]
#[doc(alias = "R32_PFIC_IPRIOR38")]
pub type R32PficIprior38 = crate::Reg<r32_pfic_iprior38::R32PficIprior38Spec>;
#[doc = "Interrupt Priority configuration Register 38"]
pub mod r32_pfic_iprior38 {
#[doc = "Register `R32_PFIC_IPRIOR38` reader"]
pub type R = crate::R<R32PficIprior38Spec>;
#[doc = "Register `R32_PFIC_IPRIOR38` writer"]
pub type W = crate::W<R32PficIprior38Spec>;
#[doc = "Field `IPRIOR38` reader - RW,Interrupt priority for number 152-155"]
pub type Iprior38R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR38` writer - RW,Interrupt priority for number 152-155"]
pub type Iprior38W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 152-155"]
#[inline(always)]
pub fn iprior38(&self) -> Iprior38R {
Iprior38R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 152-155"]
#[inline(always)]
pub fn iprior38(&mut self) -> Iprior38W<R32PficIprior38Spec> {
Iprior38W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 38\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior38::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior38::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior38Spec;
impl crate::RegisterSpec for R32PficIprior38Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior38::R`](R) reader structure"]
impl crate::Readable for R32PficIprior38Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior38::W`](W) writer structure"]
impl crate::Writable for R32PficIprior38Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR38 to value 0"]
impl crate::Resettable for R32PficIprior38Spec {}
}
#[doc = "R32_PFIC_IPRIOR39 (rw) register accessor: Interrupt Priority configuration Register 39\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior39::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior39::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior39`] module"]
#[doc(alias = "R32_PFIC_IPRIOR39")]
pub type R32PficIprior39 = crate::Reg<r32_pfic_iprior39::R32PficIprior39Spec>;
#[doc = "Interrupt Priority configuration Register 39"]
pub mod r32_pfic_iprior39 {
#[doc = "Register `R32_PFIC_IPRIOR39` reader"]
pub type R = crate::R<R32PficIprior39Spec>;
#[doc = "Register `R32_PFIC_IPRIOR39` writer"]
pub type W = crate::W<R32PficIprior39Spec>;
#[doc = "Field `IPRIOR39` reader - RW,Interrupt priority for number 156-159"]
pub type Iprior39R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR39` writer - RW,Interrupt priority for number 156-159"]
pub type Iprior39W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 156-159"]
#[inline(always)]
pub fn iprior39(&self) -> Iprior39R {
Iprior39R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 156-159"]
#[inline(always)]
pub fn iprior39(&mut self) -> Iprior39W<R32PficIprior39Spec> {
Iprior39W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 39\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior39::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior39::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior39Spec;
impl crate::RegisterSpec for R32PficIprior39Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior39::R`](R) reader structure"]
impl crate::Readable for R32PficIprior39Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior39::W`](W) writer structure"]
impl crate::Writable for R32PficIprior39Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR39 to value 0"]
impl crate::Resettable for R32PficIprior39Spec {}
}
#[doc = "R32_PFIC_IPRIOR40 (rw) register accessor: Interrupt Priority configuration Register 40\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior40::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior40::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior40`] module"]
#[doc(alias = "R32_PFIC_IPRIOR40")]
pub type R32PficIprior40 = crate::Reg<r32_pfic_iprior40::R32PficIprior40Spec>;
#[doc = "Interrupt Priority configuration Register 40"]
pub mod r32_pfic_iprior40 {
#[doc = "Register `R32_PFIC_IPRIOR40` reader"]
pub type R = crate::R<R32PficIprior40Spec>;
#[doc = "Register `R32_PFIC_IPRIOR40` writer"]
pub type W = crate::W<R32PficIprior40Spec>;
#[doc = "Field `IPRIOR40` reader - RW,Interrupt priority for number 160-163"]
pub type Iprior40R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR40` writer - RW,Interrupt priority for number 160-163"]
pub type Iprior40W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 160-163"]
#[inline(always)]
pub fn iprior40(&self) -> Iprior40R {
Iprior40R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 160-163"]
#[inline(always)]
pub fn iprior40(&mut self) -> Iprior40W<R32PficIprior40Spec> {
Iprior40W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 40\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior40::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior40::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior40Spec;
impl crate::RegisterSpec for R32PficIprior40Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior40::R`](R) reader structure"]
impl crate::Readable for R32PficIprior40Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior40::W`](W) writer structure"]
impl crate::Writable for R32PficIprior40Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR40 to value 0"]
impl crate::Resettable for R32PficIprior40Spec {}
}
#[doc = "R32_PFIC_IPRIOR41 (rw) register accessor: Interrupt Priority configuration Register 41\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior41::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior41::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior41`] module"]
#[doc(alias = "R32_PFIC_IPRIOR41")]
pub type R32PficIprior41 = crate::Reg<r32_pfic_iprior41::R32PficIprior41Spec>;
#[doc = "Interrupt Priority configuration Register 41"]
pub mod r32_pfic_iprior41 {
#[doc = "Register `R32_PFIC_IPRIOR41` reader"]
pub type R = crate::R<R32PficIprior41Spec>;
#[doc = "Register `R32_PFIC_IPRIOR41` writer"]
pub type W = crate::W<R32PficIprior41Spec>;
#[doc = "Field `IPRIOR41` reader - RW,Interrupt priority for number 164-167"]
pub type Iprior41R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR41` writer - RW,Interrupt priority for number 164-167"]
pub type Iprior41W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 164-167"]
#[inline(always)]
pub fn iprior41(&self) -> Iprior41R {
Iprior41R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 164-167"]
#[inline(always)]
pub fn iprior41(&mut self) -> Iprior41W<R32PficIprior41Spec> {
Iprior41W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 41\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior41::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior41::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior41Spec;
impl crate::RegisterSpec for R32PficIprior41Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior41::R`](R) reader structure"]
impl crate::Readable for R32PficIprior41Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior41::W`](W) writer structure"]
impl crate::Writable for R32PficIprior41Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR41 to value 0"]
impl crate::Resettable for R32PficIprior41Spec {}
}
#[doc = "R32_PFIC_IPRIOR42 (rw) register accessor: Interrupt Priority configuration Register 42\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior42::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior42::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior42`] module"]
#[doc(alias = "R32_PFIC_IPRIOR42")]
pub type R32PficIprior42 = crate::Reg<r32_pfic_iprior42::R32PficIprior42Spec>;
#[doc = "Interrupt Priority configuration Register 42"]
pub mod r32_pfic_iprior42 {
#[doc = "Register `R32_PFIC_IPRIOR42` reader"]
pub type R = crate::R<R32PficIprior42Spec>;
#[doc = "Register `R32_PFIC_IPRIOR42` writer"]
pub type W = crate::W<R32PficIprior42Spec>;
#[doc = "Field `IPRIOR42` reader - RW,Interrupt priority for number 168-171"]
pub type Iprior42R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR42` writer - RW,Interrupt priority for number 168-171"]
pub type Iprior42W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 168-171"]
#[inline(always)]
pub fn iprior42(&self) -> Iprior42R {
Iprior42R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 168-171"]
#[inline(always)]
pub fn iprior42(&mut self) -> Iprior42W<R32PficIprior42Spec> {
Iprior42W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 42\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior42::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior42::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior42Spec;
impl crate::RegisterSpec for R32PficIprior42Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior42::R`](R) reader structure"]
impl crate::Readable for R32PficIprior42Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior42::W`](W) writer structure"]
impl crate::Writable for R32PficIprior42Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR42 to value 0"]
impl crate::Resettable for R32PficIprior42Spec {}
}
#[doc = "R32_PFIC_IPRIOR43 (rw) register accessor: Interrupt Priority configuration Register 43\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior43::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior43::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior43`] module"]
#[doc(alias = "R32_PFIC_IPRIOR43")]
pub type R32PficIprior43 = crate::Reg<r32_pfic_iprior43::R32PficIprior43Spec>;
#[doc = "Interrupt Priority configuration Register 43"]
pub mod r32_pfic_iprior43 {
#[doc = "Register `R32_PFIC_IPRIOR43` reader"]
pub type R = crate::R<R32PficIprior43Spec>;
#[doc = "Register `R32_PFIC_IPRIOR43` writer"]
pub type W = crate::W<R32PficIprior43Spec>;
#[doc = "Field `IPRIOR43` reader - RW,Interrupt priority for number 172-175"]
pub type Iprior43R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR43` writer - RW,Interrupt priority for number 172-175"]
pub type Iprior43W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 172-175"]
#[inline(always)]
pub fn iprior43(&self) -> Iprior43R {
Iprior43R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 172-175"]
#[inline(always)]
pub fn iprior43(&mut self) -> Iprior43W<R32PficIprior43Spec> {
Iprior43W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 43\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior43::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior43::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior43Spec;
impl crate::RegisterSpec for R32PficIprior43Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior43::R`](R) reader structure"]
impl crate::Readable for R32PficIprior43Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior43::W`](W) writer structure"]
impl crate::Writable for R32PficIprior43Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR43 to value 0"]
impl crate::Resettable for R32PficIprior43Spec {}
}
#[doc = "R32_PFIC_IPRIOR44 (rw) register accessor: Interrupt Priority configuration Register 44\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior44::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior44::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior44`] module"]
#[doc(alias = "R32_PFIC_IPRIOR44")]
pub type R32PficIprior44 = crate::Reg<r32_pfic_iprior44::R32PficIprior44Spec>;
#[doc = "Interrupt Priority configuration Register 44"]
pub mod r32_pfic_iprior44 {
#[doc = "Register `R32_PFIC_IPRIOR44` reader"]
pub type R = crate::R<R32PficIprior44Spec>;
#[doc = "Register `R32_PFIC_IPRIOR44` writer"]
pub type W = crate::W<R32PficIprior44Spec>;
#[doc = "Field `IPRIOR44` reader - RW,Interrupt priority for number 176-179"]
pub type Iprior44R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR44` writer - RW,Interrupt priority for number 176-179"]
pub type Iprior44W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 176-179"]
#[inline(always)]
pub fn iprior44(&self) -> Iprior44R {
Iprior44R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 176-179"]
#[inline(always)]
pub fn iprior44(&mut self) -> Iprior44W<R32PficIprior44Spec> {
Iprior44W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 44\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior44::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior44::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior44Spec;
impl crate::RegisterSpec for R32PficIprior44Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior44::R`](R) reader structure"]
impl crate::Readable for R32PficIprior44Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior44::W`](W) writer structure"]
impl crate::Writable for R32PficIprior44Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR44 to value 0"]
impl crate::Resettable for R32PficIprior44Spec {}
}
#[doc = "R32_PFIC_IPRIOR45 (rw) register accessor: Interrupt Priority configuration Register 45\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior45::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior45::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior45`] module"]
#[doc(alias = "R32_PFIC_IPRIOR45")]
pub type R32PficIprior45 = crate::Reg<r32_pfic_iprior45::R32PficIprior45Spec>;
#[doc = "Interrupt Priority configuration Register 45"]
pub mod r32_pfic_iprior45 {
#[doc = "Register `R32_PFIC_IPRIOR45` reader"]
pub type R = crate::R<R32PficIprior45Spec>;
#[doc = "Register `R32_PFIC_IPRIOR45` writer"]
pub type W = crate::W<R32PficIprior45Spec>;
#[doc = "Field `IPRIOR45` reader - RW,Interrupt priority for number 180-183"]
pub type Iprior45R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR45` writer - RW,Interrupt priority for number 180-183"]
pub type Iprior45W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 180-183"]
#[inline(always)]
pub fn iprior45(&self) -> Iprior45R {
Iprior45R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 180-183"]
#[inline(always)]
pub fn iprior45(&mut self) -> Iprior45W<R32PficIprior45Spec> {
Iprior45W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 45\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior45::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior45::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior45Spec;
impl crate::RegisterSpec for R32PficIprior45Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior45::R`](R) reader structure"]
impl crate::Readable for R32PficIprior45Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior45::W`](W) writer structure"]
impl crate::Writable for R32PficIprior45Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR45 to value 0"]
impl crate::Resettable for R32PficIprior45Spec {}
}
#[doc = "R32_PFIC_IPRIOR46 (rw) register accessor: Interrupt Priority configuration Register 46\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior46::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior46::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior46`] module"]
#[doc(alias = "R32_PFIC_IPRIOR46")]
pub type R32PficIprior46 = crate::Reg<r32_pfic_iprior46::R32PficIprior46Spec>;
#[doc = "Interrupt Priority configuration Register 46"]
pub mod r32_pfic_iprior46 {
#[doc = "Register `R32_PFIC_IPRIOR46` reader"]
pub type R = crate::R<R32PficIprior46Spec>;
#[doc = "Register `R32_PFIC_IPRIOR46` writer"]
pub type W = crate::W<R32PficIprior46Spec>;
#[doc = "Field `IPRIOR46` reader - RW,Interrupt priority for number 184-187"]
pub type Iprior46R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR46` writer - RW,Interrupt priority for number 184-187"]
pub type Iprior46W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 184-187"]
#[inline(always)]
pub fn iprior46(&self) -> Iprior46R {
Iprior46R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 184-187"]
#[inline(always)]
pub fn iprior46(&mut self) -> Iprior46W<R32PficIprior46Spec> {
Iprior46W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 46\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior46::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior46::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior46Spec;
impl crate::RegisterSpec for R32PficIprior46Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior46::R`](R) reader structure"]
impl crate::Readable for R32PficIprior46Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior46::W`](W) writer structure"]
impl crate::Writable for R32PficIprior46Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR46 to value 0"]
impl crate::Resettable for R32PficIprior46Spec {}
}
#[doc = "R32_PFIC_IPRIOR47 (rw) register accessor: Interrupt Priority configuration Register 47\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior47::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior47::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior47`] module"]
#[doc(alias = "R32_PFIC_IPRIOR47")]
pub type R32PficIprior47 = crate::Reg<r32_pfic_iprior47::R32PficIprior47Spec>;
#[doc = "Interrupt Priority configuration Register 47"]
pub mod r32_pfic_iprior47 {
#[doc = "Register `R32_PFIC_IPRIOR47` reader"]
pub type R = crate::R<R32PficIprior47Spec>;
#[doc = "Register `R32_PFIC_IPRIOR47` writer"]
pub type W = crate::W<R32PficIprior47Spec>;
#[doc = "Field `IPRIOR47` reader - RW,Interrupt priority for number 188-191"]
pub type Iprior47R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR47` writer - RW,Interrupt priority for number 188-191"]
pub type Iprior47W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 188-191"]
#[inline(always)]
pub fn iprior47(&self) -> Iprior47R {
Iprior47R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 188-191"]
#[inline(always)]
pub fn iprior47(&mut self) -> Iprior47W<R32PficIprior47Spec> {
Iprior47W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 47\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior47::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior47::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior47Spec;
impl crate::RegisterSpec for R32PficIprior47Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior47::R`](R) reader structure"]
impl crate::Readable for R32PficIprior47Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior47::W`](W) writer structure"]
impl crate::Writable for R32PficIprior47Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR47 to value 0"]
impl crate::Resettable for R32PficIprior47Spec {}
}
#[doc = "R32_PFIC_IPRIOR48 (rw) register accessor: Interrupt Priority configuration Register 48\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior48::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior48::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior48`] module"]
#[doc(alias = "R32_PFIC_IPRIOR48")]
pub type R32PficIprior48 = crate::Reg<r32_pfic_iprior48::R32PficIprior48Spec>;
#[doc = "Interrupt Priority configuration Register 48"]
pub mod r32_pfic_iprior48 {
#[doc = "Register `R32_PFIC_IPRIOR48` reader"]
pub type R = crate::R<R32PficIprior48Spec>;
#[doc = "Register `R32_PFIC_IPRIOR48` writer"]
pub type W = crate::W<R32PficIprior48Spec>;
#[doc = "Field `IPRIOR48` reader - RW,Interrupt priority for number 192-195"]
pub type Iprior48R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR48` writer - RW,Interrupt priority for number 192-195"]
pub type Iprior48W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 192-195"]
#[inline(always)]
pub fn iprior48(&self) -> Iprior48R {
Iprior48R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 192-195"]
#[inline(always)]
pub fn iprior48(&mut self) -> Iprior48W<R32PficIprior48Spec> {
Iprior48W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 48\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior48::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior48::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior48Spec;
impl crate::RegisterSpec for R32PficIprior48Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior48::R`](R) reader structure"]
impl crate::Readable for R32PficIprior48Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior48::W`](W) writer structure"]
impl crate::Writable for R32PficIprior48Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR48 to value 0"]
impl crate::Resettable for R32PficIprior48Spec {}
}
#[doc = "R32_PFIC_IPRIOR49 (rw) register accessor: Interrupt Priority configuration Register 49\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior49::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior49::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior49`] module"]
#[doc(alias = "R32_PFIC_IPRIOR49")]
pub type R32PficIprior49 = crate::Reg<r32_pfic_iprior49::R32PficIprior49Spec>;
#[doc = "Interrupt Priority configuration Register 49"]
pub mod r32_pfic_iprior49 {
#[doc = "Register `R32_PFIC_IPRIOR49` reader"]
pub type R = crate::R<R32PficIprior49Spec>;
#[doc = "Register `R32_PFIC_IPRIOR49` writer"]
pub type W = crate::W<R32PficIprior49Spec>;
#[doc = "Field `IPRIOR49` reader - RW,Interrupt priority for number 196-199"]
pub type Iprior49R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR49` writer - RW,Interrupt priority for number 196-199"]
pub type Iprior49W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 196-199"]
#[inline(always)]
pub fn iprior49(&self) -> Iprior49R {
Iprior49R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 196-199"]
#[inline(always)]
pub fn iprior49(&mut self) -> Iprior49W<R32PficIprior49Spec> {
Iprior49W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 49\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior49::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior49::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior49Spec;
impl crate::RegisterSpec for R32PficIprior49Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior49::R`](R) reader structure"]
impl crate::Readable for R32PficIprior49Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior49::W`](W) writer structure"]
impl crate::Writable for R32PficIprior49Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR49 to value 0"]
impl crate::Resettable for R32PficIprior49Spec {}
}
#[doc = "R32_PFIC_IPRIOR50 (rw) register accessor: Interrupt Priority configuration Register 50\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior50::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior50::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior50`] module"]
#[doc(alias = "R32_PFIC_IPRIOR50")]
pub type R32PficIprior50 = crate::Reg<r32_pfic_iprior50::R32PficIprior50Spec>;
#[doc = "Interrupt Priority configuration Register 50"]
pub mod r32_pfic_iprior50 {
#[doc = "Register `R32_PFIC_IPRIOR50` reader"]
pub type R = crate::R<R32PficIprior50Spec>;
#[doc = "Register `R32_PFIC_IPRIOR50` writer"]
pub type W = crate::W<R32PficIprior50Spec>;
#[doc = "Field `IPRIOR50` reader - RW,Interrupt priority for number 200-203"]
pub type Iprior50R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR50` writer - RW,Interrupt priority for number 200-203"]
pub type Iprior50W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 200-203"]
#[inline(always)]
pub fn iprior50(&self) -> Iprior50R {
Iprior50R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 200-203"]
#[inline(always)]
pub fn iprior50(&mut self) -> Iprior50W<R32PficIprior50Spec> {
Iprior50W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 50\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior50::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior50::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior50Spec;
impl crate::RegisterSpec for R32PficIprior50Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior50::R`](R) reader structure"]
impl crate::Readable for R32PficIprior50Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior50::W`](W) writer structure"]
impl crate::Writable for R32PficIprior50Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR50 to value 0"]
impl crate::Resettable for R32PficIprior50Spec {}
}
#[doc = "R32_PFIC_IPRIOR51 (rw) register accessor: Interrupt Priority configuration Register 51\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior51::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior51::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior51`] module"]
#[doc(alias = "R32_PFIC_IPRIOR51")]
pub type R32PficIprior51 = crate::Reg<r32_pfic_iprior51::R32PficIprior51Spec>;
#[doc = "Interrupt Priority configuration Register 51"]
pub mod r32_pfic_iprior51 {
#[doc = "Register `R32_PFIC_IPRIOR51` reader"]
pub type R = crate::R<R32PficIprior51Spec>;
#[doc = "Register `R32_PFIC_IPRIOR51` writer"]
pub type W = crate::W<R32PficIprior51Spec>;
#[doc = "Field `IPRIOR51` reader - RW,Interrupt priority for number 204-207"]
pub type Iprior51R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR51` writer - RW,Interrupt priority for number 204-207"]
pub type Iprior51W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 204-207"]
#[inline(always)]
pub fn iprior51(&self) -> Iprior51R {
Iprior51R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 204-207"]
#[inline(always)]
pub fn iprior51(&mut self) -> Iprior51W<R32PficIprior51Spec> {
Iprior51W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 51\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior51::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior51::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior51Spec;
impl crate::RegisterSpec for R32PficIprior51Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior51::R`](R) reader structure"]
impl crate::Readable for R32PficIprior51Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior51::W`](W) writer structure"]
impl crate::Writable for R32PficIprior51Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR51 to value 0"]
impl crate::Resettable for R32PficIprior51Spec {}
}
#[doc = "R32_PFIC_IPRIOR52 (rw) register accessor: Interrupt Priority configuration Register 52\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior52::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior52::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior52`] module"]
#[doc(alias = "R32_PFIC_IPRIOR52")]
pub type R32PficIprior52 = crate::Reg<r32_pfic_iprior52::R32PficIprior52Spec>;
#[doc = "Interrupt Priority configuration Register 52"]
pub mod r32_pfic_iprior52 {
#[doc = "Register `R32_PFIC_IPRIOR52` reader"]
pub type R = crate::R<R32PficIprior52Spec>;
#[doc = "Register `R32_PFIC_IPRIOR52` writer"]
pub type W = crate::W<R32PficIprior52Spec>;
#[doc = "Field `IPRIOR52` reader - RW,Interrupt priority for number 208-211"]
pub type Iprior52R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR52` writer - RW,Interrupt priority for number 208-211"]
pub type Iprior52W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 208-211"]
#[inline(always)]
pub fn iprior52(&self) -> Iprior52R {
Iprior52R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 208-211"]
#[inline(always)]
pub fn iprior52(&mut self) -> Iprior52W<R32PficIprior52Spec> {
Iprior52W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 52\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior52::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior52::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior52Spec;
impl crate::RegisterSpec for R32PficIprior52Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior52::R`](R) reader structure"]
impl crate::Readable for R32PficIprior52Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior52::W`](W) writer structure"]
impl crate::Writable for R32PficIprior52Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR52 to value 0"]
impl crate::Resettable for R32PficIprior52Spec {}
}
#[doc = "R32_PFIC_IPRIOR53 (rw) register accessor: Interrupt Priority configuration Register 53\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior53::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior53::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior53`] module"]
#[doc(alias = "R32_PFIC_IPRIOR53")]
pub type R32PficIprior53 = crate::Reg<r32_pfic_iprior53::R32PficIprior53Spec>;
#[doc = "Interrupt Priority configuration Register 53"]
pub mod r32_pfic_iprior53 {
#[doc = "Register `R32_PFIC_IPRIOR53` reader"]
pub type R = crate::R<R32PficIprior53Spec>;
#[doc = "Register `R32_PFIC_IPRIOR53` writer"]
pub type W = crate::W<R32PficIprior53Spec>;
#[doc = "Field `IPRIOR53` reader - RW,Interrupt priority for number 212-215"]
pub type Iprior53R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR53` writer - RW,Interrupt priority for number 212-215"]
pub type Iprior53W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 212-215"]
#[inline(always)]
pub fn iprior53(&self) -> Iprior53R {
Iprior53R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 212-215"]
#[inline(always)]
pub fn iprior53(&mut self) -> Iprior53W<R32PficIprior53Spec> {
Iprior53W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 53\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior53::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior53::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior53Spec;
impl crate::RegisterSpec for R32PficIprior53Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior53::R`](R) reader structure"]
impl crate::Readable for R32PficIprior53Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior53::W`](W) writer structure"]
impl crate::Writable for R32PficIprior53Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR53 to value 0"]
impl crate::Resettable for R32PficIprior53Spec {}
}
#[doc = "R32_PFIC_IPRIOR54 (rw) register accessor: Interrupt Priority configuration Register 54\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior54::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior54::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior54`] module"]
#[doc(alias = "R32_PFIC_IPRIOR54")]
pub type R32PficIprior54 = crate::Reg<r32_pfic_iprior54::R32PficIprior54Spec>;
#[doc = "Interrupt Priority configuration Register 54"]
pub mod r32_pfic_iprior54 {
#[doc = "Register `R32_PFIC_IPRIOR54` reader"]
pub type R = crate::R<R32PficIprior54Spec>;
#[doc = "Register `R32_PFIC_IPRIOR54` writer"]
pub type W = crate::W<R32PficIprior54Spec>;
#[doc = "Field `IPRIOR54` reader - RW,Interrupt priority for number 216-219"]
pub type Iprior54R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR54` writer - RW,Interrupt priority for number 216-219"]
pub type Iprior54W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 216-219"]
#[inline(always)]
pub fn iprior54(&self) -> Iprior54R {
Iprior54R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 216-219"]
#[inline(always)]
pub fn iprior54(&mut self) -> Iprior54W<R32PficIprior54Spec> {
Iprior54W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 54\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior54::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior54::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior54Spec;
impl crate::RegisterSpec for R32PficIprior54Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior54::R`](R) reader structure"]
impl crate::Readable for R32PficIprior54Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior54::W`](W) writer structure"]
impl crate::Writable for R32PficIprior54Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR54 to value 0"]
impl crate::Resettable for R32PficIprior54Spec {}
}
#[doc = "R32_PFIC_IPRIOR55 (rw) register accessor: Interrupt Priority configuration Register 55\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior55::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior55::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior55`] module"]
#[doc(alias = "R32_PFIC_IPRIOR55")]
pub type R32PficIprior55 = crate::Reg<r32_pfic_iprior55::R32PficIprior55Spec>;
#[doc = "Interrupt Priority configuration Register 55"]
pub mod r32_pfic_iprior55 {
#[doc = "Register `R32_PFIC_IPRIOR55` reader"]
pub type R = crate::R<R32PficIprior55Spec>;
#[doc = "Register `R32_PFIC_IPRIOR55` writer"]
pub type W = crate::W<R32PficIprior55Spec>;
#[doc = "Field `IPRIOR55` reader - RW,Interrupt priority for number 220-223"]
pub type Iprior55R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR55` writer - RW,Interrupt priority for number 220-223"]
pub type Iprior55W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 220-223"]
#[inline(always)]
pub fn iprior55(&self) -> Iprior55R {
Iprior55R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 220-223"]
#[inline(always)]
pub fn iprior55(&mut self) -> Iprior55W<R32PficIprior55Spec> {
Iprior55W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 55\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior55::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior55::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior55Spec;
impl crate::RegisterSpec for R32PficIprior55Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior55::R`](R) reader structure"]
impl crate::Readable for R32PficIprior55Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior55::W`](W) writer structure"]
impl crate::Writable for R32PficIprior55Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR55 to value 0"]
impl crate::Resettable for R32PficIprior55Spec {}
}
#[doc = "R32_PFIC_IPRIOR56 (rw) register accessor: Interrupt Priority configuration Register 56\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior56::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior56::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior56`] module"]
#[doc(alias = "R32_PFIC_IPRIOR56")]
pub type R32PficIprior56 = crate::Reg<r32_pfic_iprior56::R32PficIprior56Spec>;
#[doc = "Interrupt Priority configuration Register 56"]
pub mod r32_pfic_iprior56 {
#[doc = "Register `R32_PFIC_IPRIOR56` reader"]
pub type R = crate::R<R32PficIprior56Spec>;
#[doc = "Register `R32_PFIC_IPRIOR56` writer"]
pub type W = crate::W<R32PficIprior56Spec>;
#[doc = "Field `IPRIOR56` reader - RW,Interrupt priority for number 224-227"]
pub type Iprior56R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR56` writer - RW,Interrupt priority for number 224-227"]
pub type Iprior56W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 224-227"]
#[inline(always)]
pub fn iprior56(&self) -> Iprior56R {
Iprior56R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 224-227"]
#[inline(always)]
pub fn iprior56(&mut self) -> Iprior56W<R32PficIprior56Spec> {
Iprior56W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 56\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior56::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior56::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior56Spec;
impl crate::RegisterSpec for R32PficIprior56Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior56::R`](R) reader structure"]
impl crate::Readable for R32PficIprior56Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior56::W`](W) writer structure"]
impl crate::Writable for R32PficIprior56Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR56 to value 0"]
impl crate::Resettable for R32PficIprior56Spec {}
}
#[doc = "R32_PFIC_IPRIOR57 (rw) register accessor: Interrupt Priority configuration Register 57\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior57::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior57::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior57`] module"]
#[doc(alias = "R32_PFIC_IPRIOR57")]
pub type R32PficIprior57 = crate::Reg<r32_pfic_iprior57::R32PficIprior57Spec>;
#[doc = "Interrupt Priority configuration Register 57"]
pub mod r32_pfic_iprior57 {
#[doc = "Register `R32_PFIC_IPRIOR57` reader"]
pub type R = crate::R<R32PficIprior57Spec>;
#[doc = "Register `R32_PFIC_IPRIOR57` writer"]
pub type W = crate::W<R32PficIprior57Spec>;
#[doc = "Field `IPRIOR57` reader - RW,Interrupt priority for number 228-231"]
pub type Iprior57R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR57` writer - RW,Interrupt priority for number 228-231"]
pub type Iprior57W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 228-231"]
#[inline(always)]
pub fn iprior57(&self) -> Iprior57R {
Iprior57R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 228-231"]
#[inline(always)]
pub fn iprior57(&mut self) -> Iprior57W<R32PficIprior57Spec> {
Iprior57W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 57\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior57::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior57::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior57Spec;
impl crate::RegisterSpec for R32PficIprior57Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior57::R`](R) reader structure"]
impl crate::Readable for R32PficIprior57Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior57::W`](W) writer structure"]
impl crate::Writable for R32PficIprior57Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR57 to value 0"]
impl crate::Resettable for R32PficIprior57Spec {}
}
#[doc = "R32_PFIC_IPRIOR58 (rw) register accessor: Interrupt Priority configuration Register 58\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior58::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior58::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior58`] module"]
#[doc(alias = "R32_PFIC_IPRIOR58")]
pub type R32PficIprior58 = crate::Reg<r32_pfic_iprior58::R32PficIprior58Spec>;
#[doc = "Interrupt Priority configuration Register 58"]
pub mod r32_pfic_iprior58 {
#[doc = "Register `R32_PFIC_IPRIOR58` reader"]
pub type R = crate::R<R32PficIprior58Spec>;
#[doc = "Register `R32_PFIC_IPRIOR58` writer"]
pub type W = crate::W<R32PficIprior58Spec>;
#[doc = "Field `IPRIOR58` reader - RW,Interrupt priority for number 232-235"]
pub type Iprior58R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR58` writer - RW,Interrupt priority for number 232-235"]
pub type Iprior58W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 232-235"]
#[inline(always)]
pub fn iprior58(&self) -> Iprior58R {
Iprior58R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 232-235"]
#[inline(always)]
pub fn iprior58(&mut self) -> Iprior58W<R32PficIprior58Spec> {
Iprior58W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 58\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior58::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior58::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior58Spec;
impl crate::RegisterSpec for R32PficIprior58Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior58::R`](R) reader structure"]
impl crate::Readable for R32PficIprior58Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior58::W`](W) writer structure"]
impl crate::Writable for R32PficIprior58Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR58 to value 0"]
impl crate::Resettable for R32PficIprior58Spec {}
}
#[doc = "R32_PFIC_IPRIOR59 (rw) register accessor: Interrupt Priority configuration Register 59\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior59::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior59::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior59`] module"]
#[doc(alias = "R32_PFIC_IPRIOR59")]
pub type R32PficIprior59 = crate::Reg<r32_pfic_iprior59::R32PficIprior59Spec>;
#[doc = "Interrupt Priority configuration Register 59"]
pub mod r32_pfic_iprior59 {
#[doc = "Register `R32_PFIC_IPRIOR59` reader"]
pub type R = crate::R<R32PficIprior59Spec>;
#[doc = "Register `R32_PFIC_IPRIOR59` writer"]
pub type W = crate::W<R32PficIprior59Spec>;
#[doc = "Field `IPRIOR59` reader - RW,Interrupt priority for number 236-239"]
pub type Iprior59R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR59` writer - RW,Interrupt priority for number 236-239"]
pub type Iprior59W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 236-239"]
#[inline(always)]
pub fn iprior59(&self) -> Iprior59R {
Iprior59R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 236-239"]
#[inline(always)]
pub fn iprior59(&mut self) -> Iprior59W<R32PficIprior59Spec> {
Iprior59W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 59\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior59::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior59::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior59Spec;
impl crate::RegisterSpec for R32PficIprior59Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior59::R`](R) reader structure"]
impl crate::Readable for R32PficIprior59Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior59::W`](W) writer structure"]
impl crate::Writable for R32PficIprior59Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR59 to value 0"]
impl crate::Resettable for R32PficIprior59Spec {}
}
#[doc = "R32_PFIC_IPRIOR60 (rw) register accessor: Interrupt Priority configuration Register 60\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior60::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior60::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior60`] module"]
#[doc(alias = "R32_PFIC_IPRIOR60")]
pub type R32PficIprior60 = crate::Reg<r32_pfic_iprior60::R32PficIprior60Spec>;
#[doc = "Interrupt Priority configuration Register 60"]
pub mod r32_pfic_iprior60 {
#[doc = "Register `R32_PFIC_IPRIOR60` reader"]
pub type R = crate::R<R32PficIprior60Spec>;
#[doc = "Register `R32_PFIC_IPRIOR60` writer"]
pub type W = crate::W<R32PficIprior60Spec>;
#[doc = "Field `IPRIOR60` reader - RW,Interrupt priority for number 240-243"]
pub type Iprior60R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR60` writer - RW,Interrupt priority for number 240-243"]
pub type Iprior60W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 240-243"]
#[inline(always)]
pub fn iprior60(&self) -> Iprior60R {
Iprior60R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 240-243"]
#[inline(always)]
pub fn iprior60(&mut self) -> Iprior60W<R32PficIprior60Spec> {
Iprior60W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 60\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior60::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior60::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior60Spec;
impl crate::RegisterSpec for R32PficIprior60Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior60::R`](R) reader structure"]
impl crate::Readable for R32PficIprior60Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior60::W`](W) writer structure"]
impl crate::Writable for R32PficIprior60Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR60 to value 0"]
impl crate::Resettable for R32PficIprior60Spec {}
}
#[doc = "R32_PFIC_IPRIOR61 (rw) register accessor: Interrupt Priority configuration Register 61\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior61::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior61::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior61`] module"]
#[doc(alias = "R32_PFIC_IPRIOR61")]
pub type R32PficIprior61 = crate::Reg<r32_pfic_iprior61::R32PficIprior61Spec>;
#[doc = "Interrupt Priority configuration Register 61"]
pub mod r32_pfic_iprior61 {
#[doc = "Register `R32_PFIC_IPRIOR61` reader"]
pub type R = crate::R<R32PficIprior61Spec>;
#[doc = "Register `R32_PFIC_IPRIOR61` writer"]
pub type W = crate::W<R32PficIprior61Spec>;
#[doc = "Field `IPRIOR61` reader - RW,Interrupt priority for number 244-247"]
pub type Iprior61R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR61` writer - RW,Interrupt priority for number 244-247"]
pub type Iprior61W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 244-247"]
#[inline(always)]
pub fn iprior61(&self) -> Iprior61R {
Iprior61R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 244-247"]
#[inline(always)]
pub fn iprior61(&mut self) -> Iprior61W<R32PficIprior61Spec> {
Iprior61W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 61\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior61::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior61::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior61Spec;
impl crate::RegisterSpec for R32PficIprior61Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior61::R`](R) reader structure"]
impl crate::Readable for R32PficIprior61Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior61::W`](W) writer structure"]
impl crate::Writable for R32PficIprior61Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR61 to value 0"]
impl crate::Resettable for R32PficIprior61Spec {}
}
#[doc = "R32_PFIC_IPRIOR62 (rw) register accessor: Interrupt Priority configuration Register 62\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior62::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior62::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior62`] module"]
#[doc(alias = "R32_PFIC_IPRIOR62")]
pub type R32PficIprior62 = crate::Reg<r32_pfic_iprior62::R32PficIprior62Spec>;
#[doc = "Interrupt Priority configuration Register 62"]
pub mod r32_pfic_iprior62 {
#[doc = "Register `R32_PFIC_IPRIOR62` reader"]
pub type R = crate::R<R32PficIprior62Spec>;
#[doc = "Register `R32_PFIC_IPRIOR62` writer"]
pub type W = crate::W<R32PficIprior62Spec>;
#[doc = "Field `IPRIOR62` reader - RW,Interrupt priority for number 248-251"]
pub type Iprior62R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR62` writer - RW,Interrupt priority for number 248-251"]
pub type Iprior62W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 248-251"]
#[inline(always)]
pub fn iprior62(&self) -> Iprior62R {
Iprior62R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 248-251"]
#[inline(always)]
pub fn iprior62(&mut self) -> Iprior62W<R32PficIprior62Spec> {
Iprior62W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 62\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior62::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior62::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior62Spec;
impl crate::RegisterSpec for R32PficIprior62Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior62::R`](R) reader structure"]
impl crate::Readable for R32PficIprior62Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior62::W`](W) writer structure"]
impl crate::Writable for R32PficIprior62Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR62 to value 0"]
impl crate::Resettable for R32PficIprior62Spec {}
}
#[doc = "R32_PFIC_IPRIOR63 (rw) register accessor: Interrupt Priority configuration Register 63\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior63::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior63::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_iprior63`] module"]
#[doc(alias = "R32_PFIC_IPRIOR63")]
pub type R32PficIprior63 = crate::Reg<r32_pfic_iprior63::R32PficIprior63Spec>;
#[doc = "Interrupt Priority configuration Register 63"]
pub mod r32_pfic_iprior63 {
#[doc = "Register `R32_PFIC_IPRIOR63` reader"]
pub type R = crate::R<R32PficIprior63Spec>;
#[doc = "Register `R32_PFIC_IPRIOR63` writer"]
pub type W = crate::W<R32PficIprior63Spec>;
#[doc = "Field `IPRIOR63` reader - RW,Interrupt priority for number 252-255"]
pub type Iprior63R = crate::FieldReader<u32>;
#[doc = "Field `IPRIOR63` writer - RW,Interrupt priority for number 252-255"]
pub type Iprior63W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 252-255"]
#[inline(always)]
pub fn iprior63(&self) -> Iprior63R {
Iprior63R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,Interrupt priority for number 252-255"]
#[inline(always)]
pub fn iprior63(&mut self) -> Iprior63W<R32PficIprior63Spec> {
Iprior63W::new(self, 0)
}
}
#[doc = "Interrupt Priority configuration Register 63\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_iprior63::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_iprior63::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficIprior63Spec;
impl crate::RegisterSpec for R32PficIprior63Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_iprior63::R`](R) reader structure"]
impl crate::Readable for R32PficIprior63Spec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_iprior63::W`](W) writer structure"]
impl crate::Writable for R32PficIprior63Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_IPRIOR63 to value 0"]
impl crate::Resettable for R32PficIprior63Spec {}
}
#[doc = "R32_PFIC_SCTLR (rw) register accessor: System Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_sctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_sctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_pfic_sctlr`] module"]
#[doc(alias = "R32_PFIC_SCTLR")]
pub type R32PficSctlr = crate::Reg<r32_pfic_sctlr::R32PficSctlrSpec>;
#[doc = "System Control Register"]
pub mod r32_pfic_sctlr {
#[doc = "Register `R32_PFIC_SCTLR` reader"]
pub type R = crate::R<R32PficSctlrSpec>;
#[doc = "Register `R32_PFIC_SCTLR` writer"]
pub type W = crate::W<R32PficSctlrSpec>;
#[doc = "Field `SLEEPONEXIT` reader - RW,SLEEPONEXIT"]
pub type SleeponexitR = crate::BitReader;
#[doc = "Field `SLEEPONEXIT` writer - RW,SLEEPONEXIT"]
pub type SleeponexitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLEEPDEEP` reader - RW,SLEEPDEEP"]
pub type SleepdeepR = crate::BitReader;
#[doc = "Field `SLEEPDEEP` writer - RW,SLEEPDEEP"]
pub type SleepdeepW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WFITOWFE` reader - RW,WFITOWFE"]
pub type WfitowfeR = crate::BitReader;
#[doc = "Field `WFITOWFE` writer - RW,WFITOWFE"]
pub type WfitowfeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEVONPEND` reader - RW,SEVONPEND"]
pub type SevonpendR = crate::BitReader;
#[doc = "Field `SEVONPEND` writer - RW,SEVONPEND"]
pub type SevonpendW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SETEVENT` reader - WO,SETEVENT"]
pub type SeteventR = crate::BitReader;
#[doc = "Field `SETEVENT` writer - WO,SETEVENT"]
pub type SeteventW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - RW,SLEEPONEXIT"]
#[inline(always)]
pub fn sleeponexit(&self) -> SleeponexitR {
SleeponexitR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RW,SLEEPDEEP"]
#[inline(always)]
pub fn sleepdeep(&self) -> SleepdeepR {
SleepdeepR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RW,WFITOWFE"]
#[inline(always)]
pub fn wfitowfe(&self) -> WfitowfeR {
WfitowfeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RW,SEVONPEND"]
#[inline(always)]
pub fn sevonpend(&self) -> SevonpendR {
SevonpendR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - WO,SETEVENT"]
#[inline(always)]
pub fn setevent(&self) -> SeteventR {
SeteventR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - RW,SLEEPONEXIT"]
#[inline(always)]
pub fn sleeponexit(&mut self) -> SleeponexitW<R32PficSctlrSpec> {
SleeponexitW::new(self, 1)
}
#[doc = "Bit 2 - RW,SLEEPDEEP"]
#[inline(always)]
pub fn sleepdeep(&mut self) -> SleepdeepW<R32PficSctlrSpec> {
SleepdeepW::new(self, 2)
}
#[doc = "Bit 3 - RW,WFITOWFE"]
#[inline(always)]
pub fn wfitowfe(&mut self) -> WfitowfeW<R32PficSctlrSpec> {
WfitowfeW::new(self, 3)
}
#[doc = "Bit 4 - RW,SEVONPEND"]
#[inline(always)]
pub fn sevonpend(&mut self) -> SevonpendW<R32PficSctlrSpec> {
SevonpendW::new(self, 4)
}
#[doc = "Bit 5 - WO,SETEVENT"]
#[inline(always)]
pub fn setevent(&mut self) -> SeteventW<R32PficSctlrSpec> {
SeteventW::new(self, 5)
}
}
#[doc = "System Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_pfic_sctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_pfic_sctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32PficSctlrSpec;
impl crate::RegisterSpec for R32PficSctlrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_pfic_sctlr::R`](R) reader structure"]
impl crate::Readable for R32PficSctlrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_pfic_sctlr::W`](W) writer structure"]
impl crate::Writable for R32PficSctlrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_PFIC_SCTLR to value 0"]
impl crate::Resettable for R32PficSctlrSpec {}
}
}
#[doc = "Systick register"]
pub type Systick = crate::Periph<systick::RegisterBlock, 0xe000_f000>;
impl core::fmt::Debug for Systick {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Systick").finish()
}
}
#[doc = "Systick register"]
pub mod systick {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
r32_stk_ctlr: R32StkCtlr,
r32_stk_sr: R32StkSr,
r32_stk_cntl: R32StkCntl,
_reserved3: [u8; 0x04],
r32_stk_cmplr: R32StkCmplr,
r32_stk_cmphr: R32StkCmphr,
}
impl RegisterBlock {
#[doc = "0x00 - Systick counter control register"]
#[inline(always)]
pub const fn r32_stk_ctlr(&self) -> &R32StkCtlr {
&self.r32_stk_ctlr
}
#[doc = "0x04 - Systick count status register"]
#[inline(always)]
pub const fn r32_stk_sr(&self) -> &R32StkSr {
&self.r32_stk_sr
}
#[doc = "0x08 - Systick counter low register"]
#[inline(always)]
pub const fn r32_stk_cntl(&self) -> &R32StkCntl {
&self.r32_stk_cntl
}
#[doc = "0x10 - Count reload/compare low register"]
#[inline(always)]
pub const fn r32_stk_cmplr(&self) -> &R32StkCmplr {
&self.r32_stk_cmplr
}
#[doc = "0x14 - Systick compare high register"]
#[inline(always)]
pub const fn r32_stk_cmphr(&self) -> &R32StkCmphr {
&self.r32_stk_cmphr
}
}
#[doc = "R32_STK_CTLR (rw) register accessor: Systick counter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_ctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_ctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_stk_ctlr`] module"]
#[doc(alias = "R32_STK_CTLR")]
pub type R32StkCtlr = crate::Reg<r32_stk_ctlr::R32StkCtlrSpec>;
#[doc = "Systick counter control register"]
pub mod r32_stk_ctlr {
#[doc = "Register `R32_STK_CTLR` reader"]
pub type R = crate::R<R32StkCtlrSpec>;
#[doc = "Register `R32_STK_CTLR` writer"]
pub type W = crate::W<R32StkCtlrSpec>;
#[doc = "Field `STE` reader - Systick counter enable"]
pub type SteR = crate::BitReader;
#[doc = "Field `STE` writer - Systick counter enable"]
pub type SteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STIE` reader - Systick counter interrupt enable"]
pub type StieR = crate::BitReader;
#[doc = "Field `STIE` writer - Systick counter interrupt enable"]
pub type StieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STCLK` reader - System counter clock Source selection"]
pub type StclkR = crate::BitReader;
#[doc = "Field `STCLK` writer - System counter clock Source selection"]
pub type StclkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STRE` reader - System counter reload control"]
pub type StreR = crate::BitReader;
#[doc = "Field `STRE` writer - System counter reload control"]
pub type StreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MODE` reader - counter mode"]
pub type ModeR = crate::BitReader;
#[doc = "Field `MODE` writer - counter mode"]
pub type ModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWIE` reader - RW0,System soft interrupt enable"]
pub type SwieR = crate::BitReader;
#[doc = "Field `SWIE` writer - RW0,System soft interrupt enable"]
pub type SwieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Systick counter enable"]
#[inline(always)]
pub fn ste(&self) -> SteR {
SteR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Systick counter interrupt enable"]
#[inline(always)]
pub fn stie(&self) -> StieR {
StieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - System counter clock Source selection"]
#[inline(always)]
pub fn stclk(&self) -> StclkR {
StclkR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - System counter reload control"]
#[inline(always)]
pub fn stre(&self) -> StreR {
StreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - counter mode"]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 31 - RW0,System soft interrupt enable"]
#[inline(always)]
pub fn swie(&self) -> SwieR {
SwieR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Systick counter enable"]
#[inline(always)]
pub fn ste(&mut self) -> SteW<R32StkCtlrSpec> {
SteW::new(self, 0)
}
#[doc = "Bit 1 - Systick counter interrupt enable"]
#[inline(always)]
pub fn stie(&mut self) -> StieW<R32StkCtlrSpec> {
StieW::new(self, 1)
}
#[doc = "Bit 2 - System counter clock Source selection"]
#[inline(always)]
pub fn stclk(&mut self) -> StclkW<R32StkCtlrSpec> {
StclkW::new(self, 2)
}
#[doc = "Bit 3 - System counter reload control"]
#[inline(always)]
pub fn stre(&mut self) -> StreW<R32StkCtlrSpec> {
StreW::new(self, 3)
}
#[doc = "Bit 4 - counter mode"]
#[inline(always)]
pub fn mode(&mut self) -> ModeW<R32StkCtlrSpec> {
ModeW::new(self, 4)
}
#[doc = "Bit 31 - RW0,System soft interrupt enable"]
#[inline(always)]
pub fn swie(&mut self) -> SwieW<R32StkCtlrSpec> {
SwieW::new(self, 31)
}
}
#[doc = "Systick counter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_ctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_ctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32StkCtlrSpec;
impl crate::RegisterSpec for R32StkCtlrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_stk_ctlr::R`](R) reader structure"]
impl crate::Readable for R32StkCtlrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_stk_ctlr::W`](W) writer structure"]
impl crate::Writable for R32StkCtlrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_STK_CTLR to value 0"]
impl crate::Resettable for R32StkCtlrSpec {}
}
#[doc = "R32_STK_SR (rw) register accessor: Systick count status register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_stk_sr`] module"]
#[doc(alias = "R32_STK_SR")]
pub type R32StkSr = crate::Reg<r32_stk_sr::R32StkSrSpec>;
#[doc = "Systick count status register"]
pub mod r32_stk_sr {
#[doc = "Register `R32_STK_SR` reader"]
pub type R = crate::R<R32StkSrSpec>;
#[doc = "Register `R32_STK_SR` writer"]
pub type W = crate::W<R32StkSrSpec>;
#[doc = "Field `CNTIF` reader - RW, CNTIF"]
pub type CntifR = crate::BitReader;
#[doc = "Field `CNTIF` writer - RW, CNTIF"]
pub type CntifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWIE` reader - RW, Enable software interrupt triggering"]
pub type SwieR = crate::BitReader;
#[doc = "Field `SWIE` writer - RW, Enable software interrupt triggering"]
pub type SwieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RW, CNTIF"]
#[inline(always)]
pub fn cntif(&self) -> CntifR {
CntifR::new((self.bits & 1) != 0)
}
#[doc = "Bit 31 - RW, Enable software interrupt triggering"]
#[inline(always)]
pub fn swie(&self) -> SwieR {
SwieR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RW, CNTIF"]
#[inline(always)]
pub fn cntif(&mut self) -> CntifW<R32StkSrSpec> {
CntifW::new(self, 0)
}
#[doc = "Bit 31 - RW, Enable software interrupt triggering"]
#[inline(always)]
pub fn swie(&mut self) -> SwieW<R32StkSrSpec> {
SwieW::new(self, 31)
}
}
#[doc = "Systick count status register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32StkSrSpec;
impl crate::RegisterSpec for R32StkSrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_stk_sr::R`](R) reader structure"]
impl crate::Readable for R32StkSrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_stk_sr::W`](W) writer structure"]
impl crate::Writable for R32StkSrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_STK_SR to value 0"]
impl crate::Resettable for R32StkSrSpec {}
}
#[doc = "R32_STK_CNTL (rw) register accessor: Systick counter low register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_stk_cntl`] module"]
#[doc(alias = "R32_STK_CNTL")]
pub type R32StkCntl = crate::Reg<r32_stk_cntl::R32StkCntlSpec>;
#[doc = "Systick counter low register"]
pub mod r32_stk_cntl {
#[doc = "Register `R32_STK_CNTL` reader"]
pub type R = crate::R<R32StkCntlSpec>;
#[doc = "Register `R32_STK_CNTL` writer"]
pub type W = crate::W<R32StkCntlSpec>;
#[doc = "Field `CNTL` reader - RW, CNTL"]
pub type CntlR = crate::FieldReader<u32>;
#[doc = "Field `CNTL` writer - RW, CNTL"]
pub type CntlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, CNTL"]
#[inline(always)]
pub fn cntl(&self) -> CntlR {
CntlR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, CNTL"]
#[inline(always)]
pub fn cntl(&mut self) -> CntlW<R32StkCntlSpec> {
CntlW::new(self, 0)
}
}
#[doc = "Systick counter low register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32StkCntlSpec;
impl crate::RegisterSpec for R32StkCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_stk_cntl::R`](R) reader structure"]
impl crate::Readable for R32StkCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_stk_cntl::W`](W) writer structure"]
impl crate::Writable for R32StkCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_STK_CNTL to value 0"]
impl crate::Resettable for R32StkCntlSpec {}
}
#[doc = "R32_STK_CMPLR (rw) register accessor: Count reload/compare low register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cmplr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cmplr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_stk_cmplr`] module"]
#[doc(alias = "R32_STK_CMPLR")]
pub type R32StkCmplr = crate::Reg<r32_stk_cmplr::R32StkCmplrSpec>;
#[doc = "Count reload/compare low register"]
pub mod r32_stk_cmplr {
#[doc = "Register `R32_STK_CMPLR` reader"]
pub type R = crate::R<R32StkCmplrSpec>;
#[doc = "Register `R32_STK_CMPLR` writer"]
pub type W = crate::W<R32StkCmplrSpec>;
#[doc = "Field `CNTH_CNPL` reader - RW,CNTH/CNPL"]
pub type CnthCnplR = crate::FieldReader<u32>;
#[doc = "Field `CNTH_CNPL` writer - RW,CNTH/CNPL"]
pub type CnthCnplW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW,CNTH/CNPL"]
#[inline(always)]
pub fn cnth_cnpl(&self) -> CnthCnplR {
CnthCnplR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW,CNTH/CNPL"]
#[inline(always)]
pub fn cnth_cnpl(&mut self) -> CnthCnplW<R32StkCmplrSpec> {
CnthCnplW::new(self, 0)
}
}
#[doc = "Count reload/compare low register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cmplr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cmplr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32StkCmplrSpec;
impl crate::RegisterSpec for R32StkCmplrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_stk_cmplr::R`](R) reader structure"]
impl crate::Readable for R32StkCmplrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_stk_cmplr::W`](W) writer structure"]
impl crate::Writable for R32StkCmplrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_STK_CMPLR to value 0"]
impl crate::Resettable for R32StkCmplrSpec {}
}
#[doc = "R32_STK_CMPHR (rw) register accessor: Systick compare high register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cmphr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cmphr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r32_stk_cmphr`] module"]
#[doc(alias = "R32_STK_CMPHR")]
pub type R32StkCmphr = crate::Reg<r32_stk_cmphr::R32StkCmphrSpec>;
#[doc = "Systick compare high register"]
pub mod r32_stk_cmphr {
#[doc = "Register `R32_STK_CMPHR` reader"]
pub type R = crate::R<R32StkCmphrSpec>;
#[doc = "Register `R32_STK_CMPHR` writer"]
pub type W = crate::W<R32StkCmphrSpec>;
#[doc = "Field `CMPH` reader - RW, Set the reload counter value to the lower 32 bits"]
pub type CmphR = crate::FieldReader<u32>;
#[doc = "Field `CMPH` writer - RW, Set the reload counter value to the lower 32 bits"]
pub type CmphW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RW, Set the reload counter value to the lower 32 bits"]
#[inline(always)]
pub fn cmph(&self) -> CmphR {
CmphR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RW, Set the reload counter value to the lower 32 bits"]
#[inline(always)]
pub fn cmph(&mut self) -> CmphW<R32StkCmphrSpec> {
CmphW::new(self, 0)
}
}
#[doc = "Systick compare high register\n\nYou can [`read`](crate::Reg::read) this register and get [`r32_stk_cmphr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r32_stk_cmphr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R32StkCmphrSpec;
impl crate::RegisterSpec for R32StkCmphrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`r32_stk_cmphr::R`](R) reader structure"]
impl crate::Readable for R32StkCmphrSpec {}
#[doc = "`write(|w| ..)` method takes [`r32_stk_cmphr::W`](W) writer structure"]
impl crate::Writable for R32StkCmphrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets R32_STK_CMPHR to value 0"]
impl crate::Resettable for R32StkCmphrSpec {}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "SYS"]
pub sys: Sys,
#[doc = "RTC"]
pub rtc: Rtc,
#[doc = "System_control"]
pub system_control: SystemControl,
#[doc = "CMP"]
pub cmp: Cmp,
#[doc = "KEYSCAN"]
pub keyscan: Keyscan,
#[doc = "GPIO"]
pub gpio: Gpio,
#[doc = "TMR"]
pub tmr: Tmr,
#[doc = "UART"]
pub uart: Uart,
#[doc = "SPI"]
pub spi: Spi,
#[doc = "I2C"]
pub i2c: I2c,
#[doc = "PWMx"]
pub pwmx: Pwmx,
#[doc = "USBFS"]
pub usbfs: Usbfs,
#[doc = "PFIC"]
pub pfic: Pfic,
#[doc = "Systick"]
pub systick: Systick,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
sys: Sys::steal(),
rtc: Rtc::steal(),
system_control: SystemControl::steal(),
cmp: Cmp::steal(),
keyscan: Keyscan::steal(),
gpio: Gpio::steal(),
tmr: Tmr::steal(),
uart: Uart::steal(),
spi: Spi::steal(),
i2c: I2c::steal(),
pwmx: Pwmx::steal(),
usbfs: Usbfs::steal(),
pfic: Pfic::steal(),
systick: Systick::steal(),
}
}
}