cge_nes 0.1.2

Cycle-accurate NES (Nintendo Entertainment System) emulator library: CPU, PPU, cartridge, input, and iNES ROM loading.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

//! PPU register types and submodules.
//!
//! Contains definitions for PPU register flags, the `Register` enum, and
//! submodules implementing register behavior and VRAM address handling.
use crate::ppu::registers::ppu_control::PpuControlFlags;
use crate::ppu::registers::ppu_mask::PpuMaskFlags;
use crate::ppu::registers::ppu_status::PpuStatus;
use ringbuffer::ConstGenericRingBuffer;

mod ppu_control;
mod ppu_mask;
mod ppu_status;
mod registers_impl;
mod vram_addr;

/// Enum representing the PPU's memory-mapped registers.
///
/// Each variant corresponds to a specific PPU register address.
/// Used for register selection and decoding.
#[derive(Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// PPU Control Register ($2000)
    PpuControl,
    /// PPU Mask Register ($2001)
    PpuMask,
    /// PPU Status Register ($2002)
    PpuStatus,
    /// OAM Address Register ($2003)
    OamAddr,
    /// OAM Data Register ($2004)
    OamData,
    /// PPU Scroll Register ($2005)
    PpuScroll,
    /// PPU Address Register ($2006)
    PpuAddr,
    /// PPU Data Register ($2007)
    Data,
}

impl From<u16> for Register {
    fn from(value: u16) -> Self {
        match value & 0b_0111 {
            0 => Register::PpuControl,
            1 => Register::PpuMask,
            2 => Register::PpuStatus,
            3 => Register::OamAddr,
            4 => Register::OamData,
            5 => Register::PpuScroll,
            6 => Register::PpuAddr,
            7 => Register::Data,
            _ => unreachable!(),
        }
    }
}

/// Holds the state of all PPU registers.
///
/// This struct contains the decoded values of the PPU's control, mask, status,
/// and data registers, as well as internal latches and write toggles.
#[derive(Clone, PartialEq, Eq)]
pub struct Registers {
    /// PPU Control Register flags.
    ppu_ctrl: PpuControlFlags,
    /// PPU Mask Register flags.
    ppu_mask: PpuMaskFlags,
    /// PPU Status Register flags.
    ppu_status: PpuStatus,
    /// OAM Address Register value.
    oam_addr: u8,
    /// OAM Data Register value.
    oam_data: u8,
    /// PPU Data Register value.
    data: u8,
    /// Current VRAM address (15-bit).
    v: u16,
    /// Temporary VRAM address (15-bit).
    t: u16,
    /// Fine x scroll value (3 bits)
    x: u8,

    /// Buffer to simulate the delay between toggling bg render
    show_bg_buffer: ConstGenericRingBuffer<bool, 4>,
    /// Buffer to simulate the delay between toggling sprites render
    show_sprites_buffer: ConstGenericRingBuffer<bool, 4>,

    /// shared write toggle for $2005/$2006 (false=first byte, true=second byte).
    write_second: bool,
}