celox 0.9.0

Celox HDL Simulator
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

use celox::BigUint;

#[path = "test_utils/mod.rs"]
#[macro_use]
mod test_utils;

all_backends! {

    fn test_wide_context_addition_carry(sim) {
        @case "wide_context_width::test_wide_context_addition_carry";
    }

    fn test_wide_context_subtraction_underflow(sim) {
        @case "wide_context_width::test_wide_context_subtraction_underflow";
    }

    fn test_wide_context_shift_left(sim) {
        @ignore_on(sv);
        @case "wide_context_width::test_wide_context_shift_left";
    }

    fn test_wide_context_constant_folding(sim) {
        @case "wide_context_width::test_wide_context_constant_folding";
    }

    fn test_wide_runtime_shift_width_behavior(sim) {
        @ignore_on(sv);
        @case "wide_context_width::test_wide_runtime_shift_width_behavior";
    }

    fn test_wide_context_constant_folding_128bit(sim) {
        @case "wide_context_width::test_wide_context_constant_folding_128bit";
    }

    fn test_wide_context_multiplication_boundary(sim) {
        @ignore_on(sv);
        @case "wide_context_width::test_wide_context_multiplication_boundary";
    }

    fn test_wide_context_addition_mixed_boundary(sim) {
        @case "wide_context_width::test_wide_context_addition_mixed_boundary";
    }
}

#[test]
fn test_wide_context_nested_propagation() {
    // (120-bit + 120-bit) * 2'd2 in 122-bit context
    let code = r#"
        module Top (
            a: input  logic<120>,
            b: input  logic<120>,
            o: output logic<122>
        ) {
            assign o = (a + b) * 2'd2;
        }
    "#;
    let code_top = "Top";
    let mut sim = celox::SimulatorBuilder::new(code, code_top)
        .build()
        .expect("Build should succeed");

    let a = sim.signal("a");
    let b = sim.signal("b");
    let o = sim.signal("o");

    // a = 2^119, b = 2^119
    // a + b = 2^120
    // (a + b) * 2 = 2^121
    let val_a = BigUint::from(1u32) << 119;
    let val_b = BigUint::from(1u32) << 119;
    let expected = BigUint::from(1u32) << 121;

    sim.modify(|io| {
        io.set_wide(a, val_a);
        io.set_wide(b, val_b);
    })
    .unwrap();
    assert_eq!(sim.get(o), expected, "Nested 122-bit context width failed");
}