---
source: crates/celox/tests/false_loop.rs
expression: sir_output
---
=== Evaluation Flip-Flops (eval_apply_ffs) ===
=== Evaluation Flip-Flops (eval_only_ffs) ===
=== Application Flip-Flops (apply_ffs) ===
=== Evaluation Combinational Logic (eval_comb) ===
Execution Unit 0:
Entry Block: 0
Registers:
r0: bit<64>
r1: bit<64>
r2: bit<64>
r3: bit<1>
r4: bit<1>
r5: bit<1>
r6: logic<1>
r7: bit<1>
r8: bit<1>
r9: bit<1>
r10: logic<1>
r11: bit<1>
r12: bit<1>
r13: bit<1>
r14: logic<1>
r15: bit<1>
r16: bit<1>
r17: bit<1>
r18: logic<1>
r19: bit<1>
r20: bit<1>
r21: bit<1>
r22: logic<1>
r23: bit<1>
r24: bit<1>
r25: bit<1>
r26: logic<1>
r27: bit<1>
r28: bit<1>
r29: bit<1>
r30: logic<1>
r31: bit<1>
r32: bit<1>
r33: bit<1>
r34: logic<1>
r35: bit<1>
r36: bit<1>
r37: bit<1>
r38: logic<1>
r39: bit<1>
r40: bit<1>
r41: bit<1>
r42: logic<1>
r43: bit<1>
r44: bit<1>
r45: bit<1>
r46: logic<1>
r47: bit<1>
r48: bit<1>
r49: bit<1>
r50: logic<1>
r51: bit<1>
r52: bit<1>
r53: bit<1>
r54: logic<1>
r55: bit<1>
r56: bit<1>
r57: bit<1>
r58: logic<1>
r59: bit<1>
r60: bit<1>
r61: bit<1>
r62: logic<1>
r63: bit<1>
r64: bit<1>
r65: bit<1>
r66: logic<1>
r67: bit<1>
r68: bit<1>
r69: bit<1>
r70: logic<1>
r71: bit<1>
r72: bit<1>
r73: bit<1>
r74: logic<1>
r75: logic<1>
r76: logic<1>
r77: bit<1>
r78: bit<1>
r79: bit<1>
r80: logic<1>
r81: bit<1>
r82: bit<1>
r83: bit<1>
r84: logic<1>
r85: bit<1>
r86: bit<1>
r87: bit<64>
r88: bit<64>
r89: logic<20>
r90: logic<4>
r91: logic<64>
r92: logic<64>
r93: logic<64>
r94: logic<64>
r95: logic<64>
r97: logic<20>
b0:
r0 = SIRValue(0x0)
r1 = SIRValue(0x3)
Jump(b1 [r0])
b1:
params: [r2]
r3 = r2 LtU r1
Branch(r3 ? b2 : b4)
b2:
r90 = Load(addr=v (region=0), offset=0, bits=4)
r9 = Load(addr=v (region=0), offset=4, bits=1)
r13 = Load(addr=v (region=0), offset=5, bits=1)
r17 = Load(addr=v (region=0), offset=6, bits=1)
r21 = Load(addr=v (region=0), offset=7, bits=1)
r25 = Load(addr=v (region=0), offset=8, bits=1)
r29 = Load(addr=v (region=0), offset=9, bits=1)
r33 = Load(addr=v (region=0), offset=10, bits=1)
r91 = SIRValue(0x3)
r92 = r90 Shr r91
r37 = Load(addr=v (region=0), offset=11, bits=1)
r93 = SIRValue(0x1)
r5 = r92 And r93
r94 = SIRValue(0x2)
r95 = r90 Shr r94
r6 = r95 And r93
r7 = r5 Ne r6
r11 = r9 Ne r6
r41 = Load(addr=v (region=0), offset=12, bits=1)
r12 = r7 Or r11
r15 = r13 Ne r6
r45 = Load(addr=v (region=0), offset=13, bits=1)
r16 = r12 Or r15
r19 = r17 Ne r6
r49 = Load(addr=v (region=0), offset=14, bits=1)
r20 = r16 Or r19
r23 = r21 Ne r6
r53 = Load(addr=v (region=0), offset=15, bits=1)
r24 = r20 Or r23
r27 = r25 Ne r6
r57 = Load(addr=v (region=0), offset=16, bits=1)
r28 = r24 Or r27
r31 = r29 Ne r6
r61 = Load(addr=v (region=0), offset=17, bits=1)
r32 = r28 Or r31
r35 = r33 Ne r6
r65 = Load(addr=v (region=0), offset=18, bits=1)
r36 = r32 Or r35
r39 = r37 Ne r6
r69 = Load(addr=v (region=0), offset=19, bits=1)
r40 = r36 Or r39
r43 = r41 Ne r6
r73 = Load(addr=v (region=0), offset=0, bits=1)
r44 = r40 Or r43
r47 = r45 Ne r6
r75 = Load(addr=i (region=0), offset=0, bits=1)
r48 = r44 Or r47
r51 = r49 Ne r6
r79 = Load(addr=v (region=0), offset=1, bits=1)
r52 = r48 Or r51
r55 = r53 Ne r6
r83 = Load(addr=v (region=0), offset=2, bits=1)
r56 = r52 Or r55
r59 = r57 Ne r6
r60 = r56 Or r59
r63 = r61 Ne r6
r64 = r60 Or r63
r67 = r65 Ne r6
r68 = r64 Or r67
r71 = r69 Ne r6
r72 = r68 Or r71
r76 = r6 Xor r75
r77 = r73 Ne r76
r78 = r72 Or r77
r81 = r79 Ne r76
r82 = r78 Or r81
r85 = r83 Ne r76
r86 = r82 Or r85
r97 = Concat(r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r6, r76, r76, r76)
Store(addr=v (region=0), offset=0, bits=20, src_reg = 97)
r87 = SIRValue(0x1)
r88 = r2 Add r87
Branch(r86 ? b1 [r88] : b3)
b3:
r89 = Load(addr=v (region=0), offset=0, bits=20)
Store(addr=o (region=0), offset=0, bits=20, src_reg = 89)
Return
b4:
Error(2000)