celox 0.4.1

Celox HDL Simulator
Documentation 
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module Module04 (
    clk: input clock,
    rst: input reset,
    a  : input logic<64>,
    b  : output logic<64>,
    c  : input logic,
) {
    always_ff (clk, rst) {
        if_reset {
            b = 0;
        } else {
            b = a;
        }
    }
}